TWI684344B - 用於使用多個連結的記憶體清單的方法及裝置 - Google Patents

用於使用多個連結的記憶體清單的方法及裝置 Download PDF

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Publication number
TWI684344B
TWI684344B TW104124865A TW104124865A TWI684344B TW I684344 B TWI684344 B TW I684344B TW 104124865 A TW104124865 A TW 104124865A TW 104124865 A TW104124865 A TW 104124865A TW I684344 B TWI684344 B TW I684344B
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Taiwan
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memory
linked
list
parallel
data
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TW104124865A
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Chinese (zh)
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TW201703475A (zh
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凡西 潘查努拉
索林 佩托
克勤 韓
札希 丹尼爾
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美商凱為有限責任公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9005—Buffering arrangements using dynamic buffer space allocation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/622—Queue service order
    • H04L47/6225—Fixed service order, e.g. Round Robin
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9015—Buffering arrangements for supporting a linked list

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
TW104124865A 2015-03-31 2015-07-31 用於使用多個連結的記憶體清單的方法及裝置 TWI684344B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/675,450 US10484311B2 (en) 2015-03-31 2015-03-31 Method and apparatus for using multiple linked memory lists
US14/675,450 2015-03-31

Publications (2)

Publication Number Publication Date
TW201703475A TW201703475A (zh) 2017-01-16
TWI684344B true TWI684344B (zh) 2020-02-01

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TW104124865A TWI684344B (zh) 2015-03-31 2015-07-31 用於使用多個連結的記憶體清單的方法及裝置

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US (2) US10484311B2 (enExample)
EP (1) EP3076621A1 (enExample)
JP (1) JP6535253B2 (enExample)
KR (1) KR102082020B1 (enExample)
CN (2) CN106209679B (enExample)
TW (1) TWI684344B (enExample)

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CN102984083B (zh) * 2012-11-19 2018-07-24 南京中兴新软件有限责任公司 队列管理方法及装置
US10484311B2 (en) * 2015-03-31 2019-11-19 Cavium, Llc Method and apparatus for using multiple linked memory lists
CN105162724B (zh) * 2015-07-30 2018-06-26 华为技术有限公司 一种数据入队与出队方法及队列管理单元
US10833843B1 (en) 2015-12-03 2020-11-10 United Services Automobile Association (USAA0 Managing blockchain access
KR101948988B1 (ko) * 2016-12-12 2019-02-15 주식회사 엘지유플러스 캐시를 이용한 파일 실행 방법 및 그 장치
CN108462646B (zh) * 2017-02-17 2020-08-25 华为技术有限公司 一种报文处理方法及装置
US10402320B1 (en) * 2018-02-27 2019-09-03 Oracle International Corporation Verifying the validity of a transition from a current tail template to a new tail template for a fused object
US10901887B2 (en) 2018-05-17 2021-01-26 International Business Machines Corporation Buffered freepointer management memory system
CN112311696B (zh) * 2019-07-26 2022-06-10 瑞昱半导体股份有限公司 网络封包接收装置及方法
US11240151B2 (en) * 2019-12-10 2022-02-01 Juniper Networks, Inc. Combined input and output queue for packet forwarding in network devices
CN113132449A (zh) * 2020-01-16 2021-07-16 京东方科技集团股份有限公司 一种调度方法、装置及设备
US11437081B2 (en) 2020-08-12 2022-09-06 Taiwan Semiconductor Manufacturing Company Limited Buffer control of multiple memory banks
US11043250B1 (en) * 2020-08-12 2021-06-22 Taiwan Semiconductor Manufacturing Company Limited Buffer control of multiple memory banks
CN112559400B (zh) * 2020-12-03 2024-07-09 南京盛科通信有限公司 多级调度装置、方法、网络芯片及计算机可读存储介质
CN116438787A (zh) * 2020-12-22 2023-07-14 华为技术有限公司 低延迟软件定义广域网架构
KR20220109213A (ko) 2021-01-28 2022-08-04 하준우 발코니 문
US20240126595A1 (en) * 2022-10-13 2024-04-18 Cortina Access, Inc. Method and apparatus for managing a queue and queue management device
KR102789200B1 (ko) * 2023-11-13 2025-03-31 리벨리온 주식회사 메모리 내 멀티 데이터 스트림을 단일 데이터 버퍼에 버퍼링하기 위한 직접 메모리 접근 장치 및 그의 동작 방법
CN119046186B (zh) * 2024-10-30 2025-03-14 合肥康芯威存储技术有限公司 一种存储器及缓存块的优化方法

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JP3117133B2 (ja) * 1999-02-16 2000-12-11 日本電気株式会社 フレーム組み立て回路及びフレーム組み立て方法
US7627870B1 (en) * 2001-04-28 2009-12-01 Cisco Technology, Inc. Method and apparatus for a data structure comprising a hierarchy of queues or linked list data structures
US20110016284A1 (en) * 2009-07-16 2011-01-20 Shreeharsha Balan Memory Management in Network Processors
US20120127860A1 (en) * 2010-11-18 2012-05-24 Cisco Technology, Inc. Dynamic Flow Redistribution for Head of Line Blocking Avoidance

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US7796627B2 (en) 2004-08-12 2010-09-14 Broadcom Corporation Apparatus and system for coupling and decoupling initiator devices to a network using an arbitrated loop without disrupting the network
JP4952642B2 (ja) 2008-04-15 2012-06-13 富士通株式会社 パケット転送装置およびパケット破棄方法
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CN101605100B (zh) * 2009-07-15 2012-04-25 华为技术有限公司 队列存储空间的管理方法和设备
JP2011254149A (ja) 2010-05-31 2011-12-15 Nippon Telegr & Teleph Corp <Ntt> 情報処理装置、情報処理方法およびプログラム
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US10484311B2 (en) * 2015-03-31 2019-11-19 Cavium, Llc Method and apparatus for using multiple linked memory lists

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JP3117133B2 (ja) * 1999-02-16 2000-12-11 日本電気株式会社 フレーム組み立て回路及びフレーム組み立て方法
US7627870B1 (en) * 2001-04-28 2009-12-01 Cisco Technology, Inc. Method and apparatus for a data structure comprising a hierarchy of queues or linked list data structures
US20110016284A1 (en) * 2009-07-16 2011-01-20 Shreeharsha Balan Memory Management in Network Processors
US20120127860A1 (en) * 2010-11-18 2012-05-24 Cisco Technology, Inc. Dynamic Flow Redistribution for Head of Line Blocking Avoidance

Also Published As

Publication number Publication date
US10484311B2 (en) 2019-11-19
CN113242186B (zh) 2024-12-24
US20160294735A1 (en) 2016-10-06
US20200044989A1 (en) 2020-02-06
CN106209679A (zh) 2016-12-07
JP6535253B2 (ja) 2019-06-26
KR20160117108A (ko) 2016-10-10
US11082366B2 (en) 2021-08-03
CN113242186A (zh) 2021-08-10
KR102082020B1 (ko) 2020-02-26
TW201703475A (zh) 2017-01-16
CN106209679B (zh) 2021-05-11
EP3076621A1 (en) 2016-10-05
JP2016195375A (ja) 2016-11-17

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