KR102082020B1 - 다수의 링크된 메모리 리스트들을 사용하기 위한 방법 및 장치 - Google Patents

다수의 링크된 메모리 리스트들을 사용하기 위한 방법 및 장치 Download PDF

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KR102082020B1
KR102082020B1 KR1020150067244A KR20150067244A KR102082020B1 KR 102082020 B1 KR102082020 B1 KR 102082020B1 KR 1020150067244 A KR1020150067244 A KR 1020150067244A KR 20150067244 A KR20150067244 A KR 20150067244A KR 102082020 B1 KR102082020 B1 KR 102082020B1
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memory
data
addresses
pointers
lists
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KR20160117108A (ko
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밤시 판차그누라
사우린 파텔
케퀸 한
자히 다니엘
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캐비엄, 엘엘씨
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9005—Buffering arrangements using dynamic buffer space allocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/622—Queue service order
    • H04L47/6225—Fixed service order, e.g. Round Robin
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9015—Buffering arrangements for supporting a linked list

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
KR1020150067244A 2015-03-31 2015-05-14 다수의 링크된 메모리 리스트들을 사용하기 위한 방법 및 장치 Active KR102082020B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/675,450 2015-03-31
US14/675,450 US10484311B2 (en) 2015-03-31 2015-03-31 Method and apparatus for using multiple linked memory lists

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KR20160117108A KR20160117108A (ko) 2016-10-10
KR102082020B1 true KR102082020B1 (ko) 2020-02-26

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US (2) US10484311B2 (enExample)
EP (1) EP3076621A1 (enExample)
JP (1) JP6535253B2 (enExample)
KR (1) KR102082020B1 (enExample)
CN (2) CN106209679B (enExample)
TW (1) TWI684344B (enExample)

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CN102984083B (zh) * 2012-11-19 2018-07-24 南京中兴新软件有限责任公司 队列管理方法及装置
US10484311B2 (en) * 2015-03-31 2019-11-19 Cavium, Llc Method and apparatus for using multiple linked memory lists
CN105162724B (zh) * 2015-07-30 2018-06-26 华为技术有限公司 一种数据入队与出队方法及队列管理单元
US10833843B1 (en) * 2015-12-03 2020-11-10 United Services Automobile Association (USAA0 Managing blockchain access
KR101948988B1 (ko) * 2016-12-12 2019-02-15 주식회사 엘지유플러스 캐시를 이용한 파일 실행 방법 및 그 장치
CN112087394B (zh) * 2017-02-17 2025-01-14 华为技术有限公司 一种报文处理方法及装置
US10402320B1 (en) * 2018-02-27 2019-09-03 Oracle International Corporation Verifying the validity of a transition from a current tail template to a new tail template for a fused object
US10901887B2 (en) 2018-05-17 2021-01-26 International Business Machines Corporation Buffered freepointer management memory system
CN112311696B (zh) * 2019-07-26 2022-06-10 瑞昱半导体股份有限公司 网络封包接收装置及方法
US11240151B2 (en) * 2019-12-10 2022-02-01 Juniper Networks, Inc. Combined input and output queue for packet forwarding in network devices
CN113132449A (zh) * 2020-01-16 2021-07-16 京东方科技集团股份有限公司 一种调度方法、装置及设备
US11437081B2 (en) 2020-08-12 2022-09-06 Taiwan Semiconductor Manufacturing Company Limited Buffer control of multiple memory banks
US11043250B1 (en) * 2020-08-12 2021-06-22 Taiwan Semiconductor Manufacturing Company Limited Buffer control of multiple memory banks
CN112559400B (zh) * 2020-12-03 2024-07-09 南京盛科通信有限公司 多级调度装置、方法、网络芯片及计算机可读存储介质
WO2022139808A1 (en) * 2020-12-22 2022-06-30 Futurewei Technologies, Inc. Low-latency software defined wide area network architecture
KR20220109213A (ko) 2021-01-28 2022-08-04 하준우 발코니 문
US20240126595A1 (en) * 2022-10-13 2024-04-18 Cortina Access, Inc. Method and apparatus for managing a queue and queue management device
KR102789200B1 (ko) * 2023-11-13 2025-03-31 리벨리온 주식회사 메모리 내 멀티 데이터 스트림을 단일 데이터 버퍼에 버퍼링하기 위한 직접 메모리 접근 장치 및 그의 동작 방법
CN119046186B (zh) * 2024-10-30 2025-03-14 合肥康芯威存储技术有限公司 一种存储器及缓存块的优化方法

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US20110016284A1 (en) * 2009-07-16 2011-01-20 Shreeharsha Balan Memory Management in Network Processors
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US7627870B1 (en) * 2001-04-28 2009-12-01 Cisco Technology, Inc. Method and apparatus for a data structure comprising a hierarchy of queues or linked list data structures
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US20050060509A1 (en) 2003-09-11 2005-03-17 International Business Machines Corporation System and method of squeezing memory slabs empty
US20090300320A1 (en) 2008-05-28 2009-12-03 Jing Zhang Processing system with linked-list based prefetch buffer and methods for use therewith
US20110016284A1 (en) * 2009-07-16 2011-01-20 Shreeharsha Balan Memory Management in Network Processors
US20120127860A1 (en) * 2010-11-18 2012-05-24 Cisco Technology, Inc. Dynamic Flow Redistribution for Head of Line Blocking Avoidance

Also Published As

Publication number Publication date
CN106209679B (zh) 2021-05-11
US20160294735A1 (en) 2016-10-06
US11082366B2 (en) 2021-08-03
CN106209679A (zh) 2016-12-07
US10484311B2 (en) 2019-11-19
JP2016195375A (ja) 2016-11-17
TWI684344B (zh) 2020-02-01
CN113242186A (zh) 2021-08-10
JP6535253B2 (ja) 2019-06-26
US20200044989A1 (en) 2020-02-06
KR20160117108A (ko) 2016-10-10
EP3076621A1 (en) 2016-10-05
TW201703475A (zh) 2017-01-16
CN113242186B (zh) 2024-12-24

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