TWI675413B - Method of wafer dicing - Google Patents

Abstract

An embodiment of the present invention provides a method for dicing a wafer, including: providing a wafer including a substrate, a plurality of dies formed in and on the substrate, and a dicing track structure located in a dicing area between adjacent dies; Remove the portion of the scribe lane structure around the test element; attach the front side of the wafer to the first tape; remove the portion of the substrate that overlaps the dicing area from the back side of the wafer; attach the back side of the wafer to A second adhesive tape; and removing the first adhesive tape and the remaining portion of the dicing track structure attached to the first adhesive tape so that a plurality of crystal grains are attached to the second adhesive tape separately.

Description

Method of dicing wafer

The present invention relates to a method for dicing a wafer, and in particular, to a method for dicing a wafer with a dicing track structure for removing the wafer in sections.

As the critical dimension of semiconductor devices shrinks, more grains can be formed on a single wafer. In this way, the time required to cut a wafer using a mechanical cutting process such as laser or knife cutting is greatly extended, so the manufacturing cost of a semiconductor element is also increased accordingly. Using plasma dicing to perform wafer dicing can effectively shorten the process time. However, if the test element group (TEG) in the scribe line contains materials that are not easily removed by dry etching or produce by-products that are not easily removed during the dry etching process, the plasma will be blocked. The cutting proceeds. In addition, it is more likely that the above-mentioned etching by-products need to be removed by a solution process, which may cause damage to the crystal grains.

The invention provides a method for dicing a wafer, which can avoid directly etching test elements that may contain metals that hinder the etching.

The method for dicing a wafer of the present invention includes: providing a wafer, wherein the wafer includes a substrate, a plurality of dies formed in the substrate and on the substrate, and a scribe line structure, and the scribe line structure is provided for dicing between adjacent dies. Within the region, the scribe line structure includes at least one insulating layer formed on the substrate and a test element formed in the at least one insulating layer; removing a portion of the at least one insulating layer located around the test element; and attaching the front side of the wafer to the first A tape, wherein the first tape contacts a plurality of dies and a remaining portion of the at least one insulating layer; a portion of the substrate that overlaps the cutting area is removed from the back side of the wafer; and the back side of the wafer is attached to the second tape ; And removing the first tape, the remaining portion of the at least one insulating layer attached to the first tape, and the test element, so that a plurality of dies are attached to the second tape separately.

Based on the above, the method for dicing a wafer according to an embodiment of the present invention includes removing a scribe line structure in a dicing area of a wafer in stages. The dicing track structure is disposed on the substrate and is located between adjacent grains. In the first stage, the part of the cutting track structure located in the peripheral area is removed. The peripheral area of the scribe line structure surrounds a central area with a test element. Next, in a second stage, the portion of the substrate that overlaps the entire cutting area is removed. Since the part of the cutting path structure located in the peripheral region and the part of the substrate overlapping the entire cutting path area have been removed, the remaining part of the cutting path structure (that is, the part located in the central region) can be disconnected from the crystal. Connection between grains. At this time, the remaining part of the scribe line structure is only attached to the tape, and is not directly connected to the die. Finally, in the third stage, the adhesive tape and the remainder of the cutting track structure attached to it are removed together. Therefore, it can be known that the method for cutting a wafer according to the embodiment of the present invention can avoid directly removing a test element that may contain a metal that hinders etching. Therefore, the method for dicing a wafer according to the embodiment of the present invention can be applied to plasma cutting. Compared to cutting a wafer by laser cutting or mechanical cutting, singulating multiple dies on a wafer by plasma cutting can greatly shorten the wafer cutting time, so the manufacturing cost can be greatly reduced.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

FIG. 1 is a flowchart of a method for dicing a wafer according to some embodiments of the present invention. 2A to 2P are schematic cross-sectional views of the structure of each intermediate stage of the method for dicing a wafer shown in FIG. 1.

Referring to FIG. 1 and FIG. 2A, step S100 is performed to provide a wafer W. The wafer W includes a substrate 100 and a plurality of dies D. In some embodiments, the substrate 100 may be a semiconductor substrate or a semiconductor on insulator (SOI) substrate. The semiconductor material in the semiconductor substrate and the SOI substrate may include an element semiconductor or an alloy semiconductor. For example, the element semiconductor may include Si or Ge. The alloy semiconductor may include SiGe, SiC, SiGeC, a group III-V semiconductor material, or a group II-VI semiconductor material. In some embodiments, the substrate 100 may be doped to a first conductivity type or a second conductivity type complementary to the first conductivity type. For example, the first conductivity type may be an N-type, and the second conductivity type may be a P-type. Each of the crystal grains D is formed on the substrate 100, and a part of the crystal grains D may be located in the substrate 100. The plurality of dies D may include an active device and a passive device to form an integrated circuit (not shown). In some embodiments, the integrated circuit includes a logic circuit, a memory circuit, an analog element circuit, the like, or a combination thereof. For brevity, these integrated circuits are not shown in FIGS. 2A to 2P. In some embodiments, the integrated circuits in the plurality of dies D may be the same as each other. In other embodiments, the integrated circuits in the plurality of dies D may be different from each other. In addition, each die D may further include a seal ring (not shown). The sealing ring surrounds the integrated circuit described above to absorb stress and protect the integrated circuit when the wafer W is cut.

The wafer W further includes a scribe line structure SLS. The scribe line structure SLS is disposed in the dicing area SLR between adjacent die D. In some embodiments, the width of the cutting region SLR ranges from 60 μm to 80 μm. In some embodiments, the cutting regions SLR between the plurality of dies D may be connected to each other and be continuous regions. The scribe line structure SLS includes one or more insulating layers 102. In some embodiments, the scribe line structure SLS includes a plurality of insulating layers 102, and the plurality of insulating layers 102 are stacked on the substrate 100. For example, the material of the insulating layer 102 may include silicon oxide, silicon nitride, a polymer, or a combination thereof. In addition, the scribe line structure SLS further includes a test element TE. The test element TE is formed in the multilayer insulating layer 102 and is located in the center region CR of the cutting region SLR. The peripheral region PR of the cutting region SLR is located between the central region CR and the adjacent die D, and no test element TE is formed therein. In other words, only the insulating layer 102 may be included in the central region CR of the cutting region SLR. In some embodiments, the width of the central region CR may range from 56 μm to 76 μm, and the width of the peripheral region PR may be greater than 2 μm.

In some embodiments, the test element TE may include multiple conductive vias 104 and multiple traces 106. Each conductive via 104 penetrates one of the multilayer insulation layers 102. Each of the traces 106 extends on one of the multilayer insulation layers 102 and is electrically connected to at least one of the plurality of conductive vias 104. In some embodiments, the test element TE further includes a pad P. The pad P is formed in the topmost insulating layer 102 and is electrically connected to the topmost conductive via 104. In some embodiments, the traces 106 and the pads P are made of a metal material, and the metal material is not easily removed by dry etching or a by-product that is not easily removed during the dry etching process. For example, the material of the traces 106 and the pads P may include aluminum or aluminum alloy. In addition, the material of the conductive via 104 may include tungsten.

Referring to FIG. 1 and FIGS. 2B to 2D, step S102 is performed to remove a portion of the scribe line structure SLS located in the peripheral region PR. In some embodiments, the portion of the scribe line structure SLS located in the peripheral region PR does not include the test element TE, and only includes a portion of the stacked structure formed by the multilayer insulation layer 102. In other words, in step S102, a portion of the multilayer insulating layer 102 located in the peripheral region PR is removed.

Referring to FIG. 2B, a method of removing a portion of the scribe line structure SLS located in the peripheral region PR may include forming a photoresist material layer (not shown) on the wafer W to substantially completely cover the wafer W. Then, the photoresist material layer is patterned by a lithography process to form a photoresist layer PR1 having an opening S1. The opening S1 exposes a peripheral region PR of the scribe line structure SLS.

Referring to FIG. 2C, the photoresist layer PR1 is used as a mask to remove the exposed portion of the scribe line structure SLS. In other words, a portion in the peripheral region PR of the scribe line structure SLS is removed, while a portion of the scribe line structure SLS located in the central area CR is retained. At this time, a gap is formed between the remaining portion of the scribe line structure SLS and the adjacent grain D. In some embodiments, a method of removing a portion of the scribe line structure SLS located in the peripheral region PR may include anisotropic etching, such as dry etching. Since the peripheral region PR of the scribe line structure SLS does not include the test element TE, there may be no metal material (such as aluminum) that hinders the etching process, and the above-mentioned portion of the scribe line structure SLS can be removed by the etching process smoothly. In some embodiments, the substrate 100 can serve as an etch stop layer. In other embodiments, the time of the etching process may be controlled to substantially completely remove the portion of the scribe line structure SLS located in the peripheral region PR.

Referring to FIG. 2D, the photoresist layer PR1 is removed. In this way, the front side FS of the wafer W can be exposed, that is, a plurality of dies D and the surface of the remaining portion of the scribe line structure SLS are exposed. In some embodiments, the method of removing the photoresist layer PR1 may include an ashing process. For example, the reactive gas used in the ashing process includes oxygen. In other embodiments, the photoresist layer PR1 may also be removed using a wet solution process.

Referring to FIG. 1 and FIG. 2E, in some embodiments, step S104 is performed to attach the polishing tape GTP to the front side FS of the wafer W. Herein, the front side FS of the wafer W refers to the surface of the die D and the scribe line structure SLS, and the back side BS of the wafer W refers to the surface of the substrate 100 relative to the die D and the scribe line structure SLS. In some embodiments, the polishing tape GTP can be attached to the front side FS of the wafer W after the structure shown in FIG. 2D is inverted. In some embodiments, after the abrasive tape GTP is attached to the front side FS of the wafer W, the abrasive tape GTP can be more closely adhered to the front side FS of the wafer W by, for example, a lamination method. In some embodiments, the abrasive tape GTP may extend into the gap between the die D and the remaining portion of the scribe line structure SLS, and partially fill the gap. In other embodiments, the abrasive tape GTP may also substantially completely fill the gap.

Referring to FIGS. 1 and 2F, in some embodiments, step S106 is performed to thin the substrate 100 from the back side BS of the wafer W. The substrate 100 can be thinned to a predetermined thickness. In some embodiments, this predetermined thickness may be substantially equal to the thickness of the substrate within the die D. In some embodiments, the thickness of the thinned substrate 100 may range from 50 μm to 300 μm. In some embodiments, the substrate 100 may be thinned by grinding or other methods.

Referring to FIGS. 1 and 2G, in some embodiments, step S108 is performed to attach the back side BS of the wafer W to the tape TP. At this time, the front side FS of the wafer W is attached to the polishing tape GTP, and the back side BS is attached to the tape TP. In some embodiments, the tape TP can be attached to the back side BS of the wafer W after the structure shown in FIG. 2F is inverted. In some embodiments, the tape TP is attached to the frame F.

Referring to FIG. 1 and FIG. 2H, in some embodiments, step S110 is performed to remove the abrasive tape GTP. In this way, the front side FS of the wafer W can be exposed, that is, the surfaces of the multiple dies D and the rest of the scribe line structure SLS are exposed. In some embodiments, the material of the abrasive tape GTP includes a photosensitive material. In these embodiments, the stickiness of the polishing tape GTP can be eliminated by irradiating the light, so that the polishing tape GTP can be smoothly peeled from the front side FS of the wafer W.

Referring to FIG. 1 and FIG. 2I, step S112 is performed to attach the front side of the wafer W to the first tape TP1. In some embodiments, the frame F connected to the tape TP may be attached to the first tape TP1 together with the wafer W. At this time, the back side BS of the wafer W is attached to the tape TP. On the other hand, the front side FS of the wafer is attached to the first tape TP1. In other words, the first tape TP1 is in contact with the surfaces of the plurality of dies D and in contact with the remaining portion of the scribe line structure SLS (that is, the portion of the scribe line structure SLS located in the central region CR). In some embodiments, the first tape TP1 may extend into the gap between the die D and the remaining portion of the scribe line structure SLS, and partially fill the gap. In other embodiments, the first tape TP1 may also substantially completely fill the gap.

Please refer to FIG. 1 and FIG. 2J. In some embodiments, step S114 is performed to remove the tape TP. In this way, the back side BS of the wafer W can be exposed. In some embodiments, the material of the tape TP includes a photosensitive material. In these embodiments, the adhesiveness of the tape TP can be eliminated by irradiating the light, so that the tape TP can be smoothly peeled from the back side BS of the wafer W. Before removing the tape TP or after removing the tape TP, the structure including the wafer W, the first tape TP1 and the frame F may be inverted so that the back side BS of the wafer W faces upward.

Referring to FIG. 1 and FIGS. 2K to 2M, step S116 is performed to remove the portion of the substrate 100 that overlaps the cutting region SLR from the back side BS of the wafer W. In some embodiments, a method of removing a portion of the substrate 100 overlapping the dicing region SLR from the backside BS of the wafer W may include sequentially performing sub-steps S116a to S116d.

Referring to FIG. 1 and FIG. 2K, a sub-step S116a is performed to form a photoresist layer PR2 on the back side BS of the wafer W. In some embodiments, the photoresist layer PR2 may be formed on the back side BS of the wafer W by spray coating. In addition, in some embodiments, the photoresist layer PR2 may substantially completely cover the back side BS of the wafer W.

Referring to FIG. 1 and FIG. 2L, sub-step S116b is performed to pattern the photoresist layer PR2. In this way, an opening S2 is formed in the photoresist layer PR2. The opening S2 exposes the back side BS of the substrate 100 and overlaps the cutting region SLR. In some embodiments, the edge of the opening S2 substantially cuts the sidewall of the die D.

Referring to FIG. 1 and FIG. 2M, a sub-step S116 c is performed, and the portion of the substrate 100 exposed by the opening S2 is removed using the patterned photoresist layer PR2 as a mask. In some embodiments, the portion of the substrate 100 overlapping the cutting region SLR is substantially completely removed to form the opening S3 in the substrate 100. The opening S3 exposes a portion of the scribe line structure SLS (including the insulating layer 102 and the test element TE) located in the central region CR. At this time, since the portion of the scribe line structure SLS located on the opposite sides of the center region CR (that is, the portion of the scribe line structure SLS located in the peripheral region PR) has been removed, the scribe line structure SLS is located in the center region CR The inner part is no longer directly connected to the die D, but is attached to the first tape TP1. Furthermore, since the structure located in the cutting region SLR has been removed or separated from the crystal grain D, a plurality of crystal grains D can be singulated. In some embodiments, a portion of the substrate 100 exposed by the opening S2 may be removed by a plasma dicing method. In some embodiments, the plasma cutting time can be adjusted to substantially completely remove the portion of the substrate 100 that overlaps the cutting region SLR. In other embodiments, the insulation layer 102 farthest from the first tape TP1 in the cutting region SLR may also be used as a stop layer for the plasma cutting process. In addition, in some embodiments, the plasma-etched etchant (also referred to as a reactive gas) includes a thiofluoride compound, but the present invention is not limited thereto.

Referring to FIG. 1 and FIG. 2N, a sub-step S116d is performed to remove the patterned photoresist layer PR2. In this way, the back side BS of the wafer W (that is, the back sides of the plurality of dies D) can be substantially completely exposed. In some embodiments, the method of removing the photoresist layer PR2 may include an ashing process. For example, the reactive gas used in the ashing process includes oxygen. In other embodiments, the photoresist layer PR2 may also be removed using a wet solution process.

Referring to FIG. 1 and FIG. 2O, step S118 is performed to attach the back side BS of the wafer W (that is, the back sides of the plurality of dies D) to the second tape TP2. In some embodiments, after the structure shown in FIG. 2N is inverted, the back side BS of the wafer W (that is, the back sides of the plurality of dies D) may be attached to the second tape TP2. In some embodiments, the frame F connected to the first tape TP1 may be attached to the second tape TP2 together with the wafer W. At this time, the front side FS of the wafer W (including the front sides of the multiple die D and the surface of the remaining portion of the scribe line structure SLS) is still attached to the first tape TP1, and the back side of the wafer W (that is, multiple The back side of the die D) is attached to the second tape TP2.

Referring to FIG. 1 and FIG. 2P, step S120 is performed to remove the first tape TP1. Since the remaining part of the scribe line structure SLS (the part located in the central region CR) is only attached to the first tape TP1 and is not directly connected to the die D, the cut is also removed when the first tape TP1 is removed. These parts of the track structure SLS. In other words, in step S120, the first tape TP1 and the remaining portion of the insulating layer 102 attached to the first tape TP1 and the test element TE are removed. At this time, the plurality of crystal grains D that are separately attached to the second tape TP2 are left. In some embodiments, the material of the first tape TP1 includes a photosensitive material. In these embodiments, the adhesiveness of the first tape TP1 can be eliminated by irradiating the light, so that the first tape TP1 can be smoothly peeled from the front side FS of the wafer W.

In some embodiments, after the first tape TP1 is removed, the plurality of dies D may be removed from the second tape TP2 by using the picking tool PT, respectively. Those with ordinary knowledge in the art may select a suitable picking tool according to requirements, and the present invention is not limited thereto. So far, the method for dicing a wafer according to some embodiments of the present invention has been completed. In addition, after the dicing of the wafer is completed, the subsequent packaging process may be performed on the removed die D.

In summary, the method for dicing a wafer according to an embodiment of the present invention includes removing a scribe line structure in a dicing area of a wafer in stages. The dicing track structure is disposed on the substrate and is located between adjacent grains. In the first stage, the part of the cutting track structure located in the peripheral area is removed. The peripheral area of the scribe line structure surrounds a central area with a test element. Next, in a second stage, the portion of the substrate that overlaps the entire cutting area is removed. Since the part of the cutting path structure located in the peripheral region and the part of the substrate overlapping the entire cutting path area have been removed, the remaining part of the cutting path structure (that is, the part located in the central region) can be disconnected from the crystal. Connection between grains. At this time, the remaining part of the scribe line structure is only attached to the tape, and is not directly connected to the die. Finally, in the third stage, the adhesive tape and the remainder of the cutting track structure attached to it are removed together. Therefore, it can be known that the method for cutting a wafer according to the embodiment of the present invention can avoid directly removing a test element that may contain a metal that hinders etching. Therefore, the method for dicing a wafer according to the embodiment of the present invention can be applied to plasma cutting. Compared to cutting a wafer by laser cutting or mechanical cutting, singulating multiple dies on a wafer by plasma cutting can greatly shorten the wafer cutting time, and therefore can greatly reduce manufacturing costs.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

100‧‧‧ substrate

102‧‧‧ Insulation

104‧‧‧ conductive via

106‧‧‧ Route

BS‧‧‧Back side

CR‧‧‧ Central Area

D‧‧‧ Grain

F‧‧‧Frame

FS‧‧‧Front

GTP‧‧‧ Abrasive Tape

P‧‧‧ pad

PR‧‧‧ Surrounding area

PR1, PR2‧‧‧Photoresistive layer

PT‧‧‧Pick up tool

S1, S2, S3‧‧‧ opening

S100, S102, S104, S106, S108, S110, S112, S114, S118, S120 ‧‧‧ steps

S116a, S116b, S116c, S116d‧‧‧ Substeps

SLR‧‧‧cut area

SLS‧‧‧Cutting Road Structure

TE‧‧‧Test Elements

TP‧‧‧Tape

TP1‧‧‧First tape

TP2‧‧‧Second Tape

W‧‧‧ Wafer

FIG. 1 is a flowchart of a method for dicing a wafer according to some embodiments of the present invention. 2A to 2P are schematic cross-sectional views of the structure of each intermediate stage of the method for dicing a wafer shown in FIG. 1.

Claims (10)

A method for dicing a wafer includes: providing a wafer, wherein the wafer includes a substrate, a plurality of dies formed in the substrate and on the substrate, and a scribe line structure, and the scribe line structure is disposed on a phase. In the cutting area between adjacent grains, the cutting track structure includes at least one insulating layer formed on the substrate and a test element formed in the at least one insulating layer; A portion located around the test element; attaching a front side of the wafer to a first tape, wherein the first tape contacts the plurality of dies and a remaining portion of the at least one insulating layer; Removing the portion of the base that overlaps the dicing area; attaching the back side of the wafer to a second tape; and removing the first tape and attaching to the first tape The remaining portion of the at least one insulating layer and the test element on a tape cause the plurality of crystal grains to be attached to the second tape separately. The method for dicing a wafer according to item 1 of the scope of patent application, wherein the method of removing the portion of the at least one insulating layer around the test element includes a lithography process and an etching process. According to the method for slicing a wafer according to item 1 of the scope of patent application, before attaching the front side of the wafer to the first tape, the method further includes: attaching an abrasive tape to the wafer. On the front side; thinning the substrate from the back side of the wafer; and removing the abrasive tape. The method for dicing a wafer according to item 3 of the patent application scope, before removing the abrasive tape, further comprising: attaching the back side of the wafer to the tape. The method for dicing a wafer according to item 4 of the scope of patent application, wherein after attaching the front side of the wafer to the first tape, the method further includes: removing the tape. The method for dicing a wafer according to item 4 of the scope of patent application, wherein the tape is connected to the same frame as the first tape. The method of dicing a wafer according to item 1 of the patent application scope, wherein the method of removing the portion of the substrate overlapping the dicing area from the back side of the wafer includes: Forming a photoresist layer on the back side of the wafer; patterning the photoresist layer to form an opening in the photoresist layer, the opening overlapping the cutting area; and using patterned light A resist layer is used as a mask to remove the portion of the substrate exposed by the opening; and removing the patterned photoresist layer. The method of dicing a wafer as described in claim 7 of the patent application scope, wherein the method of removing the portion of the substrate includes plasma dicing. The method for dicing a wafer as described in claim 1, wherein the test element includes aluminum. The method for dicing a wafer according to item 1 of the scope of patent application, wherein the first tape and the second tape are connected to the same frame.