JP2019169686A - Manufacturing method of element chip - Google Patents

Abstract

To provide a manufacturing method of semiconductor chip capable of restraining adhesion of debris to the surface of a substrate when executing laser scribe.SOLUTION: A division region is coated with resin 23 on the front 6A side of a semiconductor wafer 12 so as to reduce the step between an element region and the division region. Then, an adhesive tape 24 is stuck to the front side of the semiconductor wafer, and the division region is irradiated with a laser beam, thus forming an exposure part for exposing the division region of the semiconductor wafer, on the adhesive tape. Then, while holding the reverse face 4A of the semiconductor wafer by means of a dicing tape 22, the surface of the semiconductor is exposed to plasma, and while protecting the element region against plasma by means of the adhesive tape, the division region exposed to the exposure part is etched until reaching the reverse face 4A, thus individualizing the semiconductor wafer into multiple semiconductor chips. Finally, the adhesive tape, remaining on the surface 6A of the individualized semiconductor chips is removed.SELECTED DRAWING: Figure 1J

Description

  The present invention relates to a method for manufacturing an element chip.

  Plasma etching may be used to manufacture element chips. Applications of plasma etching are wide, and for example, a method called plasma dicing for separating a substrate into individual pieces is known as one of them. In plasma dicing of a substrate having a plurality of element regions defined by the divided regions, the divided regions are subjected to plasma etching from one surface of the substrate to the other surface, and the substrate is divided into individual device chips. In such plasma dicing, only the divided regions are plasma etched, and the element region needs to be protected from plasma etching. Therefore, generally, a plasma-resistant mask is formed on the surface of the element region before plasma etching. This mask is removed by ashing or the like after plasma dicing.

  Depending on the type of element chip, an evaluation device called a TEG (Test Element Group) may be formed in the divided region. In the manufacturing process of the element chip, various characteristic investigations are performed using the TEG, and actual device characteristics are monitored. Since TEG is generally made of a material containing a metal or an inorganic substance, it can hinder plasma dicing. Therefore, in this case, after the TEG is removed by cutting the divided region to a certain extent by laser scribing, the remaining portion may be plasma-diced. A method of manufacturing an element chip including such laser scribe and plasma dicing is disclosed in, for example, Patent Document 1. Patent Document 1 discloses a method of applying a resin formed in a film shape or a method of applying a liquid resin by spin coating as a method of forming a mask. The method of sticking a resin formed in a film has an advantage that it can be performed with relatively simple equipment as compared with a method of applying a liquid resin by spin coating.

Japanese Patent No. 5023614

  When laser scribing is performed, cutting waste called debris is generated. Normally, laser scribing is performed from above the mask as described in Patent Document 1, so that debris is prevented from adhering to the substrate surface. However, since there are various uneven parts such as electrodes on the surface of the element chip, it is difficult to attach the mask completely along the uneven part when pasting the resin formed in a film shape as a mask. is there. Therefore, a gap may be partially generated between the surface of the substrate and the mask. In particular, when the gap is generated in a divided region where laser scribing is performed, debris may enter the mask from the gap and adhere to the surface of the substrate. If debris excessively adheres to the surface of the substrate, the device chip becomes a defective product.

  An object of the present invention is to suppress debris from adhering to the surface of a substrate when laser scribing is performed in a method for manufacturing an element chip.

  The present invention includes a first surface and a second surface opposite to the first surface, and defines a plurality of element regions having electrodes on the first surface, and the element regions. A substrate comprising a divided region having a height lower than the element region is prepared, and the divided region on the first surface side of the substrate is reduced so as to reduce a step between the element region and the divided region. An exposed portion that applies resin to the substrate, affixes an adhesive tape to the first surface side of the substrate, irradiates the divided area with a laser beam, and exposes the divided area of the substrate to the adhesive tape. In a state where the second surface of the substrate is held by a holding member, the first surface of the substrate is exposed to plasma, and the element region is protected from the plasma by the adhesive tape, The divided area exposed to the exposed portion is the The method of manufacturing an element chip, comprising: etching the substrate until reaching the surface 2 to divide the substrate into a plurality of element chips, and removing the adhesive tape remaining on the surface of the singulated substrate. I will provide a.

  According to this method, the step between the element region and the divided region can be reduced by applying the resin to the divided region before performing laser scribing. In the substrate, since the height of the divided region is lower than the height of the element region, the step is reduced by filling the divided region having a low height with resin. By reducing the step, it is possible to increase the area where the adhesive tape adheres to the substrate when the adhesive tape is attached to the substrate. As a result, since laser scribing can be performed with the adhesive tape in close contact with the substrate, debris can be prevented from adhering to the surface of the substrate.

  The resin may have water solubility.

  According to this method, even if the resin is thick, the resin can be easily removed by washing with water after the substrate is separated into a plurality of element chips. Further, when the resin is removed by washing with the adhesive tape attached to the substrate via the resin, the adhesive tape can be removed together with the resin by washing with water.

  The adhesive tape may have water solubility.

  According to this method, the adhesive tape can be easily removed by washing with water after the substrate is separated into a plurality of element chips.

  ADVANTAGE OF THE INVENTION According to this invention, it can suppress that a debris adheres to the surface of a board | substrate when performing laser scribing in the manufacturing method of an element chip.

Sectional drawing which shows the 1st preparatory process of the manufacturing method of the element chip which concerns on 1st Embodiment. Sectional drawing which shows the 2nd preparatory process of the manufacturing method of the element chip which concerns on 1st Embodiment. Sectional drawing which shows the protection process of the manufacturing method of the element chip which concerns on 1st Embodiment. Sectional drawing which shows the thinning process of the manufacturing method of the element chip concerning 1st Embodiment. Sectional drawing which shows the 1st holding process of the manufacturing method of the element chip concerning 1st Embodiment. Sectional drawing which shows the 2nd holding process of the manufacturing method of the element chip concerning 1st Embodiment. Sectional drawing which shows the 1st mask formation process of the manufacturing method of the element chip concerning 1st Embodiment. Sectional drawing which shows the 2nd mask formation process of the manufacturing method of the element chip concerning 1st Embodiment. Sectional drawing which shows the laser scribing process of the manufacturing method of the element chip concerning 1st Embodiment. Sectional drawing which shows the isolation | separation process of the manufacturing method of the element chip which concerns on 1st Embodiment. Sectional drawing which shows the mask removal process of the manufacturing method of the element chip concerning 1st Embodiment. The top view of the semiconductor wafer which shows the positional relationship of each area | region in a laser scribing process. Sectional drawing which shows the comparative example of the 2nd mask formation process of 1st Embodiment. The schematic diagram of a plasma etching apparatus. The schematic block diagram of the manufacturing apparatus of an element chip. Sectional drawing which shows the 1st mask formation process of the manufacturing method of the element chip concerning 2nd Embodiment. Sectional drawing which shows the 2nd mask formation process of the manufacturing method of the element chip which concerns on 2nd Embodiment. Sectional drawing which shows the 3rd mask formation process of the manufacturing method of the element chip concerning 2nd Embodiment. Sectional drawing which shows the laser scribing process of the manufacturing method of the element chip which concerns on 2nd Embodiment. Sectional drawing which shows the isolation | separation process of the manufacturing method of the element chip which concerns on 2nd Embodiment. Sectional drawing which shows the mask removal process of the manufacturing method of the element chip concerning 2nd Embodiment.

  Embodiments of the present invention will be described below with reference to the accompanying drawings. The dimension of each part in an accompanying drawing is shown typically, and may differ from an actual thing.

(First embodiment)
1A to 1K show a manufacturing process of a semiconductor chip (element chip) 2 according to the first embodiment of the present invention. Referring to FIG. 1K, which is a completed drawing, the manufactured semiconductor chip 2 includes a semiconductor layer 4, a wiring layer 6 formed on the semiconductor layer 4, a protective film 8 formed on the wiring layer 6, and an electrode. The bump 10 is provided. The semiconductor layer 4 is made of, for example, Si or a Si-based material, and the wiring layer 6 is made of, for example, an insulating film such as SiO ₂ and a metal such as Cu. The material of the insulating film of the wiring layer 6 can be SiN, SiOC, Low-k material, or the like. The metal material of the wiring layer 6 can be Al, Al alloy, W, or the like. The wiring layer 6 also includes TEG. The metal contained in the bump 10 may be copper, an alloy of copper, tin, and silver, an alloy of silver and tin, an alloy of lead and tin, gold, aluminum, an aluminum alloy, or the like. The shape of the bump 10 is not particularly limited, and may be a prism, a cylinder, a mountain shape, a ball shape, or the like. The arrangement and number of the bumps 10 are not particularly limited, and are appropriately set according to the purpose.

  In the first preparation step shown in FIG. 1A, a semiconductor wafer (substrate) 12 is prepared. As shown in FIG. 1A, the semiconductor wafer 12 includes a semiconductor layer 4 and a wiring layer 6 formed on the semiconductor layer 4. The thickness of the semiconductor layer 4 is 5 μm, for example. The thickness of the wiring layer 6 is, for example, 50 μm.

  In the second preparation step shown in FIG. 1B, the protective film 8 and the bumps 10 are formed on the surface (first surface) 6A of the wiring layer 6 of the semiconductor wafer 12. The height of the bump 10 is, for example, 50 μm. The semiconductor wafer 12 that has undergone this step includes a plurality of element regions 14 on which the bumps 10 are formed, and divided regions 16 adjacent to the periphery of the individual element regions 14. In other words, the individual element regions 14 are defined by the divided regions 16.

  Comparing the height of the element region 14 and the height of the divided region 16, the height of the divided region 16 is lower due to the formation of the bump 10. In the present embodiment, such a height difference is caused by the bump 10, but there are various factors other than the bump 10, for example, other mounted components mounted on the surface of the semiconductor wafer 12. Depending on the height, a difference in height may occur. Further, when the semiconductor wafer 12 includes a CMOS image sensor or a MEMS element, a difference in height may occur depending on a lens included in the CMOS image sensor or a structure included in the MEMS element. Even when the height difference is caused by other mounting parts other than the bumps 10, the lens or the structure, it is sufficient that the height of the divided region 16 is lower than the height of the element region 14. Moreover, as long as the height of the divided region 16 is lower than the height of the element region 14, the form of the electrode is not limited to a convex shape such as the bump 10, and may be a concave shape such as a pad.

  In the protection process shown in FIG. 1C, a BG (back grind) tape 20 is attached to the front surface 6A of the semiconductor wafer 12 for protection during grinding of the back surface 4A. 1C is shown upside down with respect to FIGS. 1A and 1B. The BG tape 20 is a protective film composed of an adhesive layer 20A and a resin base layer 20B. That is, the adhesive layer 20A is attached to the surface 6A of the semiconductor wafer 12, and the surface 6A of the semiconductor wafer 12 is protected by the base material layer 20B. Since the BG tape 20 is cut in accordance with the outer shape of the semiconductor wafer 12 after being attached to the semiconductor wafer 12 or before being attached, the handling property of the semiconductor wafer 12 is not impaired.

  1D, the semiconductor layer 4 is ground from the back surface (second surface) 4A side of the semiconductor wafer 12 by a grinding apparatus (not shown). The semiconductor wafer 12 is thinned to a predetermined thickness by grinding the semiconductor layer 4.

  In the first holding step shown in FIG. 1E, a dicing tape (holding member) 22 is attached to the back surface 4 </ b> A of the semiconductor wafer 12. 1E is shown upside down with respect to FIGS. 1C and 1D. The dicing tape 22 is a holding film composed of an adhesive layer 22A and a resin base layer 22B. The adhesive layer 22A is attached to the back surface 4A of the semiconductor wafer 12, and the semiconductor wafer 12 is held by the base material layer 22B. Further, a frame 22C is attached to the dicing tape 22 from the viewpoint of handling properties.

  In the second holding step shown in FIG. 1F, the BG tape 20 is peeled off from the semiconductor wafer 12 and removed. In a state where the BG tape 20 is removed, the bumps 10 are exposed on the surface 6A of the semiconductor wafer 12.

  In the first mask formation step shown in FIG. 1G, a water-soluble resin 23 is applied on the surface of the semiconductor wafer 12. The resin 23 is applied to reduce the level difference on the surface of the semiconductor wafer 12. As a method for applying the resin 23, spray coating or spin coating can be employed. In the present embodiment, since the bump 10 is formed in the element region 14, the height of the element region 14 is higher than the height of the divided region 16. Therefore, in order to reduce the level difference, it is necessary to apply the resin 23 to at least the divided region 16. In the example of FIG. 1G, spin coating is employed as a method for applying the resin 23, and the resin 23 is applied to the entire surface 6A of the semiconductor wafer 12. At this time, the thickness of the resin 23 formed particularly on the bumps 10 in the element region 14 is thinner than the thickness of the resin 23 formed in the divided region 16, so that the step on the semiconductor wafer 12 is reduced. Instead of this, the resin may be applied only to the divided region 16 by a spray nozzle or a dispenser.

  In the second mask forming step shown in FIG. 1H, a water-soluble adhesive tape 24 is pressed and pasted on the surface 6A of the semiconductor wafer 12. The thickness of the adhesive tape 24 is about 5 to 50 μm, and for example, 20 μm in this embodiment. The adhesive tape 24 has a two-layer structure including a base material layer 24 </ b> A serving as a base and an adhesive layer 24 </ b> B attached to the semiconductor wafer 12. In the present embodiment, both the base material layer 24A and the adhesive layer 24B have water solubility. The adhesive tape 24 (particularly the base material layer 24A) has plasma resistance. Therefore, the portion of the semiconductor wafer 12 to which the adhesive tape 24 is attached is protected from later plasma etching. That is, the adhesive tape 24 functions as a mask against plasma.

  FIG. 2 is a cross-sectional view when the second mask forming step is executed without virtually passing through the first mask forming step. Comparing FIG. 1H with FIG. 2, in FIG. 2, a gap S is generated between the periphery of the bump 10 and the adhesive tape 24, whereas in FIG. Even if the gap S is generated, it is relatively small. Therefore, by performing the first mask forming step, the generation of the gap S can be suppressed or the gap S can be reduced. In the illustrated example, the air gap S is generated due to the step formed by the bump 10 protruding from the surface 6 </ b> A of the semiconductor wafer 12. For example, the height difference can be formed by other mounting parts mounted on the surface of the semiconductor wafer 12. Further, when the semiconductor wafer 12 includes a CMOS image sensor or a MEMS element, the height difference can be formed also by a lens provided in the CMOS image sensor or a structure provided in the MEMS element. Therefore, in practice, the air gap S can be generated not only around the bump 10 as shown in the figure but also in various modes.

  The gap S generated in the divided region 16 is preferably as small as possible and does not affect the subsequent steps. Therefore, after the adhesive tape 24 is pasted, in consideration of the possibility that the gap S is generated, only the divided region 16 is further pressed, or the thermoplastic adhesive tape 24 is used and heat is applied to the adhesive tape 24. The gap S may be reduced by pressing after softening. In addition, after the adhesive tape 24 has been applied, the semiconductor wafer 12 is put into the vacuum chamber and the pressure is reduced stepwise, whereby the air in the gap S is removed, the gap S is reduced, and the gap S is reduced. May be.

  In the laser scribing step shown in FIG. 1I, the exposed portion 18 is formed by cutting the adhesive tape 24, the resin 23, and the semiconductor wafer 12 by laser scribing at a portion corresponding to the divided region 16 (see FIG. 1H). Specifically, the exposed portion 18 is formed by cutting the wiring layer 6, the protective film 8, the resin 23, and the adhesive tape 24 by irradiating them with a laser beam. At this time, the semiconductor layer 4 may be partially cut or not cut, but not completely cut. Therefore, when the semiconductor wafer 12 is viewed from the surface 6A side, the semiconductor layer 4 is exposed at the exposed portion 18.

  FIG. 3 is a plan view of the semiconductor wafer 12 showing the positional relationship between the regions 14 and 16 in the laser scribing process. As shown in the drawing, on the semiconductor wafer 12, there are provided street-like divided regions 16 extending vertically and horizontally and rectangular element regions 14 defined by the divided regions 16. The width w1 of the element region 14 is, for example, 200 μm to 50 mm. The width w2 of the divided region 16 is about 20 to 80 μm, and is 50 μm in the present embodiment, for example. A plurality of bumps 10 are arranged in the element region 14. The arrangement of the bumps 10 is not necessarily regular, and may be various arrangements as in the illustrated example.

  A wiring pattern called a seal ring 14B is formed on the outer edge portion of the element region 14. The seal ring 14B is for suppressing the peeling of the wiring layer 6 after the singulation process described later, and suppresses the progress of the peeling to the inside when the peeling occurs at the boundary between the wiring layers 6. It has a function. Since the outer edge portion of the element region 14 is thus formed by the seal ring 14B, the divided region 16 can also be referred to as a region outside the seal ring 14B.

  In the divided region 16 of FIG. 3, the locus of the laser beam irradiated in the laser scribing process is schematically shown (see reference LB). The beam diameter is, for example, 5 to 20 μm, which is sufficiently smaller than the width w2 of the divided region 16. The laser is irradiated while moving linearly within the divided region 16. Laser irradiation may be performed in one row or two or more rows.

  As in the comparative example shown in FIG. 2, the adhesive tape 24 is not necessarily in close contact with the entire divided region 16, and a gap S is generated in the divided region 16 between the adhesive tape 24 and the semiconductor wafer 12. Sometimes. In the laser scribing step, the divided region 16 is irradiated with laser to form the exposed portion 18 (see FIG. 1I). Preferably, the divided region 16 to which the adhesive tape 24 is in close contact is irradiated with laser. If the region where the gap S exists in the divided region 16 is irradiated with laser, the end of the adhesive tape 24 may be peeled off from the surface 6A of the semiconductor wafer 12 when the adhesive tape 24 is cut by the laser. Then, debris (cutting waste) enters between the adhesive tape 24 and the semiconductor wafer 12 from the peeled portion, and the debris may adhere to the surface 6 </ b> A of the semiconductor wafer 12. In order to suppress this, in the present embodiment, the resin 23 is applied to the semiconductor wafer 12 in the first mask forming step, and the generation of the gap S (see FIG. 2) in the second mask forming step is suppressed. Laser is irradiated so that the adhesive tape 24 is not peeled off.

  In the singulation process shown in FIG. 1J, the semiconductor wafer 12 is singulated by plasma etching (plasma dicing) with the back surface 4A of the semiconductor wafer 12 held by the dicing tape 22. Further, FIG. 2 shows an example of a dry etching apparatus (plasma etching apparatus) 50 used in this step. A dielectric window is provided at the top of the chamber 52 of the dry etching apparatus 50, and an antenna 54 as an upper electrode is disposed above the dielectric window. The antenna 54 is electrically connected to the first high frequency power supply unit 56. On the other hand, a stage 60 on which the semiconductor wafer 12 is disposed is disposed on the bottom side of the processing chamber 58 in the chamber 52. The stage 60 also functions as a lower electrode and is electrically connected to the second high frequency power supply unit 62. The stage 60 includes an electrostatic chucking electrode (ESC electrode) (not shown) so that the dicing tape 22 (that is, the semiconductor wafer 12) placed on the stage 60 can be electrostatically chucked to the stage 60. Alternatively, a vacuum suction mechanism may be employed, and the dicing tape 22 (that is, the semiconductor wafer 12) placed on the stage 60 may be vacuum-sucked to the stage 60. The stage 60 is provided with a cooling gas hole (not shown) for supplying a cooling gas, and is electrostatically adsorbed to the stage 60 by supplying a cooling gas such as helium from the cooling gas hole. The semiconductor wafer 12 can be cooled. The gas inlet 64 of the chamber 52 is fluidly connected to an etching gas source 66, and the exhaust port 68 is connected to a vacuum exhaust unit 70 including a vacuum pump for evacuating the chamber 52.

In this singulation process, the semiconductor wafer 12 is placed on the stage 60 via the dicing tape 22, the inside of the processing chamber 58 is evacuated by the evacuation unit 70, and, for example, SF is supplied from the etching gas source 66 into the processing chamber 58. _The etching gas which is ₆ is supplied. Then, the inside of the processing chamber 58 is maintained at a predetermined pressure, high frequency power is supplied from the first high frequency power supply unit 56 to the antenna 54, plasma is generated in the processing chamber 58, and the semiconductor wafer 12 is irradiated. At this time, the semiconductor layer 4 of the semiconductor wafer 12 exposed at the exposed portion 18 is removed by the physicochemical action of radicals and ions in the plasma. Through this singulation process, the semiconductor wafer 12 is formed into individual rectangular semiconductor chips 2.

  In the mask removing process shown in FIG. 1K, the adhesive tape 24 and the resin 23 as a mask are removed from the surface 6A of the semiconductor chip 2. In this embodiment, since both the adhesive tape 24 and the resin 23 have water solubility, they are removed together by washing with water. As a material for the water-soluble adhesive tape 24 and the resin 23, a synthetic resin containing polyvinyl alcohol, oxazole and lithium styrenesulfonate, polyester, or the like can be used.

  Further, even when only the resin 23 is water-soluble and the adhesive tape 24 is water-insoluble, it can be removed by washing with water. When the resin 23 is removed by washing with the water-insoluble adhesive tape 24 attached to the semiconductor wafer 12 via the water-soluble resin 23, the adhesive tape 24 and the resin 23 can be removed by washing with water.

  Further, when both the adhesive tape 24 and the resin 23 are water-insoluble, the adhesive tape 24 and the resin 23 may be removed by ashing instead of washing with water. Specifically, a gas type different from the plasma etching in the singulation process is used, the adhesive tape 24 and the resin 23 that react to the gas type are used, and the adhesive tape 24 and the resin 23 are removed together by etching. May be. Alternatively, the adhesive tape 24 and the resin 23 may be mechanically peeled off, but it takes time to peel the adhesive tape 24 one by one from each individual semiconductor chip 2, so that Thus, it is preferable that the adhesive tape 24 and the resin 23 can be removed together by ashing.

  In this way, the semiconductor chip 2 is manufactured through the steps of FIGS.

  FIG. 5 shows a semiconductor chip (element chip) manufacturing apparatus 100 that performs the series of steps described above. The manufacturing apparatus 100 includes a carry-in / out unit 110, a first mask forming unit 120, a second mask forming unit 130, a laser scribing unit 140, an individualizing unit 150, a mask removing unit 160, and a transport mechanism 170. And a control device 180. The semiconductor wafer 12 is transferred between the units 110 to 160 by the transfer mechanism 170.

  The semiconductor wafer 12 that has undergone the first preparation process, the second preparation process, the protection process, the thinning process, the first holding process, and the second holding process is carried into the carry-in / out section 110. The loaded semiconductor wafer 12 is transferred to the first mask forming unit 120 and a mask forming process is executed. Next, the semiconductor wafer 12 is transferred to the second mask forming unit 130, and a second mask forming process is performed. Next, the semiconductor wafer 12 is transferred to the laser scribe unit 140, and a laser scribe process is performed. Next, the semiconductor wafer 12 is transferred to the singulation unit 150, and the singulation process is executed. Next, the semiconductor wafer 12 is transferred to the mask removal unit 160, and a mask removal process is performed. After all these steps are completed, the semiconductor wafer 12 is taken out from the loading / unloading unit 110 as the semiconductor chip 2.

  According to the present embodiment, the step between the element region 14 and the divided region 16 can be reduced by applying the resin 23 to the divided region 16 before performing laser scribing. In the semiconductor wafer 12, since the height of the divided region 16 is lower than the height of the element region 14, the step is reduced by filling the divided region 16 having a low height with the resin 23. By reducing the level difference, the area where the adhesive tape 24 is in close contact with the semiconductor wafer 12 when the adhesive tape 24 is attached to the semiconductor wafer 12 can be increased. As a result, laser scribing can be performed with the adhesive tape 24 in close contact with the semiconductor wafer 12, so that debris can be prevented from adhering to the surface 6 </ b> A of the semiconductor wafer 12.

  Moreover, according to this embodiment, since the resin 23 and the adhesive tape 24 are both water-soluble, even if the adhesive tape 24 and the resin 23 are thick, the adhesive tape 24 and the resin 23 are washed with water after the singulation process. Can be easily removed.

(Second Embodiment)
6A to 6F show each manufacturing process in the method of creating the semiconductor chip (element chip) 2 according to the second embodiment. 6A to 6F respectively show a first mask forming process, a second mask forming process, a third mask forming process, a laser scribing process, an individualizing process, and a mask removing process. Note that the first preparation process, the second preparation process, the protection process, the thinning process, the first holding process, and the second holding process in the first embodiment are executed in the same manner as in the first embodiment. However, since the content is the same, the description is omitted. In the first mask forming process, the second mask forming process, the third mask forming process, the laser scribing process, the singulation process, and the mask removing process, the description of the same parts as in the first embodiment is omitted. There is a case.

  In the first mask formation step shown in FIG. 6A, a water-soluble resin 23 is applied on the surface of the semiconductor wafer 12. The resin 23 is applied to reduce the level difference on the surface of the semiconductor wafer 12. Preferably, the material of the resin 23 is highly adhesive to the adhesive layer 24B described later. Specifically, the adhesive strength between the resin 23 and the adhesive layer 24B is preferably higher than the adhesive strength between the base material layer 24A and the adhesive layer 24B described later.

  In the second mask formation step shown in FIG. 6B, the adhesive tape 24 is attached to the surface 6A of the semiconductor wafer 12. The thickness of the adhesive tape 24 is about 5 to 50 μm, and for example, 20 μm in this embodiment. The adhesive tape 24 has a two-layer structure including a base material layer 24 </ b> A serving as a base and an adhesive layer 24 </ b> B attached to the semiconductor wafer 12. In the two-layer structure, the base material layer 24A can be easily peeled from the adhesive layer 24B.

  In the third mask formation step shown in FIG. 6C, the base material layer 24A of the adhesive tape 24 is peeled off. Specifically, only the base material layer 24A is removed with the adhesive layer 24B left. At this time, as the adhesive force between the resin 23 and the adhesive layer 24B is higher than the adhesive force between the base material layer 24A and the adhesive layer 24B, the adhesive layer 24B is left on the semiconductor wafer 12 and the base material layer 24A. Can be easily peeled off from the adhesive layer 24B. Hereinafter, the remaining adhesive layer 24 </ b> B is also simply referred to as an adhesive tape 24. In the present embodiment, the adhesive layer 24B has water solubility and plasma resistance. Therefore, the portion of the semiconductor wafer 12 to which the adhesive layer 24B is attached is protected from later plasma etching. That is, the adhesive layer 24B functions as a mask for plasma. In addition, about the base material layer 24A of the adhesive tape 24, since it removes at this process, it does not specifically limit about a material, The thing of arbitrary materials can be used.

  The laser scribing process shown in FIG. 6D, the singulation process shown in FIG. 6E, and the mask removal process shown in FIG. 6F are the same as those in the first embodiment except that the adhesive tape 24 is only the adhesive layer 24B. is there.

  The element chip manufacturing method according to the present embodiment is executed by the same manufacturing apparatus 100 as in the first embodiment (see FIG. 5). However, the processing is different from that of the first embodiment in that both the second mask forming step and the third mask forming step are performed in the second mask forming unit 130.

  According to this embodiment, the adhesive tape 24 is only the adhesive layer 24B after the second mask forming step. Therefore, as compared with the first embodiment, since only the adhesive layer 24B has to be removed in the mask removing process, the process is simpler than that of the first embodiment, and the remaining adhesive tape 24 can be suppressed.

2 Semiconductor chip (element chip)
4 Semiconductor layer 4A Back surface (second surface)
6 Wiring layer 6A Surface (first surface)
8 Protective film 10 Bump 12 Semiconductor wafer (substrate)
DESCRIPTION OF SYMBOLS 14 Element area | region 14B Seal ring 16 Dividing area | region 18 Exposed part 20 BG tape 20A Adhesive layer 20B Base material layer 22 Dicing tape (holding member)
22A Adhesive Layer 22B Base Material Layer 22C Frame 23 Resin 24 Adhesive Tape 24A Base Material Layer 24B Adhesive Layer 50 Dry Etching Device 52 Chamber 54 Antenna 56 First High Frequency Power Supply Unit 58 Processing Chamber 60 Stage 62 Second High Frequency Power Supply Unit 64 Gas Inlet 66 Etching gas source 68 Exhaust port 70 Vacuum exhaust part 100 Semiconductor chip (element chip) manufacturing apparatus 110 Loading / unloading part 120 First mask forming part 130 Second mask forming part 140 Laser scribing part 150 Divided part 160 Mask removing part 170 Transport mechanism

Claims (3)

A first surface and a second surface opposite to the first surface; and a plurality of element regions having electrodes on the first surface; and defining the element region; Preparing a substrate with a divided region having a low height,
Applying a resin to the divided region on the first surface side of the substrate so as to reduce a step between the element region and the divided region;
Affixing an adhesive tape to the first surface side of the substrate;
Irradiating the divided area with a laser beam to form an exposed portion that exposes the divided area of the substrate on the adhesive tape;
In the state where the second surface of the substrate is held by a holding member, the first surface of the substrate is exposed to plasma, and the element region is protected from the plasma by the adhesive tape, while being exposed to the exposed portion. Etching the exposed divided area until it reaches the second surface, thereby dividing the substrate into a plurality of element chips,
A method for producing an element chip, comprising: removing the adhesive tape remaining on the surface of the substrate that has been separated into pieces.   The method for manufacturing an element chip according to claim 1, wherein the resin has water solubility.   The manufacturing method of the element chip of Claim 1 or Claim 2 with which the said adhesive tape is provided with water solubility.

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