CN111180322B - Method for cutting wafer - Google Patents

Method for cutting wafer Download PDF

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Publication number
CN111180322B
CN111180322B CN201811344565.6A CN201811344565A CN111180322B CN 111180322 B CN111180322 B CN 111180322B CN 201811344565 A CN201811344565 A CN 201811344565A CN 111180322 B CN111180322 B CN 111180322B
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wafer
tape
substrate
dicing
scribe line
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CN111180322A (en
Inventor
陈靖为
韦承宏
张硕哲
陈宏生
周信宏
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Winbond Electronics Corp
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Winbond Electronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)

Abstract

The embodiment of the invention provides a method for cutting a wafer, which comprises the following steps: providing a wafer, wherein the wafer comprises a substrate, a plurality of crystal grains formed in and on the substrate, and a cutting channel structure positioned in a cutting area between adjacent crystal grains; removing a part of the cutting path structure around the test element; attaching the front side of the wafer to a first tape; removing a portion of the substrate from the back side of the wafer that overlaps the dicing area; attaching the back side of the wafer to a second tape; and removing the first adhesive tape and the rest part of the cutting path structure attached to the first adhesive tape, so that the plurality of crystal grains are separately attached to the second adhesive tape.

Description

Method for cutting wafer
Technical Field
The present invention relates to a method for cutting a wafer, and more particularly, to a method for cutting a wafer by removing scribe lines of the wafer in a segmented manner.
Background
As critical dimensions (critical dimensions) of semiconductor devices are scaled, more die can be formed on a single wafer. Therefore, the time required for cutting the wafer by using a mechanical cutting process such as laser or knife cutting is greatly prolonged, and the manufacturing cost of the semiconductor device is increased accordingly. The plasma dicing (plasma dicing) is used to perform wafer dicing, which can effectively shorten the process time. However, plasma dicing is hindered when the Test Element Group (TEG) in the scribe line contains a material such as aluminum that is not easily removed by dry etching or generates a by-product that is not easily removed by dry etching. In addition, it may be necessary to remove the etching by-products by a solution process, which may cause damage to the die.
Disclosure of Invention
The present invention provides a method for dicing a wafer, which can avoid directly etching a test device that may contain a metal that inhibits etching.
The wafer cutting method comprises the following steps: providing a wafer, wherein the wafer comprises a substrate, a plurality of crystal grains formed in and on the substrate, and a cutting channel structure, the cutting channel structure is arranged in a cutting area between adjacent crystal grains, and the cutting channel structure comprises at least one insulating layer formed on the substrate and a test element formed in the at least one insulating layer; removing a portion of at least one insulating layer around the test element; attaching the front side of the wafer to a first tape, wherein the first tape contacts the plurality of dies and the remaining portion of the at least one insulating layer; removing a portion of the substrate from the back side of the wafer that overlaps the dicing area; attaching the back side of the wafer to a second tape; and removing the first adhesive tape, the rest part of at least one insulating layer attached to the first adhesive tape and the test element, so that the plurality of dies are separately attached to the second adhesive tape.
Based on the above, the method for dicing a wafer according to the embodiment of the invention includes removing the scribe line structure in the dicing area of the wafer in a segmented manner. The scribe line structure is disposed on the substrate and between adjacent dies. In the first stage, the part of the scribe line structure located in the peripheral region is removed. The peripheral region of the street structure surrounds the central region with the test elements. Next, in a second stage, the portion of the substrate that overlaps the entire cutting area is removed. Since the portions of the scribe line structure in the peripheral region and the portion of the substrate overlapping the entire scribe line region are removed, the connection between the remaining portion of the scribe line structure (i.e., the portion in the central region) and the die can be broken. At this time, the remaining portion of the scribe line structure is attached only to the tape and not directly connected to the die. Finally, in the third stage, the tape is removed together with the remaining portion of the scribe line structure attached thereto. Therefore, the method for dicing the wafer according to the embodiment of the invention can avoid directly removing the test element which may contain the metal that hinders the etching. Therefore, the method for cutting the wafer of the embodiment of the invention can be suitable for plasma cutting. Compared with the method of cutting the wafer by laser cutting or mechanical cutting, the method of plasma cutting to singulate a plurality of crystal grains on the wafer can greatly shorten the time of cutting the wafer, so the manufacturing cost can be greatly reduced.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a flow chart of a method of dicing a wafer according to some embodiments of the invention;
fig. 2A to 2P are schematic cross-sectional views illustrating structures at intermediate stages of the method for dicing a wafer shown in fig. 1.
Detailed Description
Fig. 1 is a flow chart of a method of dicing a wafer according to some embodiments of the invention. Fig. 2A to 2P are schematic cross-sectional views illustrating structures at intermediate stages of the method for dicing a wafer shown in fig. 1.
Referring to fig. 1 and fig. 2A, step S100 is performed to provide a wafer W. The wafer W includes a substrate 100 and a plurality of dies D. In some embodiments, the substrate 100 may be a semiconductor substrate or a Semiconductor On Insulator (SOI) substrate. The semiconductor material in the semiconductor substrate and the SOI substrate may comprise an elemental semiconductor or an alloy semiconductor. The elemental semiconductor may comprise Si or Ge, for example. The alloy semiconductor may comprise SiGe, SiC, SiGeC, a group III-V semiconductor material, or a group II-VI semiconductor material. In some embodiments, the substrate 100 may be doped to a first conductivity type or a second conductivity type complementary to the first conductivity type. For example, the first conductivity type may be N-type and the second conductivity type may be P-type. Each die D is formed on the substrate 100, and a portion of the die D may be located in the substrate 100. The dies D may include active and passive devices to form an integrated circuit (not shown). In some embodiments, an integrated circuit includes logic circuitry, memory circuitry, analog component circuitry, the like, or combinations thereof. For simplicity, fig. 2A-2P do not show such integrated circuits. In some embodiments, the integrated circuits in multiple dies D may be identical to each other. In other embodiments, the integrated circuits in the plurality of dies D may also be different from each other. In addition, each die D may further include a seal ring (not shown). The seal ring surrounds the integrated circuits to absorb stress and protect the integrated circuits when the wafer W is diced.
The wafer W further includes a scribe line structure SLS. The scribe line structure SLS is disposed in the scribe region SLR between the adjacent dies D. In some embodiments, the width of the cleavage region SLR ranges from 60 μm to 80 μm. In some embodiments, the dicing regions SLR between the plurality of dies D may be connected to each other, but are continuous regions. The street structure SLS comprises one or more insulating layers 102. In some embodiments, the scribe line structure SLS includes a plurality of insulating layers 102, and the plurality of insulating layers 102 are stacked on the substrate 100. For example, the material of the insulating layer 102 may include silicon oxide, silicon nitride, a polymer, or a combination thereof. Furthermore, the street structure SLS further comprises a test element TE. The test element TE is formed in the multi-layered insulating layer 102 and is located in the central region CR of the cutting region SLR. The peripheral region PR of the scribe region SLR is located between the central region CR and the adjacent die D, and no test element TE is formed therein. In other words, only the insulating layer 102 may be included in the peripheral region PR of the cutting region SLR. In some embodiments, the central region CR may have a width in the range of 56 μm to 76 μm, and the peripheral region PR may have a width greater than 2 μm.
In some embodiments, the test element TE may include a plurality of conductive vias 104 and a plurality of traces 106. Each conductive via 104 penetrates one of the multiple insulating layers 102. Each trace 106 extends on one of the insulating layers 102 and is electrically connected to at least one of the conductive vias 104. In some embodiments, the test device TE further includes a pad P. The pad P is formed in the topmost insulating layer 102 and electrically connected to the topmost conductive via 104. In some embodiments, the trace 106 and the pad P are made of a metal material, and the metal material is not easily removed by dry etching or easily forms a byproduct that is not easily removed during the dry etching process. For example, the material of the trace 106 and the pad P may include aluminum or aluminum alloy. Additionally, the material of the conductive via 104 may include tungsten.
Referring to fig. 1 and fig. 2B to fig. 2D, step S102 is performed to remove a portion of the scribe line structure SLS located in the peripheral region PR. In some embodiments, the portion of the scribe line structure SLS located in the peripheral region PR does not include the test element TE, and only includes the portion of the stacked structure formed by the multiple insulating layers 102. In other words, in step S102, a portion of the multi-layered insulation layer 102 located in the peripheral region PR is removed.
Referring to fig. 2B, the method of removing the portion of the scribe line structure SLS located in the peripheral region PR may include forming a photoresist material layer (not shown) on the wafer W substantially covering the entire surface of the wafer W. Then, the photoresist material layer is patterned by a photolithography process to form a photoresist layer PR1 having an opening S1. The opening S1 exposes the peripheral region PR of the scribe line structure SLS.
Referring to fig. 2C, the exposed portion of the scribe line structure SLS is removed by using the photoresist layer PR1 as a mask. In other words, the portion of the scribe line structure SLS in the peripheral region PR is removed, and the portion of the scribe line structure SLS in the central region CR is remained. At this time, a gap is formed between the remaining portion of the scribe line structure SLS and the adjacent grain D. In some embodiments, the method of removing the portion of the scribe line structure SLS located in the peripheral region PR may include anisotropic etching, such as dry etching. Since the peripheral region PR of the scribe line structure SLS does not include the test element TE, the metal material (such as aluminum) obstructing the etching process can be eliminated, and the above-mentioned portion of the scribe line structure SLS can be removed smoothly by the etching process. In some embodiments, the substrate 100 may serve as an etch stop layer. In other embodiments, the etching process may be timed to substantially completely remove the portion of the scribe line structure SLS located in the peripheral region PR.
Referring to fig. 2D, the photoresist layer PR1 is removed. As a result, the front side FS of the wafer W, i.e. the surfaces of the plurality of dies D and the remaining portion of the scribe line structure SLS, are exposed. In some embodiments, the method of removing the photoresist layer PR1 may include an ashing process. For example, the reactive gas used in the ashing process may include oxygen. In other embodiments, the photoresist layer PR1 may also be removed using a wet solution process.
Referring to fig. 1 and 2E, in some embodiments, a step S104 is performed to attach a polishing tape GTP to the front side FS of the wafer W. Herein, the front side FS of the wafer W refers to the surface of the die D and the scribe line structure SLS, and the back side BS of the wafer W refers to the surface of the substrate 100 opposite to the die D and the scribe line structure SLS. In some embodiments, the grinding tape GTP may be attached to the front side FS of the wafer W after the structure shown in fig. 2D is inverted. In some embodiments, after the tape GTP is attached to the front side FS of the wafer W, the tape GTP can be more closely adhered to the front side FS of the wafer W by, for example, lamination. In some embodiments, the polishing tape GTP may extend into the gap between the die D and the remaining portion of the scribe line structure SLS, and partially fill the gap. In other embodiments, the polishing tape GTP may substantially completely fill the gap.
Referring to fig. 1 and 2F, in some embodiments, step S106 is performed to thin the substrate 100 from the back side BS of the wafer W. The substrate 100 may be thinned to a predetermined thickness. In some embodiments, the predetermined thickness may be substantially equal to the thickness of the substrate within the die D. In some embodiments, the thinned substrate 100 may have a thickness ranging from 50 μm to 300 μm. In some embodiments, substrate 100 may be thinned by grinding or other methods.
Referring to fig. 1 and 2G, in some embodiments, step S108 is performed to attach the backside BS of the wafer W to the tape TP. At this point, the front side FS of the wafer W is attached to a polishing tape GTP, and the back side BS is attached to a tape TP. In some embodiments, the tape TP may be attached to the backside BS of the wafer W after inverting the structure shown in fig. 2F. In some embodiments, the tape TP is attached to the frame F.
Referring to fig. 1 and fig. 2H, in some embodiments, step S110 is performed to remove the polishing tape GTP. As a result, the front side FS of the wafer W is exposed, i.e. the surfaces of the plurality of dies D and the remaining portions of the scribe line structure SLS are exposed. In some embodiments, the material of the abrasive tape GTP comprises a photosensitive material. In such embodiments, the polishing tape GTP can be smoothly peeled off from the front side FS of the wafer W by removing the stickiness of the polishing tape GTP by irradiation with light.
Referring to fig. 1 and fig. 2I, step S112 is performed to attach the front side of the wafer W to the first tape TP 1. In some embodiments, the frame F connected to the tape TP may be attached to the first tape TP1 along with the wafer W. At this time, the backside BS of the wafer W is attached to the tape TP. On the other hand, the front side FS of the wafer is attached to a first tape TP 1. In other words, the first adhesive tape TP1 contacts the surfaces of the plurality of dies D and the remaining portion of the street structure SLS (i.e. the portion of the street structure SLS located in the central region CR). In some embodiments, the first tape TP1 may extend into the gap between the die D and the remaining portion of the scribe line structure SLS, so as to partially fill the gap. In other embodiments, the first tape TP1 may substantially completely fill the gap.
Referring to fig. 1 and fig. 2J, in some embodiments, step S114 is performed to remove the tape TP. In this way, the backside BS of the wafer W is exposed. In some embodiments, the material of the tape TP includes a photosensitive material. In such embodiments, the light can be used to eliminate the tackiness of the tape TP, so that the tape TP can be smoothly peeled off from the backside BS of the wafer W. Before or after removing the tape TP, the structure including the wafer W, the first tape TP1 and the frame F may be inverted such that the backside BS of the wafer W faces upward.
Referring to fig. 1 and fig. 2K to 2M, step S116 is performed to remove a portion of the substrate 100 overlapping the scribe line SLR from the backside BS of the wafer W. In some embodiments, the method of removing the portion of the substrate 100 overlapping the cutting region SLR from the backside BS of the wafer W may include sequentially performing the sub-steps S116a to S116 d.
Referring to fig. 1 and 2K, a sub-step S116a is performed to form a photoresist layer PR2 on the back side BS of the wafer W. In some embodiments, the photoresist layer PR2 may be formed on the back side BS of the wafer W by spray coating (sputtering). Furthermore, in some embodiments, the photoresist layer PR2 may substantially entirely cover the backside BS of the wafer W.
Referring to fig. 1 and fig. 2L, a sub-step S116b is performed to pattern the photoresist layer PR 2. As a result, an opening S2 is formed in the photoresist layer PR 2. The opening S2 exposes the backside BS of the substrate 100 and overlaps the dicing region SLR. In some embodiments, the edges of the opening S2 substantially align the sidewalls of the die D.
Referring to fig. 1 and 2M, a sub-step S116c is performed to remove the portion of the substrate 100 exposed by the opening S2 by using the patterned photoresist layer PR2 as a mask. In some embodiments, a portion of the substrate 100 overlapping the cutting region SLR is substantially completely removed to form an opening S3 in the substrate 100. The opening S3 exposes the portion of the scribe line structure SLS (including the insulating layer 102 and the test element TE) in the central region CR. At this time, since the portions of the street structures SLS located on the opposite sides of the central region CR (i.e. the portions of the street structures SLS located in the peripheral region PR) have been removed, the portions of the street structures SLS located in the central region CR are no longer directly connected to the die D, but are attached to the first tape TP 1. Further, since the structure located in the cutting region SLR has been removed or separated from the die D, the plurality of dies D can be singulated. In some embodiments, the portion of the substrate 100 exposed by the opening S2 may be removed by a plasma dicing (plasma dicing) method. In some embodiments, the plasma dicing time may be adjusted to substantially completely remove the portion of the substrate 100 that overlaps the dicing region SLR. In other embodiments, the insulating layer 102 farthest from the first tape TP1 in the cutting region SLR may also be used as a stop layer for the plasma cutting process. In addition, in some embodiments, the etchant (or referred to as a reactive gas) for plasma dicing includes a sulfur fluorine compound, but the invention is not limited thereto.
Referring to fig. 1 and 2N, a sub-step S116d is performed to remove the patterned photoresist layer PR 2. As such, the backside BS of the wafer W (i.e., the backsides of the dies D) may be substantially completely exposed. In some embodiments, the method of removing the photoresist layer PR2 may include an ashing process. For example, the reactive gas used in the ashing process may include oxygen. In other embodiments, the photoresist layer PR2 may also be removed using a wet solution process.
Referring to fig. 1 and fig. 2O, step S118 is performed to attach the back side BS of the wafer W (i.e., the back sides of the dies D) to the second tape TP 2. In some embodiments, the structure shown in fig. 2N may be inverted and the backside BS of the wafer W (i.e., the backsides of the plurality of dies D) may be attached to the second tape TP 2. In some embodiments, the frame F connected to the first tape TP1 may be attached to the second tape TP2 along with the wafer W. At this time, the front side FS of the wafer W (including the front sides of the plurality of dies D and the surface of the remaining portion of the scribe line structure SLS) is still attached to the first tape TP1, and the back side of the wafer W (i.e., the back side of the plurality of dies D) is attached to the second tape TP 2.
Referring to fig. 1 and fig. 2P, step S120 is performed to remove the first tape TP 1. Since the remaining portion of the scribe line structure SLS (the portion located in the central region CR) is only attached to the first tape TP1 and not directly connected to the die D, the first tape TP1 is removed to remove the remaining portion of the scribe line structure SLS. In other words, in step S120, the first tape TP1, the remaining portion of the insulating layer 102 attached to the first tape TP1, and the test element TE are removed. At this time, a plurality of the dies D separately attached to the second tape TP2 are left. In some embodiments, the material of the first adhesive tape TP1 includes a photosensitive material. In such embodiments, the first tape TP1 can be smoothly peeled off from the front side FS of the wafer W by removing the tackiness of the first tape TP1 by irradiation with light.
In some embodiments, after removing the first tape TP1, the plurality of dies D can be respectively removed from the second tape TP2 by using the pick-up tool PT. One skilled in the art can select a suitable picking tool according to the requirement, and the invention is not limited thereto. Thus, the method of dicing a wafer according to some embodiments of the present invention has been completed. In addition, after the dicing of the wafer is completed, the subsequent packaging process may be performed on the removed die D.
In summary, the method for dicing a wafer according to the embodiment of the invention includes removing the scribe line structure in the dicing area of the wafer in a segmented manner. The scribe line structure is disposed on the substrate and between adjacent dies. In the first stage, the part of the scribe line structure located in the peripheral region is removed. The peripheral region of the street structure surrounds the central region with the test elements. Next, in a second stage, the portion of the substrate that overlaps the entire cutting area is removed. Since the portions of the scribe line structure in the peripheral region and the portion of the substrate overlapping the entire scribe line region are removed, the connection between the remaining portion of the scribe line structure (i.e., the portion in the central region) and the die can be broken. At this time, the remaining part of the scribe line structure is attached only to the tape and not directly connected to the die. Finally, in the third stage, the tape is removed together with the remaining portion of the scribe line structure attached thereto. Therefore, the method for dicing the wafer according to the embodiment of the invention can avoid directly removing the test element which may contain the metal that hinders the etching. Therefore, the method for cutting the wafer of the embodiment of the invention can be suitable for plasma cutting. Compared with the method of cutting the wafer by laser cutting or mechanical cutting, the method of plasma cutting to singulate a plurality of crystal grains on the wafer can greatly shorten the time of cutting the wafer, so the manufacturing cost can be greatly reduced.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (10)

1. A method of dicing a wafer, comprising:
providing a wafer, wherein the wafer comprises a substrate, a plurality of dies formed in and on the substrate, and a scribe line structure, the scribe line structure is disposed in a scribe area between adjacent dies, the scribe line structure comprises at least one insulating layer formed on the substrate and a test element formed in the at least one insulating layer;
removing a portion of the at least one insulating layer around the test element;
attaching a front side of the wafer to a first tape, wherein the first tape contacts the plurality of dies and a remaining portion of the at least one insulating layer;
removing a portion of the substrate from a back side of the wafer that overlaps the dicing area;
attaching the back side of the wafer to a second tape; and
removing the first tape and the remaining portion of the at least one insulating layer and the test element attached to the first tape, so that the plurality of dies are separately attached to the second tape.
2. The method as claimed in claim 1, wherein the step of removing the portion of the at least one insulating layer around the test device comprises photolithography and etching.
3. The method of dicing a wafer of claim 1, further comprising, prior to attaching the front side of the wafer to the first tape:
attaching a grinding tape to the front side of the wafer;
thinning the substrate from the backside of the wafer; and
removing the grinding tape.
4. The method of claim 3, further comprising, prior to removing the polishing tape: attaching the back side of the wafer to a tape.
5. The method of dicing a wafer of claim 4, further comprising, after attaching the front side of the wafer to the first tape: removing the adhesive tape.
6. The method of claim 4, wherein the tape is attached to the same frame as the first tape.
7. The method of dicing a wafer according to claim 1, wherein the removing the portion of the substrate that overlaps the dicing area from the back side of the wafer comprises:
forming a photoresist layer on the back side of the wafer;
patterning the photoresist layer to form an opening in the photoresist layer, the opening overlapping the cutting region;
removing the portion of the substrate exposed by the opening with the patterned photoresist layer as a mask; and
the patterned photoresist layer is removed.
8. The method of dicing a wafer according to claim 7, wherein the method of removing the portion of the substrate comprises plasma dicing.
9. The method of claim 1, wherein the test element comprises aluminum.
10. The method of claim 1, wherein the first tape and the second tape are attached to a same frame.
CN201811344565.6A 2018-11-13 2018-11-13 Method for cutting wafer Active CN111180322B (en)

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CN111180322B true CN111180322B (en) 2022-05-31

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000294673A (en) * 1999-04-01 2000-10-20 Miyazaki Oki Electric Co Ltd Manufacture of semiconductor device
TW200709288A (en) * 2005-08-23 2007-03-01 Advanced Semiconductor Eng Method for dicing a wafer
CN101075580A (en) * 2007-06-01 2007-11-21 日月光半导体制造股份有限公司 Method for cutting crystal wafer
TW200924040A (en) * 2007-11-29 2009-06-01 United Microelectronics Corp Method for dicing wafer
TW201344774A (en) * 2012-03-02 2013-11-01 Fujifilm Corp Manufacturing method of semiconductor device
JP2016143671A (en) * 2015-01-29 2016-08-08 日立化成株式会社 Method for manufacturing semiconductor device and semiconductor device
CN108624250A (en) * 2017-03-15 2018-10-09 麦克赛尔控股株式会社 The manufacturing method of cutting adhesive tape, the manufacturing method of cutting adhesive tape and semiconductor chip

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000294673A (en) * 1999-04-01 2000-10-20 Miyazaki Oki Electric Co Ltd Manufacture of semiconductor device
TW200709288A (en) * 2005-08-23 2007-03-01 Advanced Semiconductor Eng Method for dicing a wafer
CN101075580A (en) * 2007-06-01 2007-11-21 日月光半导体制造股份有限公司 Method for cutting crystal wafer
TW200924040A (en) * 2007-11-29 2009-06-01 United Microelectronics Corp Method for dicing wafer
TW201344774A (en) * 2012-03-02 2013-11-01 Fujifilm Corp Manufacturing method of semiconductor device
JP2016143671A (en) * 2015-01-29 2016-08-08 日立化成株式会社 Method for manufacturing semiconductor device and semiconductor device
CN108624250A (en) * 2017-03-15 2018-10-09 麦克赛尔控股株式会社 The manufacturing method of cutting adhesive tape, the manufacturing method of cutting adhesive tape and semiconductor chip

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