TWI674708B - Fabrication method of chip package structure semi-finished product, chip package structure module and chip package structure - Google Patents

Abstract

A method for manufacturing a semi-finished product of a chip packaging structure, a chip packaging structure module, and a chip packaging structure. A plurality of conductive terminals are positioned by positioning a housing, so that the plurality of conductive terminals are laid out synchronously, thereby reducing the laying time of the conductive terminals, and then removed. The positioning case exposes the top overlapping portions of the conductive terminals, and conducts electrical connection with a predetermined circuit substrate or electronic component. The chip package structure module can quickly form a plurality of chip package structures through a cutting method, thereby simplifying the manufacturing process of the chip package structure and increasing the quality of the product.

Description

Method for manufacturing semi-finished product of chip package structure, chip package structure module and chip package structure

The present application relates to an integrated circuit packaging process, and more specifically, to a method for manufacturing a semi-finished product of a chip packaging structure, a chip packaging structure module, and a chip packaging structure.

In the traditional IC packaging process, the number of conductive terminals makes the layout of conductive terminals very cumbersome. It is often necessary to install a machine to send each conductive terminal to the circuit board for welding, which results in a long time for the layout of the conductive terminals and makes manufacturing costs. Stay high.

Therefore, in the IC packaging process, how to reduce the difficulty of laying out the conductive terminals and solve the problems of the long time for laying out the conductive terminals has become a technical issue that the industry is eager to overcome.

In view of the shortcomings of the foregoing prior art, the present application provides a semi-finished product of a chip packaging structure for manufacturing a chip packaging structure, wherein the chip packaging structure includes: a circuit carrier, the circuit carrier having an electrical bonding surface And at least one chip, the chip is electrically bonded to the electrical bonding surface and has a chip height, characterized in that the semi-finished product of the chip packaging structure includes: a plurality of conductive terminals, at least two of the plurality of conductive terminals The receiving space is defined to be spaced apart, and the receiving space is used to receive the at least one chip, and each of the conductive terminals has a height-increasing portion and a plug-in portion. A connecting portion, a bottom overlapping portion and a top overlapping portion, the bottom overlapping portion is connected to an end of the elevated portion close to the circuit carrier, and the top overlapping portion is connected to an end of the elevated portion facing away from the circuit carrier; The plug-in portion is connected to an end of the top overlap portion facing away from the bottom overlap portion, and the heightened portion heightens the top overlap portion, and the heightened portion has an increased height, so that the top overlap portion is overlapped with the bottom The distance dimension of the portion substantially conforms to the height of the increased height, wherein the increased height is greater than the height of the wafer, so that the top overlap portion avoids the wafer; and a positioning housing having a plurality of stop surfaces and The plurality of insertion holes, each of the stop surfaces is adjacent to one of the plurality of insertion holes, wherein the insertion portion of the plurality of conductive terminals is inserted into one of the plurality of insertion holes until the top The overlapping portions are positioned on the stop surface, and positioning of the plurality of conductive terminals by the positioning housing is completed, so that the bottom overlapping portions of the plurality of conductive terminals can be electrically overlapped with the electrical overlapping surfaces, respectively.

Optionally, in the above-mentioned semi-finished product of the chip packaging structure, the positioning case further has a glue injection hole, the glue injection hole penetrates the body of the positioning case, and is used for glue injection between the positioning case and the circuit. The gap between the carriers is filled with insulating glue to insulate and separate the chip and the plurality of conductive terminals.

Optionally, in the above-mentioned semi-finished product of the chip packaging structure, each of the conductive terminals is formed by a T-shaped structure, and the top overlapping portion is formed by bending a middle portion of the T-shaped structure.

Optionally, in the above-mentioned semi-finished product of the chip package structure, the top overlapping portions of each of the conductive terminals are formed by a U-shaped structure.

Optionally, in the above-mentioned semi-finished product of the chip packaging structure, in terms of a cross section, the top overlapped portion is larger than the bottom overlapped portion or larger than the plug-in portion.

Optionally, in the above-mentioned semi-finished product of the chip packaging structure, the raised portion, the plug-in portion and the bottom overlapped portion have substantially the same cross-section.

Optionally, in the semi-finished product of the chip packaging structure, four of the plurality of conductive terminals are designed in groups, so as to define the range of the accommodating space by the four of the group designs.

In addition, the present application also provides a chip package structure module, which includes a plurality of semi-finished products of the chip package structure. The chip package structure including the at least one chip and the plurality of conductive terminals can be formed by cutting.

Furthermore, the present application also provides a manufacturing method of a chip packaging structure, which is used for manufacturing a chip packaging structure, including: providing a circuit carrier, the circuit carrier having an electrical bonding surface; and providing at least one chip, so that The wafer is electrically connected to the electrical overlap surface, wherein the wafer has a wafer height; a semi-finished product of a chip package structure is provided, and the semi-finished product of the chip package structure includes: a plurality of conductive terminals, the plurality of conductive terminals are spaced apart and And at least one accommodation space is formed between the adjacent and the accommodation space, the accommodation space is used for accommodating the chip, and the plurality of conductive terminals respectively have an elevated portion, a plug-in portion, a bottom overlapped portion and a top overlapped portion; The bottom overlap portion is connected to an end of the heightened portion close to the circuit carrier, the top overlap portion is connected to an end of the heightened portion facing away from the circuit carrier, and the plug connection portion is connected to the top overlap portion away from the bottom overlap. At one end of the joint portion, the elevated portion increases the top overlap portion, and the elevated portion has an increased height, so that the distance between the top overlap portion and the bottom overlap portion substantially conforms to the rule of the increased height. Wherein the height increase is greater than the height of the wafer, so that the top overlap portion avoids the wafer; and a positioning housing having a plurality of stop surfaces and a plurality of insertion holes, each of the stop surfaces is One of the plurality of insertion holes is adjacent to the plurality of insertion holes, wherein the insertion portion of the plurality of conductive terminals is inserted into one of the plurality of insertion holes until the top overlapping portion is positioned on the stop surface, and Completing the positioning of the positioning case to the plurality of conductive terminals, so that the bottom overlapping portions of the plurality of conductive terminals have to be electrically connected to the electrical overlapping surfaces, respectively; and removing the positioning case and being inserted into the plurality of plugs The plug-in portion of the contact hole constitutes the chip package structure.

In addition, the present application also provides another manufacturing method of a chip packaging structure, which is used for manufacturing a plurality of chip packaging structures, including: providing a circuit carrier having an electrical bonding surface; and providing a plurality of chips so that the A plurality of wafers are electrically overlapped with the electrical overlap surface, wherein the plurality of wafers have a wafer height; a semi-finished product with a chip packaging structure is provided, and the semi-finished product with the chip packaging structure is Including: a plurality of conductive terminals, the plurality of conductive terminals are spaced apart from each other and form at least one accommodating space, and the accommodating space is used for accommodating the chip; A plug portion, a bottom overlap portion and a top overlap portion, the bottom overlap portion is connected to an end of the heightened portion close to the circuit carrier, and the top overlap portion is connected to the end of the heightened portion away from the circuit carrier, The plug portion is connected to an end of the top overlap portion facing away from the bottom overlap portion, the heightened portion heightens the top overlap portion, and the heightened portion has an increased height so that the top overlap portion and the bottom overlap The distance dimension of the connecting portion substantially conforms to the height of the increased height, wherein the increased height is greater than the height of the wafer, so that the top overlapping portion avoids the wafer; and a positioning housing, the positioning housing has a plurality of stop surfaces. And the plurality of insertion holes, each of the stop surfaces is adjacent to one of the plurality of insertion holes, wherein the insertion portion of the plurality of conductive terminals is inserted into one of the plurality of insertion holes until the The top overlap portion is positioned on the stop surface, The positioning of the plurality of conductive terminals by the positioning shell is completed, so that the bottom overlapping portions of the plurality of conductive terminals can be electrically overlapped with the electrical overlap surfaces, respectively; the positioning shell is removed and the plurality of conductive terminals are removed. The plug-in portion of the hole constitutes a chip package structure module, the chip package structure module includes the plurality of chip package structures, wherein each of the chip package structures includes one of the plurality of chips; and cutting the chip package The structural module separates the plurality of chip packaging structures from each other.

Compared with the prior art, in the semi-finished product of the chip package structure provided by the present application, the design structure of inserting a plurality of conductive terminals into the insertion holes of the positioning housing is used to synchronously lay out the plurality of conductive terminals through the positioning housing. , 俾 reduce the time required for the layout of each conductive terminal. The positioning housing is provided with a glue injection hole, and an insulating glue can be injected to insulate and isolate the wafer from the conductive terminals, thereby ensuring that the conductive transmission energy does not interfere with each other between the wafer and the conductive terminals, and avoids interference caused by external factors. Happening.

In addition, the chip package structure module provided in the present application includes a plurality of semi-finished products of the chip package structure, and a plurality of chip package structures can be formed in large quantities through cutting, thereby reducing the manufacturing cost of the chip package structure. In addition, in this application, four conductive terminals can be selected as a group, and four groups can be selected as a group. The conductive terminals surround a chip to form a chip packaging structure, so that the periphery of the chip is protected, which is conducive to cutting operations. Therefore, in addition to reducing the difficulty of laying out the conductive terminals, the application can also simplify the manufacturing process of the chip packaging structure. And increase the rate of goodness of the product.

1‧‧‧chip package structure

11‧‧‧ Semi-finished product of chip package structure

111‧‧‧Conductive terminal

1111‧‧‧Elevation Department

1112‧‧‧Socket

1113‧‧‧Bottom overlap

1114‧‧‧Top Overlap

11141‧‧‧ convex

112‧‧‧accommodation space

113‧‧‧Positioning housing

1131‧‧‧stop surface

1132‧‧‧Socket

1133‧‧‧Injection hole

12‧‧‧circuit carrier

121‧‧‧ Electric Lap Face

13‧‧‧Chip

14‧‧‧Insulating glue

X‧‧‧ increase height

Y‧‧‧Chip height

Z‧‧‧ remove height

FIG. 1 is an exploded schematic diagram of a preferred embodiment of a semi-finished product of a chip package structure used for manufacturing a chip package structure according to the present application.

FIG. 2 and FIG. 1 are perspective views of the semi-finished product of the chip package structure from another angle.

FIG. 3 and FIG. 1 are three-dimensional explosion diagrams of the semi-finished product of the chip packaging structure.

FIG. 4 and FIG. 1 are schematic partial cross-sectional views of a semi-finished product of the chip package structure.

FIG. 5 and FIG. 1 are schematic perspective views of the conductive terminals of the semi-finished product of the chip package structure.

FIG. 6 is a schematic side view of the conductive terminal shown in FIG. 5.

FIG. 7 is a schematic bottom view of the conductive terminal shown in FIG. 6.

FIG. 8 is a cross-sectional view of the plug-in portion of the conductive terminal shown in FIG. 6 cut along the AA line segment.

FIG. 9 is a cross-sectional view of the top overlapped portion of the conductive terminal shown in FIG. 6 cut along the BB line segment.

FIG. 10 is a cross-sectional view of a raised portion of the conductive terminal shown in FIG. 6 cut along a CC line segment.

FIG. 11 is a schematic cross-sectional view of a semi-finished product of a chip package structure of the present application before being mounted on a circuit carrier.

FIG. 12 is a schematic cross-sectional view of a semi-finished product of a chip packaging structure of the present application after being mounted on a circuit carrier.

FIG. 13 is a schematic cross-sectional view of the semi-finished product of the chip packaging structure of the present application, with the positioning housing removed.

FIG. 14 is a schematic diagram of a preferred embodiment of a chip package structure of the present application.

FIG. 15 is a schematic perspective view of another preferred embodiment of a semi-finished product of a chip package structure of the present application.

FIG. 16 is a schematic perspective view of the conductive terminal shown in FIG. 15.

FIG. 17 is a schematic side view of the conductive terminal shown in FIG. 16.

FIG. 18 is a cross-sectional view of the top overlapping portion of the conductive terminal shown in FIG. 17 taken along the DD line segment.

FIG. 19 is a schematic bottom view of the bottom overlapping portion of the conductive terminal shown in FIG. 16.

The following content will be combined with drawings to illustrate the technical content of this application through specific embodiments. Those familiar with this technology can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied by other different specific embodiments. Various details in this specification can also be modified and changed based on different perspectives and applications without departing from the spirit of this application. In particular, the proportional relationships and relative positions of the various elements in the drawings are for exemplary purposes only, and do not represent the actual status of the implementation of this application.

This application provides a method for manufacturing a semi-finished product of a chip packaging structure, a chip packaging structure module, and a chip packaging structure. For a description of the embodiments disclosed in the technology of this application, please refer to FIGS. 1 to 19 together.

As shown in FIG. 1, the semi-finished product 11 of the chip packaging structure of the present application is used for manufacturing a chip packaging structure 1. In the present application, the chip packaging structure 1 includes a circuit carrier 12 and at least one chip 13, wherein the circuit carrier 12 For example, it is a circuit substrate, and an electrical overlap surface is provided on the circuit carrier 12 121 (as shown in FIG. 11), and the chip 13 may be disposed on the circuit carrier 12 and electrically overlap with the electrical bonding surface 121 by, for example, soldering. Among them, it should be defined that the chip 13 has a Wafer height Y.

Please refer to FIG. 2. The semi-finished product 11 of the chip package structure of the present application includes a plurality of conductive terminals 111 and a positioning housing 113. The positioning housing 113 provides positioning for the plurality of conductive terminals 111, and the conductive terminals 111 are formed of, for example, a T-shaped structure made of metal. Furthermore, at least two of the plurality of conductive terminals 111 are spaced apart to define an accommodation space 112 (as shown in FIGS. 12 and 13) between the plurality of conductive terminals 111, and the accommodation space 112 is available. The chip 13 is accommodated in the accommodating space 112, and the chip 13 is not limited to one.

In the present application, each of the conductive terminals 111 has a heightened portion 1111, a plug portion 1112 (refer to FIG. 3), a bottom overlap portion 1113 and a top overlap portion 1114. Among them, the bottom overlapping portion 1113 is an end of the connection increasing portion 1111 close to the circuit carrier 12, so that the bottom overlapping portion 1113 can be directly electrically overlapped with the electrical overlapping surface 121 of the circuit carrier 12 (as shown in FIG. 11) . As shown in FIG. 3, the plug portion 1112 is connected to an end of the top overlap portion 1114 facing away from the bottom overlap portion 1113. The elevated portion 1111 is used to increase the top overlap portion 1114, and it should be defined that the elevated portion 1111 has an increased height X. In the present application, the height X of the heightened portion 1111 is greater than the wafer height Y of the wafer 13, so that the top overlap portion 1114 can be increased to avoid the wafer 13 to avoid interference between the top overlap portion 1114 and the wafer 13. . The top overlap portion 1114 is an end of the connecting height portion 1111 facing away from the circuit carrier 12. Optionally, each conductive terminal 111 has a T-shaped structure, and the top overlap portion 1114 is formed by bending the middle portion of the T-shaped structure. . In addition, as shown in FIG. 5, the top overlapping portion 1114 of each conductive terminal 111 has a convex portion 11141 formed of a U-shaped structure.

Please refer to FIG. 4. The positioning housing 113 of the present application has a plurality of stop surfaces 1131 and a plurality of insertion holes 1132. Each of the stop surfaces 1131 is adjacent to one of the plurality of insertion holes 1132. The plug-in portion 1112 can be inserted into the plug-in hole 1132 of the positioning housing 113 until the top overlap portion 1114 of the conductive terminal 111 is positioned on the stop surface 1131 of the positioning housing 113. Specifically, when the conductive terminal 111 When the plug portion 1112 is inserted into the plug hole 1132 in the positioning housing 113, the top of the conductive terminal 111 is overlapped. The convex portion 11141 of the connecting portion 1114 is positioned on the stop surface 1131 of the positioning housing 113 to complete the positioning of the conductive terminal 111 by the positioning housing 113. Therefore, the positioning housing 113 can simultaneously drag the plurality of conductive terminals 111 to make the conductive terminal The bottom overlap portion 1113 of 111 can be electrically overlapped with the electrical overlap surface 121 of the circuit carrier 12 (as shown in FIG. 14), thereby reducing the difficulty of laying out the plurality of conductive terminals 111.

With reference to FIG. 14, in an embodiment of the present application, four conductive terminals 111 are designed into a group, and an accommodation space 112 is defined between the four conductive terminals 111 designed in a group for use in One or more chips 13 are accommodated, and the four conductive terminals 111 designed in groups are respectively inserted into the insertion holes 1132 of the positioning housing 113 through the respective insertion portions 1132, and the positioning is completed to increase the structure The convex portions 11141 on the top overlapping portions 1114 of the conductive terminals 111 are opposite to each other inward. This design can protect the periphery of the chip 13, and can provide four electrical pins for transmitting the electrical signals to the chip 13 disposed therein through the four conductive terminals 111.

As shown in FIG. 4, the plug-in portion 1112 is inserted in the plug-in hole 1132 of the positioning housing 113. When the plug-in portion 1112 is inserted in the plug-in hole 1132, the stop surface 1131 is used for the conductive terminal 111. One side of the top overlap portion 1114 provides stop positioning, and at the same time, the stop surface 1131 can also be used as a reference surface to adjust the insertion portion 1112 to be inserted into the insertion hole 1132 in cooperation with the top overlap portion 1114 of the conductive terminal 111. The depth is such that the conductive terminal 111 can be inserted into the positioning housing 113 with a desired predetermined length.

Please refer to FIG. 5 to FIG. 10 at the same time. In a preferred embodiment, the conductive terminal 111 of the present application is composed of a metal T-shaped structure, and the top overlap portion 1114 of the conductive terminal 111 is formed by the conductive terminal 111. The middle part of the T-shaped structure is bent, thereby forming a convex portion 11141 of the U-shaped structure. The advantage of this design is that the top overlap portion 1114 can form the convex of the U-shaped structure through a bending method without the need for a dedicated mold. The portion 11141 can reduce the manufacturing cost.

In addition, in this embodiment, the cross-section of the top lap portion 1114 is larger than the cross-section of the bottom lap portion 1113 or larger than the cross-section of the plug portion 1112. This design structure may facilitate subsequent soldering of the top lap portion 1114 to the circuit. On the substrate, and helps to make the conductive terminal when the conductive terminal 111 is inserted into the positioning housing 113 The top overlap portion 1114 of the sub-111 is positioned on the stop surface 1131 of the positioning housing 113. In addition, the raised portion 1111 of the conductive terminal 111, the plug-in portion 1112 and the bottom overlapping portion 1113 may have substantially the same cross-section, thereby simplifying the manufacturing process of the conductive terminal 111.

Please continue to refer to FIG. 15 to FIG. 19. In another embodiment of the present application, the conductive terminal 111 may also be formed by forging or drawing, and is not limited to the above T-shaped structure. In addition, the top overlapping portion 1114 of each conductive terminal 111 may also be directly formed into a predetermined shape by the above processing method. For the predetermined shape, for this embodiment, the cross-section of the top overlapping portion 1114 of each conductive terminal 111 may be larger than the bottom. The cross section of the overlapping portion 1113 is such that the top overlapping portion 1114 of the conductive terminal 111 can be positioned on the stop surface 1131 of the positioning housing 113.

As shown in FIG. 11 to FIG. 13, in another embodiment of the present application, the positioning housing 113 may further have at least one glue injection hole 1133, wherein the glue injection hole 1133 penetrates the body of the positioning housing 113 and is used for The gap 14 between the positioning housing 113 and the circuit carrier 12 is filled with glue to fill the insulating glue 14 so as to insulate and separate the chip 13 from the plurality of conductive terminals 111 and form a chip packaging structure 1. That is, the insulating glue 14 covers the wafer 13 and insulates the wafer 13 from the conductive terminals 111 at the same time, thereby protecting the wafer 13 and avoiding short circuits caused by the conductive terminals 111 and the wafer 13 on the circuit carrier 12 being exposed to the air, Influenced by the risk of irresistible factors such as moisture, which causes the problem that the chip 13 is burned or shortens the service life of the chip 13. Then, the positioning shell 113 and the plug portion 1112 inserted into the plug hole 1132 can be removed, so that the top overlap portion 1114 is exposed.

Furthermore, the present application also provides a chip package structural module, which includes a plurality of heightened connectors described in the above embodiments, and can be quickly formed by cutting to include a plurality of at least one chip 13 and a plurality of conductive terminals 111. The chip packaging structure 1 reduces the layout time of the conductive terminals, thereby simplifying the manufacturing process of the chip packaging structure and increasing the excellent rate of products.

In another embodiment, the present application also provides a method for manufacturing a chip packaging structure for manufacturing a chip packaging structure. Please refer to FIG. 11 to FIG. 14. The method for manufacturing a chip packaging structure provided in this application includes:

First, a circuit carrier 12 having an electrical bonding surface 121 is provided; then, at least one chip 13 is provided, and the chip 13 is electrically bonded to the electrical bonding surface 121 of the circuit carrier 12, and each chip 13 has One wafer height Y.

A chip package structure semi-finished product 11 having a plurality of conductive terminals 111 is provided, and the chip package structure semi-finished product 11 is soldered to the circuit carrier 12. In an embodiment of the present application, the chip package structure semi-finished product 11 is surface mount technology (Surface Mount Technology) ) It is welded and fixed to the electrical connection surface 121 of the circuit carrier 12 to complete the assembly. In an embodiment of the present application, the plurality of conductive terminals 111 may be designed as a group of four, and a space between them is defined for each other. An accommodating space 112 of at least one wafer 13 is placed so that the conductive terminals 111 surround the periphery of the wafer 13, and the wafer 13 is protected around the periphery, and a space is created for the insulating glue 14 to be injected to protect the wafer 13.

In addition, the heightened portion 1111 of the conductive terminal 11 has an increased height X, so that the distance dimension between the top overlap portion 1114 and the bottom overlap portion 1113 of the conductive terminal 111 substantially conforms to the dimension of the height increase X. In this embodiment, the conductive terminal 111 The height X is larger than the wafer height Y of the wafer 13, so that the top overlapping portion 1117 of the conductive terminal 111 can be exposed from the wafer 13 to avoid interference between the top overlapping portion 1114 and the wafer 13. Secondly, the insulating glue 14 can be injected through the injection hole 1133 on the positioning housing 113 of the semi-finished product 11 of the chip packaging structure, and the insulating glue 14 can be filled into the accommodating space 112 formed by the conductive terminals 111 so as to be set in the accommodating space. The wafer 13 in 112 is covered with an insulating glue 14, and the insulating glue 14 is used to provide an insulating environment for the wafer 13. Then, after the insulating glue 14 fills the accommodating space 112 and is cured, the positioning housing 113, the insertion portion 1112 of the conductive terminal 111, the top overlap portion 1114, and a portion of the insulating glue 14 injected therein are removed. Then, the exposed top overlap portion 1114 is formed to form a chip package structure module including at least one chip package structure. In addition, when the chip package structure module includes a plurality of chip packages When the structure 1 is used, the chip packaging structures 1 can be separated from each other by cutting, dicing, etc., and a plurality of independent chip packaging structures 1 can be cut, and the power supply can be connected to a preset circuit substrate (not shown in the figure). Or electronic components (not shown).

In addition, the top bonding portion 1114 forming a U-shaped structural cross section in each chip package structure 1 is the only conductive terminal 111 exposed outside the insulating glue 14, and the top bonding portion 1114 having a U-shaped structural cross section can increase conductivity The soldering area of the terminal 111 is beneficial for being electrically connected to a predetermined circuit substrate (not shown in the figure) or an electronic component (not shown in the figure). It should be noted that the removal height Z can be set by the user according to the specifications. Each chip package structure 1 includes four conductive terminals 111 and a chip 13 surrounded by the four conductive terminals 111, but is not limited thereto. The number of the conductive terminals 111 and the chips 13 in each chip package structure 1 may be changed according to circumstances. .

In summary, the semi-finished product of the chip package structure includes a plurality of conductive terminals and a positioning housing. At least two of the plurality of conductive terminals are spaced apart from each other, and an accommodating space for accommodating a chip is defined between each of the conductive terminals. The terminals each have an elevated portion, a bottom overlapping portion connected to the end of the elevated portion close to the circuit carrier, a top overlapping portion connected to the end of the elevated portion facing away from the circuit carrier, and a connection of the top overlapping portion away from the bottom overlapping portion. The heightened part is to increase the top overlap part, and the height is greater than the height of the wafer, so that the top overlap part avoids the chip, and the positioning housing has a plurality of stop surfaces and A plurality of insertion holes, wherein the insertion portion of the conductive terminal is inserted into the insertion hole until the top overlap portion is positioned on the stop surface, and the positioning of the conductive terminal by the positioning housing is completed, and The bottom overlapping portions of the conductive terminals are electrically overlapped with the electrical overlap surfaces, respectively.

The above-mentioned embodiments only exemplify the principle and effect of the present application, and are not intended to limit the present application. Anyone familiar with this technology can modify and change the above embodiments without departing from the spirit and scope of this application. Therefore, the scope of protection of the rights in this application should be as listed in the scope of patents in this application.

Claims (10)

A semi-finished product of a chip packaging structure is used for manufacturing a chip packaging structure, wherein the chip packaging structure includes: a circuit carrier having an electrical bonding surface; and at least one chip, the chip is electrically The electrical bonding surface is overlapped and has a chip height. The semi-finished product of the chip packaging structure includes:
A plurality of conductive terminals. At least two of the plurality of conductive terminals are spaced apart to define an accommodating space. The accommodating space is used for accommodating the at least one wafer. Each of the conductive terminals has an elevated portion, A plug portion, a bottom overlap portion and a top overlap portion, the bottom overlap portion is connected to an end of the heightened portion close to the circuit carrier, and the top overlap portion is connected to the end of the heightened portion away from the circuit carrier The plug-in portion is connected to an end of the top overlapped portion facing away from the bottom overlapped portion, and the heightened portion heightens the top overlapped portion, and the heightened portion has an increased height so that the top overlapped portion and the bottom The distance dimension of the overlapping portion substantially conforms to the height of the increased height, wherein the increased height is greater than the height of the wafer, so that the top overlapping portion avoids the wafer; and a positioning housing, the positioning housing has a plurality of stops. Surface and a plurality of insertion holes, each of the stop surfaces is adjacent to one of the plurality of insertion holes, wherein the insertion portion of the plurality of conductive terminals is inserted into one of the plurality of insertion holes until The top overlap portion is positioned on the stop surface, The completion of the positioning of the positioning housing a plurality of conductive terminals, so that the plurality of conductive terminal portions of the bottom have overlapping lap electrically the electrical faying surfaces. The semi-finished product of the chip package structure according to item 1 of the scope of the patent application, wherein the positioning housing further has a glue injection hole that penetrates the body of the positioning housing and is used for injection of glue in the positioning housing. The gap between the body and the circuit carrier is filled with insulating glue to insulate and separate the chip from the plurality of conductive terminals. The semi-finished product of the chip package structure according to item 1 of the scope of the patent application, wherein each of the conductive terminals is formed by a T-shaped structure, and the top overlapping portion is formed by bending a middle portion of the T-shaped structure. The semi-finished product of the chip package structure according to item 1 of the scope of the patent application, wherein the top overlapping portions of each of the conductive terminals are formed by a U-shaped structure. According to the semi-finished product of the chip package structure described in the first item of the patent application scope, in terms of a cross section, the top bonding portion is larger than the bottom bonding portion or larger than the insertion portion. The semi-finished product of the chip package structure according to item 1 of the patent application scope, wherein the raised portion, the plug-in portion and the bottom overlapped portion have substantially the same cross-section. The semi-finished product of the chip package structure according to item 1 of the scope of the patent application, wherein four of the plurality of conductive terminals are designed in a group, so that the range of the accommodation space is defined by the four of the group design. A chip package structure module includes a plurality of semi-finished products of the chip package structure as described in any one of items 1 to 7 of the scope of patent application, which can be formed by cutting to include the at least one chip and the plurality Chip package structure of conductive terminals. A manufacturing method of a chip package structure, which is used for manufacturing a chip package structure, includes:
Providing a circuit carrier, the circuit carrier having an electrical bonding surface; and providing at least one chip, so that the chip is electrically connected to the electrical bonding surface, wherein the chip has a chip height;
Provide a chip package structure semi-finished product. The chip package structure semi-finished product includes:
A plurality of conductive terminals, the plurality of conductive terminals being spaced apart from each other and forming at least one accommodating space between the plurality of conductive terminals, the accommodating space is used for accommodating the chip, and the plurality of conductive terminals are respectively provided with an elevated portion and a plug connection A bottom overlap portion and a top overlap portion, the bottom overlap portion is connected to an end of the heightened portion close to the circuit carrier, the top overlap portion is connected to the end of the heightened portion away from the circuit carrier, and the plug The connecting portion is connected to an end of the top overlapping portion facing away from the bottom overlapping portion. The elevated portion raises the top overlapping portion, and the elevated portion has an increased height, so that the top overlapping portion and the bottom overlapping portion are elevated. The distance dimension substantially corresponds to the height of the increased height, wherein the increased height is greater than the height of the wafer, so that the top overlap portion avoids the wafer; and a positioning housing, the positioning housing has a plurality of stop surfaces and a plurality of Each of the stopping surfaces is adjacent to one of the plurality of insertion holes, and the insertion portion of the plurality of conductive terminals is inserted into one of the plurality of insertion holes until the top The joint is positioned on the stop surface and completed Positioning the positioning case to the plurality of conductive terminals, so that the bottom overlapping portions of the plurality of conductive terminals have to be electrically connected to the electrical overlapping surfaces, respectively; and removing the positioning case and being inserted into the plurality of insertion holes To form the chip package structure. A manufacturing method of a chip packaging structure is used for manufacturing a plurality of chip packaging structures, including:
Providing a circuit carrier, the circuit carrier having an electrical bonding surface; and providing a plurality of chips to electrically connect the plurality of chips to the electrical bonding surface, wherein the plurality of chips have a chip height;
Provide a chip package structure semi-finished product. The chip package structure semi-finished product includes:
A plurality of conductive terminals, the plurality of conductive terminals being spaced apart from each other and forming at least one accommodating space between the plurality of conductive terminals, the accommodating space is used for accommodating the chip, and the plurality of conductive terminals are respectively provided with an elevated portion and a plug connection A bottom overlap portion and a top overlap portion, the bottom overlap portion is connected to an end of the heightened portion close to the circuit carrier, the top overlap portion is connected to the end of the heightened portion away from the circuit carrier, and the plug The connecting portion is connected to an end of the top overlapping portion facing away from the bottom overlapping portion. The elevated portion raises the top overlapping portion, and the elevated portion has an increased height, so that the top overlapping portion and the bottom overlapping portion are elevated. The distance dimension substantially corresponds to the height of the increased height, wherein the increased height is greater than the height of the wafer, so that the top overlap portion avoids the wafer; and a positioning housing, the positioning housing has a plurality of stop surfaces and a plurality of Each of the stopping surfaces is adjacent to one of the plurality of insertion holes, and the insertion portion of the plurality of conductive terminals is inserted into one of the plurality of insertion holes until the top The joint is positioned on the stop surface and completed Positioning a plurality of conductive terminals positioned in the housing, so that the plurality of conductive terminal portions of the bottom have overlapping lap electrically the electrical faying surfaces;
Removing the positioning housing and the plug-in part inserted into the plurality of plug-in holes to form a chip package structure module, the chip package structure module including the plurality of chip package structures, wherein each of the chip package structures includes the One of a plurality of chips; and cutting the chip package structure module to separate the plurality of chip package structures from each other.