TWI672771B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TWI672771B
TWI672771B TW104133872A TW104133872A TWI672771B TW I672771 B TWI672771 B TW I672771B TW 104133872 A TW104133872 A TW 104133872A TW 104133872 A TW104133872 A TW 104133872A TW I672771 B TWI672771 B TW I672771B
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semiconductor wafer
sealant
circuit board
substrate
oxide film
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TW201624638A (zh
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三室陽一
渡邊考太郎
南志昌
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日商艾普凌科有限公司
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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/73201—Location after the connecting process on the same surface
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Abstract

在電路基板安裝半導體晶片的覆晶(Flip Chip)安裝中，被充填於兩者之間的密封劑的熱膨脹係數是比半導體晶片大，因此在溫度循環等的環境試驗中，大的熱應力會施加於半導體晶片，會有以殘存於劃線領域上的氧化膜與矽的界面為起點產生龜裂的情況。於是，提供一種不易產生龜裂之覆晶安裝的半導體裝置。
其解決手段是因為除去成為龜裂的起點之殘存於劃線(scribe)領域上的氧化膜與矽的界面，所以為氧化膜不存在於劃線領域上的構造，在該狀態下進行覆晶安裝。其結果，在半導體晶片的端部，成為電路基板、密封劑、矽基板層疊的狀態。

Description

半導體裝置
本發明是有關半導體晶片被覆晶安裝於電路基板的半導體裝置。
為了製造半導體裝置，而使用覆晶安裝，其係經由凸塊，元件面正對於電路基板，在電路基板上安裝半導體晶片。在覆晶安裝中，電路基板與半導體晶片的連接是藉由在半導體晶片側設置焊錫凸塊等，予以壓著於電路基板側的配線來實現。而且，在電路基板與半導體晶片之間，為了耐溼性的確保、或從電路基板往焊錫凸塊的應力緩和，而充填環氧樹脂等的密封劑。
由於前述的密封劑的熱膨脹係數是比半導體晶片大，因此在溫度循環等的環境試驗中，大的熱應力會施加於半導體晶片。因為半導體晶片與電路基板的熱膨脹係數也不同，所以在密封劑也產生大的應力。因此，在溫度循環試驗中，因應力而焊錫凸塊的接合變不安定，或發生龜裂進入半導體晶片的情形。
在專利文獻1中記載：為了迴避如此的不良情況，在以往無凸塊的半導體晶片的各邊的中央部的領域形成只進行接合的凸塊，而與電路基板連接，藉此提高可靠度。
而且，充填密封劑的工程若使密封劑的量或注入方向形成有效率的，則會成為密封劑未被覆至晶片側面的構造。圖2是顯示此狀況。在電路基板7上，半導體晶片10會倒裝藉由凸塊(未圖示)來接合。半導體晶片與電路基板之間是藉由密封劑6來充填。在專利文獻1中也顯示如此的構造。
[先行技術文獻] [專利文獻]
[專利文獻1]日本特開2002-170848號公報
當密封劑成為如此的形狀時，會成為密封劑的端部接觸於半導體晶片外周部分之以箭號所規定的劃線領域的構造，應力會集中於該密封劑端部附近，大的熱應力會施加於半導體晶片的劃線領域。而且，會有以殘存於半導體晶片的劃線領域上的氧化膜(層間絕緣膜)3與矽基板1的界面為起點，至半導體晶片內部，產生龜裂的情況。一旦產生如此的龜裂，則會因為將形成於半導體晶片內的PN接合部分破壞，所以產生洩漏電流，有消耗電流的增加或導致電路動作障礙的情形。
於是，本發明是以提供一種充分耐於溫度循環試驗之使用適於具有劃線領域構造的覆晶安裝的半導體晶片之半導體裝置為課題。
為了解決上述的課題，本發明是取以下那樣的構成。亦即，因為除去成為龜裂的起點之殘存於劃線領域上的氧化膜與矽基板的界面，所以為氧化膜不存在於劃線領域上的構造，在該狀態下進行覆晶安裝。其結果，在半導體晶片的外周部分，成為電路基板、密封劑、矽基板的層疊狀態，因此在層間膜的氧化膜與矽基板上之間不會施加大的應力。
藉由使用上述手段，即使在施加熱應力的環境狀態中，也不會在覆晶安裝後的半導體晶片中產生龜裂。因此，可取得可靠度高，特性的安定化、防止經年劣化的效果。
1‧‧‧矽基板
2‧‧‧場氧化膜
3‧‧‧層間氧化膜
4‧‧‧金屬配線層
5‧‧‧保護膜
6‧‧‧密封劑
7‧‧‧電路基板
8‧‧‧焊錫凸塊
9‧‧‧窪坑
10‧‧‧半導體晶片
圖1是半導體晶片被覆晶安裝於電路基板之本發明的實施例的半導體裝置的剖面構造圖。
圖2是半導體晶片被覆晶安裝於電路基板之以往的半導體裝置的剖面構造圖。
圖3是表示本發明的半導體裝置的實施例的製造工程的剖面圖。
圖4是表示本發明的半導體裝置的其他的實施例的剖面圖。
在圖1中顯示本半導體晶片被覆晶安裝於電路基板之本發明的實施例的半導體裝置的剖面構造圖。以元件面能夠正對於電路基板的方式，半導體晶片被覆晶安裝於電路基板的半導體裝置是在電路基板7之上，半導體晶片10會倒裝(Face-down)藉由凸塊(未圖示)來接合。半導體晶片與電路基板之間是藉由密封劑6來充填。此情況，會成為密封劑的端部接觸於半導體晶片外周部分之以箭號所示的劃線領域的構造。半導體晶片10是具有：設在矽基板1的表面之場氧化膜2、從場氧化膜2直設到矽基板表面之層間絕緣膜3、設在層間絕緣膜上之金屬配線層4、及設在金屬配線層4上之保護膜5。
在圖1中重要的點是層間絕緣膜3不存在於劃線領域上。在本實施例中，層間絕緣膜3是和保護膜5一起只在與劃線領域的境界露出端面。
圖3是表示本發明的半導體裝置的實施例的製造工程的剖面圖，依序顯示用以製造圖1的實施例的工程的概略。首先，使用適於其機能的半導體製程來製造圖3(a)所示的半導體晶片10。半導體晶片10所具有的代表性的構 造是如同圖1般。矽基板1及設在矽基板1的表面之場氧化膜2、從場氧化膜2直設到矽基板表面之層間絕緣膜3、設在層間絕緣膜上之金屬配線層4、設在金屬配線層4上之保護膜5、被設在未設有保護膜5的金屬配線的露出部(所謂的焊墊部)之焊錫凸塊8。
在劃線領域上是蝕刻除去在製造如此的構造的半導體製程的過程所被層疊的各種的金屬膜。有關絕緣膜是至保護膜的圖案化終了後，僅劃線領域上蝕刻除去。或，在使各種的絕緣膜圖案化的各工程蝕刻除去也無妨。如此，將除去劃線領域上的絕緣膜之半導體晶片上下反轉而往電路基板安裝。
如圖3(b)所示般，例如只要是在半導體晶片形成有焊錫凸塊8，適於進行覆晶安裝的形態，便會將焊錫凸塊8連接至電路基板7的配線。為了使焊錫溶融接著，而進行短時間的熱處理，將半導體晶片上的焊錫凸塊8壓著於電路基板上的配線。
然後，如圖3(c)所示般，為了提高耐環境性及耐溼性，而將密封劑6注入至半導體晶片與電路基板之間，進行適當的硬化處理。如在此所示般充填密封劑的工程若使密封劑的量或注入方向形成有效率的，則會成為密封劑未被覆至晶片側面的構造。亦即，密封劑是成為與半導體晶片只接觸於其表面，與半導體晶片的側面不接觸的形狀。
圖4是表示本發明的其他的實施例的剖面圖。在使各種的絕緣膜圖案化的各工程，蝕刻除去絕緣膜時，若以使 用氟化碳等的各向同性蝕刻來除去最後的絕緣膜，則如圖4所示般，劃線領域的矽基板會被各向同性地蝕刻。矽基板是從內部往周邊，其厚度變薄。在如此的形狀中，層間絕緣膜會與先前的實施例同樣不存在於劃線領域上，密封劑會與半導體晶片直接接觸，可成為在半導體晶片不會產生龜裂的構造。而且，在矽基板中具有藉由蝕刻所形成的窪坑9，密封劑6會埋入窪坑9，其結果窪坑會成為裹住密封劑那樣的形狀，因此可提高矽基板與密封劑的密著度。

Claims (1)

  1. 一種半導體裝置，係被覆晶安裝的半導體裝置，其特徵為具有：電路基板；半導體晶片，其係由矽基板所構成，該矽基板係以元件面能夠正對於前述電路基板的方式接合；及密封劑，其係充填於前述半導體晶片與前述電路基板之間，前述密封劑係未被覆至前述半導體晶片的側面，前述側面露出，在前述半導體晶片的劃線領域上具有構成前述矽基板的矽表露的領域，前述矽表露的領域係形成與構成被前述劃線領域包圍的內部的矽的表面相同的平面，在前述矽表露的領域中，前述密封劑與前述矽基板係直接接觸。
TW104133872A 2014-11-04 2015-10-15 半導體裝置 TWI672771B (zh)

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US9704771B2 (en) 2017-07-11
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