TWI667746B - Semiconductor package structure and method for manufacturing the same - Google Patents

Abstract

A semiconductor packaging structure includes a circuit substrate, a chip, an adhesive layer, a plurality of wires, and a packaging gel. The circuit substrate includes an opposite first surface, a second surface, a through slot penetrating the first surface and the second surface, and a plurality of first pads on the second surface. The wafer is disposed on the first surface of the circuit substrate and covers a portion of the through groove. The chip includes an active surface facing the first surface and a plurality of second pads located on the active surface and exposed in the through slot, wherein the through slot includes a die orifice that is not covered by the wafer. The adhesive layer is disposed between the first surface of the circuit substrate and the chip, and includes at least one buffer wall extending to the die orifice.

Description

Semiconductor packaging structure and manufacturing method thereof

The invention relates to a semiconductor packaging structure and a manufacturing method thereof, and in particular to a semiconductor packaging structure with a buffer wall and a manufacturing method thereof.

In the semiconductor industry, the production of integrated circuits (ICs) can be divided into the following three stages: integrated circuit design (IC design), integrated circuit manufacturing (IC process), and integrated circuit packaging IC package, in which the packaging process usually covers the chip and wires with encapsulating gel. The purpose is to prevent the chip from being affected by external humidity and dust.

In the conventional semiconductor packaging technology, the encapsulating colloid is formed after the flow colloid is poured onto the wafer and cured. In the process of filling, the filling particles in the flowing encapsulant (Filler) are easy to directly impact between the edge of the wafer and the substrate with the flow of the mold flow, causing the wafer to shift and lift up and be damaged.

The invention provides a semiconductor package structure and a manufacturing method thereof, which can reduce Probability that the colloid will damage the wafer during the low-molding process.

The semiconductor packaging structure of the present invention includes a circuit substrate, a wafer, an adhesive layer, a plurality of wires, and a packaging gel. The circuit substrate includes an opposite first surface, a second surface, a through slot penetrating the first surface and the second surface, and a plurality of first pads on the second surface. The wafer is disposed on the first surface of the circuit substrate and covers a portion of the through groove. The chip includes an active surface facing the first surface and a plurality of second pads located on the active surface and exposed in the through slot, wherein the through slot includes a die orifice that is not covered by the wafer. The adhesive layer is disposed between the first surface of the circuit substrate and the chip, and includes at least one buffer wall extending to the die orifice. A plurality of wires pass through the slot and are connected to the first pad and the second pad. The encapsulation gel covers the first surface, the second surface of a part of the circuit substrate, the chip, the adhesive layer, and a plurality of wires, and fills the through groove and the die orifice.

The method for manufacturing a semiconductor package structure of the present invention includes the following steps. Provide a circuit board. The circuit substrate includes an opposite first surface, a second surface, a through slot penetrating the first surface and the second surface, and a plurality of first pads on the second surface. An adhesive layer is formed on the first surface of the circuit substrate near the through groove. The wafer is arranged on the adhesive layer and the wafer covers part of the through grooves. The wafer includes an active surface facing the first surface and a plurality of second pads located on the active surface and exposed in the through grooves. The through grooves include non-wafers. The covered mold openings, and the adhesive layer includes at least one buffer wall extending to the mold openings. A plurality of wires passing through the slot are provided, and the plurality of wires are connected to the first pad and the second pad. The flow colloid is injected onto the circuit substrate, the adhesive layer, and the wafer, and a part of the flow colloid flows from the first surface to the plurality of wires on the second surface through the die orifice, wherein at least a part of each buffer wall extends in a non-parallel direction. The direction of flow of the colloid. Solidified colloid An encapsulating gel is formed, wherein the encapsulating gel covers the first surface, a part of the second surface, the chip, the adhesive layer, and a plurality of wires of the circuit substrate, and fills the through grooves and the die orifice.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

100, 100a, 100b, 100c, 100d‧‧‧ semiconductor package structure

110‧‧‧circuit board

111‧‧‧ the first side

112‧‧‧ Wafer projection area

113‧‧‧Second Side

114‧‧‧ through groove

115‧‧‧mould mouth

116‧‧‧The first pad

120‧‧‧Chip

122‧‧‧ Active side

124‧‧‧Second pad

130‧‧‧ Adhesive layer

132‧‧‧ Part I

134‧‧‧Part Two

136, 136a, 136b, 136c, 136d

138‧‧‧solder ball

140‧‧‧ multiple wires

150‧‧‧ encapsulated colloid

G‧‧‧ Clearance

FIG. 1 is a schematic top view of a method for fabricating a semiconductor package structure according to an embodiment of the present invention.

Fig. 2 is a schematic cross-sectional view taken along the line A-A 'in Fig. 1.

FIG. 3 is a side view before FIG. 1.

FIG. 4A is a schematic top view of a method for manufacturing a semiconductor package structure according to another embodiment of the present invention.

Fig. 4B is a schematic cross-sectional view taken along the line A-A 'in Fig. 4A.

FIG. 4C is a schematic front view of FIG. 4A.

FIG. 5A is a schematic top view of a method for manufacturing a semiconductor package structure according to another embodiment of the present invention.

Fig. 5B is a schematic cross-sectional view taken along the line A-A 'of Fig. 5A.

FIG. 6 is a schematic top view of a method for manufacturing a semiconductor package structure according to another embodiment of the present invention.

FIG. 7 is a schematic top view of a method for manufacturing a semiconductor package structure according to another embodiment of the present invention.

In order to improve the manufacturing process of the conventional semiconductor package structure, the impact of the flowing colloid on the edge of the wafer during molding, especially the damage to the wafer by the filling particles (Filer) in the flowing colloid, the present invention uses the following These examples illustrate. FIG. 1 is a schematic top view of a method for fabricating a semiconductor package structure according to an embodiment of the present invention. Fig. 2 is a schematic cross-sectional view taken along the line A-A 'in Fig. 1. FIG. 3 is a side view before FIG. 1.

Please refer to FIG. 1, FIG. 2, and FIG. 3 at the same time, and provide a circuit substrate 110. The circuit substrate 110 includes an opposite first surface 111, a second surface 113, a through groove 114 passing through the first surface 111 and the second surface 113, and A plurality of first pads 116 on the second surface 113.

Next, an adhesive layer 130 is formed on the first surface 111 of the circuit substrate 110 near the through groove 114. In this embodiment, the adhesive layer 130 includes a first portion 132, a second portion 134, and at least one buffer wall 136. The first portion 132 and the second portion 134 are disposed on the first surface 111 of the circuit substrate 110 and are respectively located on two sides of the through groove 114. In this embodiment, the first portion 132 and the second portion 134 are rectangular, but the distribution shapes of the first portion 132 and the second portion 134 are not limited thereto. In this embodiment, the buffer wall 136 is provided on both sides of the through groove 114 as an example. One of the buffer walls 136 is connected to the first portion 132 and the other buffer wall 136 is connected to the second portion 134. Of course, in other embodiments, the number and connection relationship of the buffer walls 136 are not limited thereto.

After that, the wafer 120 is set on the adhesive layer 130, and the wafer 120 is covered. Part of the through groove 114, wherein the wafer 120 includes an active surface 122 facing the first surface 111 and a plurality of second pads 124 located on the active surface 122 and exposed from the through groove 114. In this embodiment, the wafer 120 is disposed on the first portion 132 and the second portion 134 of the adhesive layer 130, so that the wafer 120 covers a local through groove 114, and the through groove 114 not covered by the wafer 120 is formed. The die orifice 115 allows the flowing colloid to circulate between the first surface 111 and the second face 113 of the circuit substrate 110 through the die orifice 115 during subsequent molding operations. In this embodiment, the two buffer walls 136 respectively extend from the first portion 132 and the second portion 134 along the contour of the die orifice 115 toward the outside of the die orifice 115 to partly surround the die orifice 115 near each other. Outside. Then, as shown in FIG. 2, after the chip 120 is disposed on the adhesive layer 130, a plurality of wires 140 are electrically connected to the first pad 116 and the second pad 124 through the through groove 114.

Next, a molding process is performed, and the flow colloid is injected onto the circuit substrate 110, the adhesive layer 130, and the wafer 120. Part of the flow colloid flows from the first surface 111 through the die orifice 115 to the plurality of wires 140 on the second surface 113. . Thereafter, the flow colloid is cured to form an encapsulating colloid 150 (in FIG. 1, the encapsulating colloid 150 is indicated by a dashed line), wherein the encapsulating colloid 150 covers the first surface 111 of the circuit substrate 110, a portion of the second surface 113, the wafer 120, The adhesive layer 130 and the plurality of wires 140 are filled in the through groove 114 and the die opening 115. Finally, a plurality of solder balls 138 are formed on the second surface 113 of the circuit substrate 110.

In this embodiment, the injection port of the flow colloid is, for example, located at the upper right side / corner of FIG. 1 and FIG. 2, that is, the flow colloid will go from one side / one corner above the first surface 111 of the circuit substrate 110 toward The direction of the other areas of the first surface 111 and the direction of the second surface 113 flow. In this embodiment, at least a part of each buffer wall 136 The extending direction of is not parallel to the flow direction of the flow colloid. Therefore, in the step of injecting the flow colloid, part of the flow colloid first contacts the buffer wall 136 and then the edge of the wafer 120 on the first surface 111.

Compared to the conventional semiconductor package structure, which does not have a buffer wall, during the filling process, the flowing colloid will hit the edge of the wafer at a faster speed, causing the wafer to lift or be damaged. In this embodiment, the semiconductor package The structure uses a part of the adhesive layer as a buffer wall next to the die opening, so that the flow colloid can be blocked by the buffer wall before the wafer edge is contacted during the filling process to slow down the flow speed. Therefore, the impact of the flowing colloid on the edge of the wafer 120 can be reduced, thereby reducing the damage to the wafer 120 during the mold filling.

In this embodiment, since the extending direction of at least a part of each buffer wall 136 is not parallel to the flow direction of the flowing colloid, part of the flowing colloid will first contact the buffer wall 136 on the first surface 111, which causes the flow velocity of the flowing colloid to slow down. Then, the flow colloid is guided to the mold flow opening 115 by the flow guiding structures formed by the buffer walls 136 extending from the first portion 132 and the second portion 134 along the contour of the mold flow opening 115 to the outside of the mold flow opening 115, The flowing colloid will then flow toward the second surface 113 and fill. That is, in this embodiment, the buffer wall 136 can be used as a structure to guide the flow direction of the flowing colloid in addition to the structure for decelerating the flowing colloid.

Other embodiments are listed below. It should be noted that in the following embodiments, the same or similar elements as in the previous embodiment are represented by the same or similar symbols. The following only describes the differences between the different embodiments. The main differences will be explained, and the other contents will not be repeated here.

FIG. 4A is a schematic top view of a method for manufacturing a semiconductor package structure according to another embodiment of the present invention. Fig. 4B is a schematic cross-sectional view taken along the line A-A 'in Fig. 4A. FIG. 4C is a schematic front view of FIG. 4A.

Please refer to FIG. 4A, FIG. 4B and FIG. 4C. The main difference between the semiconductor package structure 100 a of FIGS. 4A, 4B and 4C and the semiconductor package structure 100 of FIGS. 1, 2 and 3 lies in that in this embodiment Each buffer wall 136a is respectively connected to the first portion 132 and the second portion 134, and a continuous low wall is formed on the outside of the die orifice 115. In this way, during the filling process, the buffer wall 136a can block the flow colloid to a greater extent, so that before the flow colloid contacts the edge of the wafer 120, the chance of the flow colloid contacting the buffer wall 136a can be increased, thereby reducing the flow colloid pair more effectively. The impact caused by the edges of the wafer 120 can reduce damage to the wafer 120 during the mold filling.

In this embodiment, the contour of the buffer wall 136a conforms to the contour of the die orifice 115, but in other embodiments, the contour of the buffer wall 136a may not conform to the contour of the die orifice 115.

FIG. 5A is a schematic top view of a method for manufacturing a semiconductor package structure according to another embodiment of the present invention. It is important to note that the encapsulant 150 on the circuit substrate 110, the chip 120, and the adhesive layer 130 is not shown in FIG. 5A, and the dashed line in FIG. 5A indicates the wafer projection area 112. The relationship between the first portion 132 and the second portion 134 of the adhesive layer 130 and the wafer 120 is more clearly shown. Fig. 5B is a schematic cross-sectional view taken along the line A-A 'of Fig. 5A.

Please refer to FIG. 5A and FIG. 5B, FIG. 5A and FIG. 5B semiconductor package structure The main difference between 100b and the semiconductor package structure 100 of FIGS. 1 and 2 is that, in this embodiment, the line buffer wall 136b is disposed along the edge of the wafer projection area 112 on the first surface 111 of the circuit substrate 110. In more detail, the two buffer walls 136b respectively extend from the first portion 132 and the second portion 134 toward the through groove 114 along the extending direction perpendicular to the through groove 114, and may extend between the first portion 132 and the second Between the edge of the portion 134 and the edge of the through groove 114. In this embodiment, the shape of the buffer wall 136b is rectangular, but the shape of the buffer wall 136b is not limited thereto.

In this embodiment, the length of the two buffer walls 136b is smaller than the distance between the first portion 132 and the through groove 114 and the distance between the second portion 134 and the through groove 114. However, in another embodiment, the length of the two buffer walls 136b may also be close to the distance between the first portion 132 and the through groove 114 and the distance between the second portion 134 and the through groove 114, so that the two buffer walls 136b The edges of the through groove 114 are respectively contacted from the first portion 132 and the second portion 134 along the extending direction perpendicular to the through groove 114.

Next, as shown in FIG. 2, a space G that is not filled with the adhesive layer 130 is stored between the edge portion of the wafer 120 and the circuit substrate 110. In contrast, as shown in FIG. 5B, since the buffer wall 136b is disposed between the edge portion of the wafer 120 and the circuit substrate 110, and is disposed along the edge of the wafer projection area 112, between the edge portion of the wafer 120 and the circuit substrate 110, The space G not filled in the adhesive layer 130 can be reduced, so that the fixed area between the edge portion of the chip 120 and the circuit substrate 110 is increased. Therefore, when the mold is poured, even if the impact of the flowing colloid on the edge of the wafer 120 and the circuit substrate 110 is not reduced, the configuration of the buffer wall 136b can still reduce the edge of the wafer 120 being impacted by the flowing colloid on the circuit substrate 110 Chance.

FIG. 6 is a schematic top view of a method for manufacturing a semiconductor package structure according to another embodiment of the present invention.

Please refer to FIG. 6. The main difference between the semiconductor package structure 100 c of FIG. 6 and the semiconductor package structure 100 b of FIGS. 5A and 5B is that, in this embodiment, the shape of each buffer wall 136 c is triangular. When the wafer 120 is covered on the adhesive layer 130, the adhesive layer 130 may overflow to the plurality of second pads 124 located on the active surface 122 and exposed in the through groove 114, and then contact the second pads 124. Therefore, When the shape of each buffer wall 136c is triangular, the risk that the adhesive layer 130 spills onto the second pad 124 can be reduced.

FIG. 7 is a schematic top view of a method for manufacturing a semiconductor package structure according to another embodiment of the present invention.

Please refer to FIG. 7. The main difference between the semiconductor package structure 100 d of FIG. 7 and the semiconductor package structure 100 b of FIGS. 5A and 5B is that, in this embodiment, the shape of each buffer wall 136 d may be semicircular. Of course, the shape of the buffer wall 136d is not limited to the above. In another embodiment, the shape of each buffer wall 136d may be a semi-circular shape, a polygonal shape, an arc shape, an irregular shape, or a combination thereof.

In summary, the semiconductor package structure and the manufacturing method of the present invention can be used to fix a part of the adhesive layer of the circuit substrate to a part of the adhesive layer of the circuit substrate to form a buffer wall next to the die orifice, so as to flow during the filling process. Before the colloid can contact the edge of the wafer, it can be blocked by the buffer wall to slow down the flow speed and reduce the impact of the flowing colloid on the edge of the wafer and cause damage to the wafer. In addition, the buffer wall of the present invention can also be arranged along the edge of the projection area of the wafer, increasing the distance between the wafer and the circuit substrate. The fixed area and the gap between the chip near the edge and the circuit board are reduced, so when the mold is filled, the impact of the flow colloid on the edge of the chip and the circuit board can be reduced, thereby reducing the edge of the chip being flowed into the colloid Probability that the filling particles impact and lift off the circuit board.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (10)

A semiconductor package structure includes a circuit substrate including a first surface, a second surface opposite to each other, a through slot penetrating through the first surface and the second surface, and a plurality of first contacts on the second surface. A pad; a wafer disposed on the first surface of the circuit substrate and covering the through slot, the wafer including an active surface facing the first surface and an active surface located on the active surface and exposed to The plurality of second pads penetrating through the groove, wherein the penetrating groove includes a die orifice not covered by the wafer; an adhesive layer is disposed between the first surface of the circuit substrate and the wafer And includes at least one buffer wall extending to the die orifice; a plurality of wires that pass through the through slot and are connected to the first pad and the second pad; and encapsulating gel, covering The first surface, a portion of the second surface, the wafer, the adhesive layer, and the plurality of wires of the circuit substrate are filled in the through groove and the die orifice. The semiconductor package structure according to item 1 of the scope of patent application, wherein the at least one buffer wall partially surrounds the outside of the die orifice. The semiconductor package structure according to item 1 of the scope of patent application, wherein the adhesive layer includes a first part and a second part, which are disposed on the first surface of the circuit substrate and are respectively located on two sides of the through groove. On the side, the two buffer walls respectively extend from the first part and the second part along the contour of the die orifice to the outside of the die orifice to close to each other. The semiconductor package structure according to item 1 of the scope of patent application, wherein the adhesive layer includes a first part and a second part, which are disposed on the first surface of the circuit substrate and are respectively located on two sides of the through groove. Side, each of the buffer walls is located outside the mold orifice and extends along the outline of the mold orifice, and each of the buffer walls is respectively connected to the first part and the second part, and each The outline of the buffer wall corresponds to the outline of the die orifice. The semiconductor package structure according to item 1 of the scope of patent application, wherein the first surface of the circuit substrate includes a wafer projection area, and the at least one buffer wall is disposed along an edge of the wafer projection area. The semiconductor package structure according to item 1 of the scope of patent application, wherein the adhesive layer includes a first part and a second part, which are disposed on the first surface of the circuit substrate and are respectively located on two sides of the through groove. On the side, the two buffer walls extend from the first portion and the second portion toward the through groove along an extending direction perpendicular to the through groove, respectively. The semiconductor package structure according to item 5 of the scope of patent application, wherein the shape of each buffer wall on the first surface is a protruding rectangle, arc, triangle, polygon, or a combination of the foregoing shapes. A method for manufacturing a semiconductor package structure includes: providing a circuit substrate, wherein the circuit substrate includes an opposite first surface, a second surface, a through groove penetrating the first surface and the second surface, and the first substrate is located in the first substrate. A plurality of first pads on two sides; forming an adhesive layer on the first surface of the circuit substrate near the through groove; setting a wafer on the adhesive layer, and covering the portion of the wafer The through slot, wherein the wafer includes an active surface facing the first surface and a plurality of second pads located on the active surface and exposed from the through slot, and the through slot includes a The die-flow opening covered by the wafer, and the adhesive layer includes at least one buffer wall extending to the die-flow opening; a plurality of wires passing through the through groove are provided, and the plurality of wires are connected to the The first pad and the second pad; injecting a flow colloid onto the circuit substrate, the adhesive layer, and the wafer, and a part of the flow colloid passing through the mold from the first surface The orifice flows onto the plurality of wires on the second side, wherein each of the buffer walls A portion of the extending direction is not parallel to the flow direction of the flowing colloid; and curing the flowing colloid to form an encapsulating colloid, wherein the encapsulating colloid covers the first surface of the circuit substrate, a portion of the first The two sides, the wafer, the adhesive layer and the plurality of wires are filled in the through slot and the die orifice. The method for manufacturing a semiconductor package structure according to item 8 of the scope of application, wherein the at least one buffer wall partially surrounds the outside of the die orifice, and in the step of injecting the flow colloid, part of the The flow colloid first contacts the at least one buffer wall on the first surface and then contacts the edge of the wafer. The method of manufacturing a semiconductor package structure according to item 8 of the scope of patent application, wherein the first surface of the circuit substrate includes a wafer projection area, and the at least one buffer wall is disposed along an edge of the wafer projection area. .