TW201943032A - Semiconductor package structure and method for manufacturing the same - Google Patents

Semiconductor package structure and method for manufacturing the same Download PDF

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TW201943032A
TW201943032A TW107111811A TW107111811A TW201943032A TW 201943032 A TW201943032 A TW 201943032A TW 107111811 A TW107111811 A TW 107111811A TW 107111811 A TW107111811 A TW 107111811A TW 201943032 A TW201943032 A TW 201943032A
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wafer
circuit substrate
semiconductor package
adhesive layer
package structure
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TW107111811A
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TWI667746B (en
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潘玉堂
周世文
呂良田
東鴻 黃
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南茂科技股份有限公司
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Priority to CN201810677885.7A priority patent/CN110349918B/en
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Publication of TW201943032A publication Critical patent/TW201943032A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Micromachines (AREA)

Abstract

A semiconductor package structure includes a circuit substrate, a chip, an adhesive layer, a plurality of wires and an encapsulant. The circuit substrate includes a first surface, a second surface opposite to the first surface, a through trench penetrating the first surface and the second surface, and a plurality of first contact pads on the second surface. The chip is disposed on the first surface of the circuit substrate and covers a part of the through trench. The chip includes an active surface facing the first surface and a plurality of second contact pads on the active surface, and the second contact pads are exposed to the through trench, wherein the through trench includes a model stream opening not covered by the chip. The adhesive layer is disposed between the first surface of the circuit substrate and the chip, and includes at least one buffering wall.

Description

半導體封裝結構及其製造方法Semiconductor packaging structure and manufacturing method thereof

本發明是有關於一種半導體封裝結構及其製造方法，且特別是有關於一種具有緩衝牆的半導體封裝結構及其製造方法。The invention relates to a semiconductor packaging structure and a manufacturing method thereof, and in particular to a semiconductor packaging structure with a buffer wall and a manufacturing method thereof.

在半導體產業中，積體電路(Integrated Circuits, IC)的生產，主要可分為以下三個階段，積體電路設計(IC design)、積體電路的製作(IC process)及積體電路的封裝製程(IC package)，其中封裝製程通常是藉由封裝膠體包覆晶片及導線，其目的在於防止晶片受到外界溼度影響及雜塵污染。In the semiconductor industry, the production of integrated circuits (ICs) can be divided into the following three stages: integrated circuit design (IC design), integrated circuit manufacturing (IC process), and integrated circuit packaging IC package, in which the packaging process usually covers the chip and wires with encapsulating gel. The purpose is to prevent the chip from being affected by external humidity and dust.

習知半導體封裝技術中，封裝膠體是流動膠體灌注至晶片上之後固化所形成。而在灌注的過程中，流動的封裝膠體中的充填粒子(Filler)容易隨模流流動而直接衝擊於晶片邊緣與基板之間，導致晶片偏移、上掀而損壞。In the conventional semiconductor packaging technology, the encapsulating colloid is formed after the flow colloid is poured onto the wafer and cured. In the process of filling, the filling particles in the flowing encapsulant (Filler) are easy to directly impact between the edge of the wafer and the substrate with the flow of the mold flow, causing the wafer to shift and lift up and be damaged.

本發明提供一種半導體封裝結構及其製造方法，其可降低灌模(molding)的過程中流動膠體損壞晶片的機率。The invention provides a semiconductor package structure and a manufacturing method thereof, which can reduce the probability that a flowing colloid damages a wafer during a molding process.

本發明的半導體封裝結構包括線路基板、晶片、黏膠層、多條導線及封裝膠體。線路基板包括相對的第一面、第二面、貫穿第一面與第二面的貫槽及位於第二面上的多個第一接墊。晶片配置於線路基板的第一面上且覆蓋部分的貫槽。晶片包括朝向第一面的主動面及位於主動面上且外露於貫槽的多個第二接墊，其中貫槽包括未被晶片覆蓋的模流口。黏膠層配置於線路基板的第一面與晶片之間，且包括延伸至模流口旁的至少一緩衝牆。多條導線穿過貫槽且連接於第一接墊及第二接墊。封裝膠體包覆線路基板的第一面、部分的第二面、晶片、黏膠層及多條導線，且填充於貫槽及模流口。The semiconductor packaging structure of the present invention includes a circuit substrate, a wafer, an adhesive layer, a plurality of wires, and a packaging gel. The circuit substrate includes an opposite first surface, a second surface, a through slot penetrating the first surface and the second surface, and a plurality of first pads on the second surface. The wafer is disposed on the first surface of the circuit substrate and covers a portion of the through groove. The chip includes an active surface facing the first surface and a plurality of second pads located on the active surface and exposed in the through slot, wherein the through slot includes a die orifice that is not covered by the wafer. The adhesive layer is disposed between the first surface of the circuit substrate and the chip, and includes at least one buffer wall extending to the die orifice. A plurality of wires pass through the slot and are connected to the first pad and the second pad. The encapsulation gel covers the first surface, the second surface of a part of the circuit substrate, the chip, the adhesive layer, and a plurality of wires, and fills the through groove and the die orifice.

本發明的半導體封裝結構的製造方法包括下列步驟。提供線路基板。線路基板包括相對的第一面、第二面、貫穿第一面與第二面的貫槽及位於第二面上的多個第一接墊。形成黏膠層於線路基板的第一面的靠近貫槽處。設置晶片於黏膠層上，且晶片覆蓋部分的貫槽，其中晶片包括朝向第一面的主動面及位於主動面上且外露於貫槽的多個第二接墊，貫槽包括未被晶片覆蓋的模流口，且黏膠層包括延伸至模流口旁的至少一緩衝牆。設置穿過貫槽的多條導線，且多條導線連接於第一接墊及第二接墊。注入流動膠體至線路基板、黏膠層、晶片上，且部分的流動膠體從第一面經過模流口流至第二面的多條導線上，其中各緩衝牆的至少一部分的延伸方向不平行於流動膠體的流動方向。固化流動膠體而形成封裝膠體，其中封裝膠體包覆線路基板的第一面、部分的第二面、晶片、黏膠層及多條導線，且填充於貫槽及模流口。The method for manufacturing a semiconductor package structure of the present invention includes the following steps. Provide a circuit board. The circuit substrate includes an opposite first surface, a second surface, a through slot penetrating the first surface and the second surface, and a plurality of first pads on the second surface. An adhesive layer is formed on the first surface of the circuit substrate near the through groove. The wafer is arranged on the adhesive layer and the wafer covers part of the through grooves. The wafer includes an active surface facing the first surface and a plurality of second pads located on the active surface and exposed in the through grooves. The through grooves include non-wafers. The covered mold openings, and the adhesive layer includes at least one buffer wall extending to the mold openings. A plurality of wires passing through the slot are provided, and the plurality of wires are connected to the first pad and the second pad. The flow colloid is injected onto the circuit substrate, the adhesive layer, and the wafer, and a part of the flow colloid flows from the first surface to the plurality of wires on the second surface through the die orifice, wherein at least a part of each buffer wall extends in a non-parallel direction. The direction of flow of the colloid. The flow colloid is cured to form an encapsulating colloid, wherein the encapsulating colloid covers the first side, a part of the second side, the chip, the adhesive layer, and a plurality of wires of the circuit substrate, and is filled in the through groove and the die orifice.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

為了改善習知半導體封裝結構的製作過程中，灌模(molding)時流動膠體對晶片的邊緣造成的衝擊，尤其是流動膠體內之填充粒子(Filer)對於晶片的損傷，本發明藉由下面的這些實施例來說明。圖1為依照本發明的一實施例所繪示的半導體封裝結構之製作方法的上視示意圖。圖2為沿圖1之A-A’線的剖面示意圖。圖3為圖1之前側視圖。In order to improve the manufacturing process of the conventional semiconductor package structure, the impact of the flowing colloid on the edge of the wafer during molding, especially the damage to the wafer by the filling particles (Filer) in the flowing colloid, the present invention uses the following These examples illustrate. FIG. 1 is a schematic top view of a method for fabricating a semiconductor package structure according to an embodiment of the present invention. Fig. 2 is a schematic cross-sectional view taken along the line A-A 'in Fig. 1. FIG. 3 is a side view before FIG. 1.

請同時參照圖1、圖2、圖3，提供線路基板110，其中線路基板110包括相對的第一面111、第二面113、貫穿第一面111與第二面113的貫槽114及位於第二面113上的多個第一接墊116。Please refer to FIG. 1, FIG. 2, and FIG. 3 at the same time, and provide a circuit substrate 110. The circuit substrate 110 includes an opposite first surface 111, a second surface 113, a through groove 114 passing through the first surface 111 and the second surface 113, and A plurality of first pads 116 on the second surface 113.

接著，形成黏膠層130於線路基板110的第一面111的靠近貫槽114處。在本實施例中，黏膠層130包括第一部分132、第二部分134及至少一緩衝牆136。第一部分132與第二部分134分別配置於線路基板110的第一面111上且位於貫槽114的兩側。在本實施例中，第一部分132及第二部分134以矩形為例，但第一部分132及第二部分134的分布形狀不以此為限制。在本實施例中，緩衝牆136以設置於貫槽114的兩邊為例，其中一個緩衝牆136連接於第一部分132，另一個緩衝牆136連接於第二部分134。當然，在其他實施例中，緩衝牆136的數量、連接關係不以此為限制。Next, an adhesive layer 130 is formed on the first surface 111 of the circuit substrate 110 near the through groove 114. In this embodiment, the adhesive layer 130 includes a first portion 132, a second portion 134, and at least one buffer wall 136. The first portion 132 and the second portion 134 are respectively disposed on the first surface 111 of the circuit substrate 110 and located on both sides of the through groove 114. In this embodiment, the first portion 132 and the second portion 134 are rectangular, but the distribution shapes of the first portion 132 and the second portion 134 are not limited thereto. In this embodiment, the buffer wall 136 is provided on both sides of the through groove 114 as an example. One of the buffer walls 136 is connected to the first portion 132 and the other buffer wall 136 is connected to the second portion 134. Of course, in other embodiments, the number and connection relationship of the buffer walls 136 are not limited thereto.

之後，設置晶片120於黏膠層130上，且晶片120覆蓋部分的貫槽114，其中晶片120包括朝向第一面111的主動面122及位於主動面122上且外露於貫槽114的多個第二接墊124。在本實施例中，晶片120配置於黏膠層130的第一部分132及第二部分134上，使晶片120覆蓋了局部之貫槽114，而未被晶片120覆蓋到的貫槽114則形成了模流口115，使後續進行模封作業時，流動膠體得以藉由模流口115而在線路基板110之第一面111與第二面113之間流通。在本實施例中，兩個緩衝牆136分別從第一部分132與第二部分134沿著模流口115的輪廓往模流口115的外側延伸至靠近於彼此而部分地環繞於模流口115的外側。然後，如圖2所示，在設置晶片120於黏膠層130上之後，多條導線140穿過貫槽114電性連接第一接墊116及第二接墊124。After that, the wafer 120 is disposed on the adhesive layer 130 and the wafer 120 covers a part of the through groove 114. The wafer 120 includes an active surface 122 facing the first surface 111 and a plurality of exposed active grooves 122 on the active surface 122 and exposed in the through groove 114.第二 接 垫 124。 The second joint pad 124. In this embodiment, the wafer 120 is disposed on the first portion 132 and the second portion 134 of the adhesive layer 130, so that the wafer 120 covers a local through groove 114, and the through groove 114 not covered by the wafer 120 is formed. The die orifice 115 allows the flowing colloid to circulate between the first surface 111 and the second face 113 of the circuit substrate 110 through the die orifice 115 during subsequent molding operations. In this embodiment, the two buffer walls 136 respectively extend from the first portion 132 and the second portion 134 along the contour of the die orifice 115 toward the outside of the die orifice 115 to partly surround the die orifice 115 near each other. Outside. Then, as shown in FIG. 2, after the chip 120 is disposed on the adhesive layer 130, a plurality of wires 140 are electrically connected to the first pad 116 and the second pad 124 through the through groove 114.

接著，進行模封製程，注入流動膠體至線路基板110、黏膠層130、晶片120上，部分的流動膠體從第一面111經過模流口115流至第二面113的多條導線140上。其後，固化流動膠體而形成封裝膠體150(在圖1中，封裝膠體150以虛線表示)，其中封裝膠體150包覆線路基板110的第一面111、部分的第二面113、晶片120、黏膠層130及多條導線140，且填充於貫槽114及模流口115。最後，於線路基板110的第二面113上形成多個焊球138。Next, a molding process is performed, and the flow colloid is injected onto the circuit substrate 110, the adhesive layer 130, and the wafer 120. Part of the flow colloid flows from the first surface 111 through the die orifice 115 to the plurality of wires 140 on the second surface 113. . Thereafter, the flow colloid is cured to form an encapsulating colloid 150 (in FIG. 1, the encapsulating colloid 150 is indicated by a dashed line), wherein the encapsulating colloid 150 covers the first surface 111 of the circuit substrate 110, a portion of the second surface 113, the wafer 120, The adhesive layer 130 and the plurality of wires 140 are filled in the through groove 114 and the die opening 115. Finally, a plurality of solder balls 138 are formed on the second surface 113 of the circuit substrate 110.

在本實施例中，流動膠體的注入口例如是位在圖1與圖2的右上側/角，也就是說，流動膠體會從線路基板110的第一面111上方的其中一側/一角往第一面111的其他區域的方向以及往第二面113的方向流動。在本實施例中，各緩衝牆136的至少一部分的延伸方向不平行於流動膠體的流動方向，因此，在注入流動膠體的步驟中，部分的流動膠體在第一面111先接觸緩衝牆136再接觸晶片120的邊緣。In this embodiment, the injection port of the flow colloid is, for example, located at the upper right side / corner of FIG. 1 and FIG. 2, that is, the flow colloid will go from one side / one corner above the first surface 111 of the circuit substrate 110 toward The direction of the other areas of the first surface 111 and the direction of the second surface 113 flow. In this embodiment, the extending direction of at least a part of each buffer wall 136 is not parallel to the flow direction of the flow colloid. Therefore, in the step of injecting the flow colloid, part of the flow colloid first contacts the buffer wall 136 on the first surface 111 and then The edge of the wafer 120 is contacted.

相較於習知的半導體封裝結構不具有緩衝牆，而在灌模的過程中，流動膠體會以較快的速度衝撞晶片的邊緣，導致晶片上掀或損壞，在本實施例中，半導體封裝結構利用黏膠層的其中一部分作為位於模流口旁的緩衝牆，來使灌模過程中流動膠體在接觸到晶片邊緣之前能夠受到緩衝牆的阻擋而減緩流動速度。所以可以減少流動膠體對晶片120的邊緣造成的衝擊，進而減少灌模時對晶片120產生的損傷。Compared to the conventional semiconductor package structure, which does not have a buffer wall, during the filling process, the flowing colloid will hit the edge of the wafer at a faster speed, causing the wafer to lift or be damaged. In this embodiment, the semiconductor package The structure uses a part of the adhesive layer as a buffer wall next to the die opening, so that the flow colloid can be blocked by the buffer wall before the wafer edge is contacted during the filling process to slow down the flow speed. Therefore, the impact of the flowing colloid on the edge of the wafer 120 can be reduced, thereby reducing the damage to the wafer 120 during the mold filling.

在本實施例中，由於各緩衝牆136的至少一部分的延伸方向不平行於流動膠體的流動方向，部分的流動膠體會在第一面111先接觸緩衝牆136，導致流動膠體的流動速度減緩，之後藉由分別從第一部分132與第二部分134沿著模流口115的輪廓往模流口115的外側延伸的緩衝牆136所形成的導流結構，將流動膠體導流向模流口115，之後流動膠體會流向第二面113充填。也就是說，在本實施例中，緩衝牆136除了作為使流動膠體減速的結構之外，還可作為引導流動膠體流動方向的結構。In this embodiment, since the extending direction of at least a part of each buffer wall 136 is not parallel to the flow direction of the flowing colloid, part of the flowing colloid will first contact the buffer wall 136 on the first surface 111, which causes the flow velocity of the flowing colloid to slow. Then, the flow colloid is guided to the mold flow opening 115 by the flow guiding structures formed by the buffer walls 136 extending from the first portion 132 and the second portion 134 along the contour of the mold flow opening 115 to the outside of the mold flow opening 115, The flowing colloid will then flow toward the second surface 113 and fill. That is, in this embodiment, the buffer wall 136 can be used as a structure to guide the flow direction of the flowing colloid in addition to the structure for decelerating the flowing colloid.

下面舉出其他的實施態樣，需說明的是，在下面的實施例中，與前一實施例相同或是相似的元件以相同或是相似的符號表示，下面僅就不同實施例之間的主要差異進行說明，其他內容不再多加贅述。Other embodiments are listed below. It should be noted that in the following embodiments, the same or similar elements as in the previous embodiment are represented by the same or similar symbols. The following only describes the differences between the different embodiments. The main differences will be explained, and the other contents will not be repeated here.

圖4A為依照本發明的另一實施例所繪示的半導體封裝結構之製作方法的上視示意圖。圖4B為圖4A之A-A’線的剖面示意圖。圖4C為圖4A之前視示意圖。FIG. 4A is a schematic top view of a method for manufacturing a semiconductor package structure according to another embodiment of the present invention. Fig. 4B is a schematic cross-sectional view taken along the line A-A 'in Fig. 4A. FIG. 4C is a schematic front view of FIG. 4A.

請參閱圖4A、圖4B及圖4C所示，圖4A、圖4B及圖4C的半導體封裝結構100a與圖1、圖2及圖3的半導體封裝結構100的主要差異在於，在本實施例中，各緩衝牆136a分別連接於第一部分132與第二部分134，而在模流口115的外側形成連續的矮牆。如此，在灌模過程中，緩衝牆136a可以更大範圍地阻擋流動膠體，造成在流動膠體接觸晶片120的邊緣前，流動膠體接觸緩衝牆136a的機會可以增加，進而更有效地減少流動膠體對晶片120的邊緣造成的衝擊，因此達到減少灌模時對晶片120產生的損傷。Please refer to FIG. 4A, FIG. 4B and FIG. 4C. The main difference between the semiconductor package structure 100 a of FIGS. 4A, 4B and 4C and the semiconductor package structure 100 of FIGS. 1, 2 and 3 lies in that in this embodiment Each buffer wall 136a is respectively connected to the first portion 132 and the second portion 134, and a continuous low wall is formed on the outside of the die orifice 115. In this way, during the filling process, the buffer wall 136a can block the flow colloid to a larger extent, so that before the flow colloid contacts the edge of the wafer 120, the chance of the flow colloid contacting the buffer wall 136a can be increased, thereby reducing the flow colloid pair more effectively The impact caused by the edges of the wafer 120 can reduce damage to the wafer 120 during the mold filling.

在本實施例中，緩衝牆136a的輪廓共形於模流口115的輪廓，但在其他實施例中，緩衝牆136a的輪廓也可以不共形於模流口115的輪廓。In this embodiment, the contour of the buffer wall 136a conforms to the contour of the die orifice 115, but in other embodiments, the contour of the buffer wall 136a may not conform to the contour of the die orifice 115.

圖5A為依照本發明的另一實施例所繪示的半導體封裝結構之製作方法的上視示意圖。需特別注意的是，位於線路基板110、晶片120及黏膠層130之上的封裝膠體150未繪示於圖5A中，而圖5A中的虛線所表示的是晶片投影區112，為的是更清楚地表示黏膠層130的第一部分132及第二部分134與晶片120的配置關係。圖5B為沿圖5A之A-A’線的剖面示意圖。FIG. 5A is a schematic top view of a method for manufacturing a semiconductor package structure according to another embodiment of the present invention. It is important to note that the encapsulant 150 on the circuit substrate 110, the chip 120, and the adhesive layer 130 is not shown in FIG. 5A, and the dashed line in FIG. 5A indicates the wafer projection area 112. The relationship between the first portion 132 and the second portion 134 of the adhesive layer 130 and the wafer 120 is more clearly shown. Fig. 5B is a schematic cross-sectional view taken along the line A-A 'of Fig. 5A.

請參閱圖5A及圖5B，圖5A及圖5B的半導體封裝結構100b與圖1及圖2的半導體封裝結構100的主要差異在於，在本實施例中，線緩衝牆136b沿著線路基板110的第一面111上的晶片投影區112的邊緣配置。更詳細地說，兩個緩衝牆136b分別從所述第一部分132與第二部分134沿著垂直於貫槽114的延伸方向朝向貫槽114延伸，並且可以延伸至介於第一部分132及第二部分134的邊緣與貫槽114的邊緣之間。在本實施例中，緩衝牆136b的形狀為矩形，但緩衝牆136b的形狀不以此為限制。Please refer to FIGS. 5A and 5B. The main difference between the semiconductor package structure 100b of FIGS. 5A and 5B and the semiconductor package structure 100 of FIGS. 1 and 2 is that in this embodiment, the line buffer wall 136b An edge of the wafer projection area 112 on the first surface 111 is disposed. In more detail, the two buffer walls 136b respectively extend from the first portion 132 and the second portion 134 toward the through groove 114 along the extending direction perpendicular to the through groove 114, and may extend between the first portion 132 and the second Between the edge of the portion 134 and the edge of the through groove 114. In this embodiment, the shape of the buffer wall 136b is rectangular, but the shape of the buffer wall 136b is not limited thereto.

在本實施例中，兩個緩衝牆136b的長度小於第一部分132與貫槽114之間的距離以及第二部分134與貫槽114之間的距離。但在另一實施例中，兩個緩衝牆136b的長度也可以接近於第一部分132與貫槽114之間的距離以及第二部分134與貫槽114之間的距離，而使得兩緩衝牆136b分別從第一部分132及第二部分134沿著垂直於貫槽114的延伸方向而接觸貫槽114的邊緣。In this embodiment, the length of the two buffer walls 136b is smaller than the distance between the first portion 132 and the through groove 114 and the distance between the second portion 134 and the through groove 114. However, in another embodiment, the length of the two buffer walls 136b may also be close to the distance between the first portion 132 and the through groove 114 and the distance between the second portion 134 and the through groove 114, so that the two buffer walls 136b The edges of the through groove 114 are respectively contacted from the first portion 132 and the second portion 134 along the extending direction perpendicular to the through groove 114.

接著，請參閱圖2所示，在晶片120的邊緣的部位與線路基板110之間，存有一未填入黏膠層130的空間G。反觀圖5B所示，由於緩衝牆136b設置在晶片120的邊緣的部位與線路基板110之間，且沿著晶片投影區112的邊緣配置，在晶片120的邊緣的部位與線路基板110之間，未填入黏膠層130的空間G可被縮減，而使得晶片120在邊緣的部位與線路基板110之間的固定面積增加。所以當灌模時，即便流動膠體對晶片120的邊緣與線路基板110之間的衝擊未被降低，緩衝牆136b的配置仍可降低晶片120的邊緣被流動膠體衝擊而相對於線路基板110上掀的機率。Next, as shown in FIG. 2, a space G that is not filled with the adhesive layer 130 is stored between the edge portion of the wafer 120 and the circuit substrate 110. In contrast, as shown in FIG. 5B, since the buffer wall 136b is disposed between the edge portion of the wafer 120 and the circuit substrate 110, and is disposed along the edge of the wafer projection area 112, between the edge portion of the wafer 120 and the circuit substrate 110, The space G not filled in the adhesive layer 130 can be reduced, so that the fixed area between the edge portion of the chip 120 and the circuit substrate 110 is increased. Therefore, when the mold is poured, even if the impact of the flowing colloid on the edge of the wafer 120 and the circuit substrate 110 is not reduced, the configuration of the buffer wall 136b can still reduce the edge of the wafer 120 being impacted by the flowing colloid on the circuit substrate 110. Chance.

圖6為依照本發明的另一實施例所繪示的半導體封裝結構之製作方法的上視示意圖。FIG. 6 is a schematic top view of a method for manufacturing a semiconductor package structure according to another embodiment of the present invention.

請參閱圖6，圖6的半導體封裝結構100c與圖5A及圖5B的半導體封裝結構100b的主要差異在於，在本實施例中，各緩衝牆136c的形狀為三角形。由於將晶片120覆蓋於黏膠層130上時，黏膠層130可能會向位於主動面122上且外露於貫槽114的多個第二接墊124溢出，進而接觸第二接墊124，因此當各緩衝牆136c的形狀為三角形時，能夠降低黏膠層130溢到第二接墊124的風險。Please refer to FIG. 6. The main difference between the semiconductor package structure 100 c of FIG. 6 and the semiconductor package structure 100 b of FIGS. 5A and 5B is that, in this embodiment, the shape of each buffer wall 136 c is triangular. When the wafer 120 is covered on the adhesive layer 130, the adhesive layer 130 may overflow to the plurality of second pads 124 located on the active surface 122 and exposed in the through groove 114, and then contact the second pads 124. Therefore, When the shape of each buffer wall 136c is triangular, the risk that the adhesive layer 130 spills onto the second pad 124 can be reduced.

圖7為依照本發明的另一實施例所繪示的半導體封裝結構之製作方法的上視示意圖。FIG. 7 is a schematic top view of a method for manufacturing a semiconductor package structure according to another embodiment of the present invention.

請參閱圖7，圖7的半導體封裝結構100d與圖5A及圖5B的半導體封裝結構100b的主要差異在於，在本實施例中，各緩衝牆136d的形狀可為半圓形。當然，緩衝牆136d的形狀不以上述為限制。在另一實施例中，各緩衝牆136d的形狀可為半圓形、多邊形、弧形、不規則形或是上述形狀之組合。Please refer to FIG. 7. The main difference between the semiconductor package structure 100 d of FIG. 7 and the semiconductor package structure 100 b of FIGS. 5A and 5B is that, in this embodiment, the shape of each buffer wall 136 d may be semicircular. Of course, the shape of the buffer wall 136d is not limited to the above. In another embodiment, the shape of each buffer wall 136d may be a semi-circular shape, a polygonal shape, an arc shape, an irregular shape, or a combination thereof.

綜上所述，本發明的半導體封裝結構及其製造方法可以藉由使用來將晶片固定至線路基板的黏膠層的其中一部分形成位於模流口旁的緩衝牆，來使灌模過程中流動膠體在接觸到晶片邊緣之前能夠受到緩衝牆的阻擋而減緩流動速度、減少流動膠體對晶片的邊緣造成衝擊而對晶片產生損傷。此外，本發明的緩衝牆還可以沿著晶片投影區的邊緣配置，增加晶片與線路基板之間的固定面積及減少晶片在靠近邊緣的部位與線路基板之間的空隙，所以當灌模時，流動膠體對晶片的邊緣與線路基板之間的衝擊可被降低，進而降低晶片邊緣被流動膠體內之充填粒子衝擊而相對於線路基板上掀的機率。In summary, the semiconductor package structure and the manufacturing method of the present invention can be used to fix a part of the adhesive layer of the circuit substrate to a part of the adhesive layer of the circuit substrate to form a buffer wall next to the die orifice, so as to flow during the filling process. Before the colloid can contact the edge of the wafer, it can be blocked by the buffer wall to slow down the flow speed and reduce the impact of the flowing colloid on the edge of the wafer and cause damage to the wafer. In addition, the buffer wall of the present invention can also be arranged along the edge of the projection area of the wafer to increase the fixed area between the wafer and the circuit substrate and reduce the gap between the wafer near the edge and the circuit substrate. Therefore, when filling the mold, The impact of the flowing colloid on the edge of the wafer and the circuit substrate can be reduced, thereby reducing the probability that the edge of the wafer is lifted by the filling particles in the flowing colloid relative to the circuit substrate.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

100、100a、100b、100c、100d‧‧‧半導體封裝結構100, 100a, 100b, 100c, 100d‧‧‧ semiconductor package structure

110‧‧‧線路基板110‧‧‧circuit board

111‧‧‧第一面111‧‧‧ the first side

112‧‧‧晶片投影區112‧‧‧ Wafer projection area

113‧‧‧第二面113‧‧‧Second Side

114‧‧‧貫槽114‧‧‧ through groove

115‧‧‧模流口115‧‧‧mould mouth

116‧‧‧第一接墊116‧‧‧The first pad

120‧‧‧晶片120‧‧‧Chip

122‧‧‧主動面122‧‧‧ Active side

124‧‧‧第二接墊124‧‧‧Second pad

130‧‧‧黏膠層130‧‧‧ Adhesive layer

132‧‧‧第一部分132‧‧‧ Part I

134‧‧‧第二部分134‧‧‧Part Two

136、136a、136b、136c、136d‧‧‧緩衝牆136, 136a, 136b, 136c, 136d

138‧‧‧焊球138‧‧‧solder ball

140‧‧‧多條導線140‧‧‧ multiple wires

150‧‧‧封裝膠體150‧‧‧ encapsulated colloid

G‧‧‧間隙G‧‧‧ Clearance

圖1為依照本發明的一實施例所繪示的半導體封裝結構之製作方法的上視示意圖。 圖2為沿圖1之A-A’線的剖面示意圖。 圖3為圖1之前側視圖。 圖4A為依照本發明的另一實施例所繪示的半導體封裝結構之製作方法的上視示意圖。 圖4B為圖4A之A-A’線的剖面示意圖。 圖4C為圖4A之前視示意圖。 圖5A為依照本發明的另一實施例所繪示的半導體封裝結構之製作方法的上視示意圖。 圖5B為沿圖5A之A-A’線的剖面示意圖。 圖6為依照本發明的另一實施例所繪示的半導體封裝結構之製作方法的上視示意圖。 圖7為依照本發明的另一實施例所繪示的半導體封裝結構之製作方法的上視示意圖。FIG. 1 is a schematic top view of a method for fabricating a semiconductor package structure according to an embodiment of the present invention. Fig. 2 is a schematic cross-sectional view taken along the line A-A 'in Fig. 1. FIG. 3 is a side view before FIG. 1. FIG. 4A is a schematic top view of a method for manufacturing a semiconductor package structure according to another embodiment of the present invention. Fig. 4B is a schematic cross-sectional view taken along the line A-A 'in Fig. 4A. FIG. 4C is a schematic front view of FIG. 4A. FIG. 5A is a schematic top view of a method for manufacturing a semiconductor package structure according to another embodiment of the present invention. Fig. 5B is a schematic cross-sectional view taken along the line A-A 'of Fig. 5A. FIG. 6 is a schematic top view of a method for manufacturing a semiconductor package structure according to another embodiment of the present invention. FIG. 7 is a schematic top view of a method for manufacturing a semiconductor package structure according to another embodiment of the present invention.

Claims (10)

一種半導體封裝結構，包括： 線路基板，包括相對的第一面、第二面、貫穿所述第一面與所述第二面的貫槽及位於所述第二面上的多個第一接墊； 晶片，配置於所述線路基板的所述第一面上且覆蓋部分的所述貫槽，所述晶片包括朝向所述第一面的主動面及位於所述主動面上且外露於所述貫槽的多個第二接墊，其中所述貫槽包括未被所述晶片覆蓋的模流口； 黏膠層，配置於所述線路基板的所述第一面與所述晶片之間，且包括延伸至所述模流口旁的至少一緩衝牆； 多條導線，穿過所述貫槽且連接於所述第一接墊及所述第二接墊；以及 封裝膠體，包覆所述線路基板的所述第一面、部分的所述第二面、所述晶片、所述黏膠層及所述多條導線，且填充於所述貫槽及所述模流口。A semiconductor package structure includes: a circuit substrate, including a first surface opposite to a second surface, a through groove penetrating through the first surface and the second surface, and a plurality of first contacts on the second surface. A pad; a wafer disposed on the first surface of the circuit substrate and covering the through groove, the wafer including an active surface facing the first surface and an active surface located on the active surface and exposed to A plurality of second pads penetrating through grooves, wherein the penetrating grooves include die orifices not covered by the wafer; an adhesive layer disposed between the first surface of the circuit substrate and the wafer And includes at least one buffer wall extending to the die orifice; a plurality of wires that pass through the through slot and are connected to the first pad and the second pad; and encapsulating gel, covering The first surface, a portion of the second surface, the wafer, the adhesive layer, and the plurality of wires of the circuit substrate are filled in the through groove and the die orifice. 如申請專利範圍第1項所述的半導體封裝結構，其中所述至少一緩衝牆部分地環繞於所述模流口的外側。The semiconductor package structure according to item 1 of the scope of patent application, wherein the at least one buffer wall partially surrounds the outside of the die orifice. 如申請專利範圍第1項所述的半導體封裝結構，其中所述黏膠層包括第一部分及第二部分，分別配置於所述線路基板的所述第一面上且位於所述貫槽的兩側，兩個所述緩衝牆分別從所述第一部分與所述第二部分沿著所述模流口的輪廓往所述模流口的外側延伸至靠近於彼此。The semiconductor package structure according to item 1 of the scope of patent application, wherein the adhesive layer includes a first part and a second part, which are respectively disposed on the first surface of the circuit substrate and located on two sides of the through groove. On the side, the two buffer walls respectively extend from the first part and the second part along the contour of the die orifice to the outside of the die orifice to close to each other. 如申請專利範圍第1項所述的半導體封裝結構，其中所述黏膠層包括第一部分及第二部分，分別配置於所述線路基板的所述第一面上且位於所述貫槽的兩側，各所述緩衝牆位於所述模流口的外側並沿著所述模流口的輪廓延伸，且各所述緩衝牆分別連接於所述第一部分與所述第二部分，且各所述緩衝牆的輪廓對應於所述模流口的輪廓。The semiconductor package structure according to item 1 of the scope of patent application, wherein the adhesive layer includes a first part and a second part, which are respectively disposed on the first surface of the circuit substrate and located on two sides of the through groove. Side, each of the buffer walls is located outside the mold orifice and extends along the outline of the mold orifice, and each of the buffer walls is respectively connected to the first part and the second part, and each The outline of the buffer wall corresponds to the outline of the die orifice. 如申請專利範圍第1項所述的半導體封裝結構，其中所述線路基板的所述第一面包括晶片投影區，且所述至少一緩衝牆沿著所述晶片投影區的邊緣配置。The semiconductor package structure according to item 1 of the scope of patent application, wherein the first surface of the circuit substrate includes a wafer projection area, and the at least one buffer wall is disposed along an edge of the wafer projection area. 如申請專利範圍第1項所述的半導體封裝結構，其中所述黏膠層包括第一部分及第二部分，分別配置於所述線路基板的所述第一面上且位於所述貫槽的兩側，兩個所述緩衝牆分別從所述第一部分與所述第二部分沿著垂直於所述貫槽的延伸方向朝向所述貫槽延伸。The semiconductor package structure according to item 1 of the scope of patent application, wherein the adhesive layer includes a first part and a second part, which are respectively disposed on the first surface of the circuit substrate and located on two sides of the through groove. On the side, the two buffer walls extend from the first portion and the second portion toward the through groove along an extending direction perpendicular to the through groove, respectively. 如申請專利範圍第5項所述的半導體封裝結構，其中各所述緩衝牆位於所述第一面的形狀為突出的矩形、弧形、三角形、多邊形或前述形狀之組合。The semiconductor package structure according to item 5 of the scope of patent application, wherein the shape of each buffer wall on the first surface is a protruding rectangle, arc, triangle, polygon, or a combination of the foregoing shapes. 一種半導體封裝結構的製造方法，包括： 提供線路基板，其中所述線路基板包括相對的第一面、第二面、貫穿所述第一面與所述第二面的貫槽及位於所述第二面上的多個第一接墊； 形成黏膠層於所述線路基板的所述第一面的靠近所述貫槽處； 設置晶片於所述黏膠層上，且所述晶片覆蓋部分的所述貫槽，其中所述晶片包括朝向所述第一面的主動面及位於所述主動面上且外露於所述貫槽的多個第二接墊，所述貫槽包括未被所述晶片覆蓋的模流口，且所述黏膠層包括延伸至所述模流口旁的至少一緩衝牆； 設置穿過所述貫槽的多條導線，且所述多條導線連接於所述第一接墊及所述第二接墊； 注入流動膠體至所述線路基板、所述黏膠層、所述晶片上，且部分的所述流動膠體從所述第一面經過所述模流口流至所述第二面的所述多條導線上，其中各所述緩衝牆的至少一部分的延伸方向不平行於所述流動膠體的流動方向；以及 固化所述流動膠體而形成封裝膠體，其中所述封裝膠體包覆所述線路基板的所述第一面、部分的所述第二面、所述晶片、所述黏膠層及所述多條導線，且填充於所述貫槽及所述模流口。A method for manufacturing a semiconductor package structure includes: providing a circuit substrate, wherein the circuit substrate includes an opposite first surface, a second surface, a through groove penetrating the first surface and the second surface, and the first substrate is located in the first substrate. A plurality of first pads on two sides; forming an adhesive layer on the first surface of the circuit substrate near the through groove; setting a wafer on the adhesive layer, and covering the portion of the wafer The through slot, wherein the wafer includes an active surface facing the first surface and a plurality of second pads located on the active surface and exposed from the through slot, and the through slot includes a Said die-covered die orifice, and said adhesive layer includes at least one buffer wall extending to said die-die orifice; a plurality of wires passing through said through slot are provided, and said plurality of wires are connected to said die The first pad and the second pad; injecting a flow colloid onto the circuit substrate, the adhesive layer, and the wafer, and a part of the flow colloid passing through the mold from the first surface A nozzle flows onto the plurality of wires on the second side, wherein each of the buffers An extending direction of at least a part of the liquid colloid is not parallel to the flow direction of the flowing colloid; and curing the flowing colloid to form an encapsulating colloid, wherein the encapsulating colloid covers the first surface of the circuit substrate, part of the The second surface, the wafer, the adhesive layer, and the plurality of wires are filled in the through slot and the die orifice. 如申請專利範圍第8項所述的半導體封裝結構的製造方法，其中所述至少一緩衝牆部分地環繞於所述模流口的外側，在注入所述流動膠體的步驟中，部分的所述流動膠體在所述第一面先接觸所述至少一緩衝牆再接觸所述晶片的邊緣。The method for manufacturing a semiconductor package structure according to item 8 of the scope of application, wherein the at least one buffer wall partially surrounds the outside of the die orifice, and in the step of injecting the flow colloid, part of the The flow colloid first contacts the at least one buffer wall on the first surface and then contacts the edge of the wafer. 如申請專利範圍第8項所述的半導體封裝結構的製造方法，其中所述線路基板的所述第一面包括晶片投影區，且所述至少一緩衝牆沿著所述晶片投影區的邊緣配置。The method of manufacturing a semiconductor package structure according to item 8 of the scope of patent application, wherein the first surface of the circuit substrate includes a wafer projection area, and the at least one buffer wall is disposed along an edge of the wafer projection area. .
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