TWI667744B - Fan-out semiconductor package module - Google Patents

Abstract

A fan-out type semiconductor package module includes a core component and a first component. A through-hole and a second through-hole; a semiconductor wafer disposed in the first through-hole and having an active surface and a non-active surface opposite to the active surface, the active surface having a connection pad disposed thereon; at least A first passive component configured in the second through hole; a first encapsulation body encapsulating at least a part of each of the core member and the at least one first passive component; a second encapsulation A body, encapsulating at least a portion of the non-active surface of the semiconductor wafer; and a connecting member disposed on the core member, the active surface of the semiconductor wafer, and the at least one first passive component, and The redistribution layer includes a redistribution layer electrically connected to the connection pad and the at least one first passive component.

Description

Fan-out semiconductor package module

The present disclosure relates to a semiconductor package module that is modularized by mounting a semiconductor chip together with multiple passive components in a single package.

[Cross-reference to related applications]

This application claims the priority of Korean Patent Application No. 10-2017-0086350 filed with the Korean Intellectual Property Office on July 7, 2017, and the Korean Patent Application Number filed with the Korean Intellectual Property Office on October 20, 2017 Priority No. 10-2017-0136769, the entirety of which is incorporated herein by reference.

As the size of displays for mobile devices increases, battery capacity needs to increase. Since the mounting area of a battery increases as the battery capacity increases, it is necessary to reduce the size of a printed circuit board (PCB). The resulting reduction in the installation area of the components can continue to increase the interest in modularization.

Meanwhile, one example of a conventional technology for mounting a plurality of components is a chip on board (COB) technology. COB uses surface mount technology (SMT) Method for mounting individual passive components and semiconductor packages on a PCB. This method may be advantageous in terms of cost, but may require a wider mounting area due to the need to maintain a minimum spacing between components, resulting in a significant increase in electromagnetic interference (EMI) between components, and due to the Significantly long distances between passive components cause increased electrical noise.

One aspect of the present disclosure can provide a fan-out semiconductor package module with a novel structure, which can significantly reduce the mounting area of a semiconductor wafer and multiple passive components, and can significantly reduce the electrical path between the semiconductor wafer and the passive components. The length can still solve the problem of production yield, and electroplating can be used to obtain improved electromagnetic interference (EMI) shielding and heat dissipation effects.

One of the various solutions proposed in this disclosure is to install multiple passive components and semiconductor wafers in a single package in two steps in a packaging process to form a module, and to encapsulate the passive components and semiconductor wafers. In addition, an electromagnetic interference (EMI) shielding and heat dissipation effect can be obtained by applying plating or the like to a package module having such a structure.

According to an aspect of the present disclosure, the fan-out type semiconductor package module may include: a core member having a first through hole and a second through hole spaced apart from each other; and a semiconductor wafer disposed in the first through hole. The semiconductor wafer has an active surface and a non-active surface opposite to the active surface, and the active surface has a connection pad disposed thereon; at least one first passive component is disposed in the second through hole; a first An encapsulation body encapsulating at least a portion of each of the core member and the at least one first passive component, the first encapsulation body filling at least a portion of the second through hole; a second encapsulation A body, encapsulating at least a portion of the non-active surface of the semiconductor wafer, the second encapsulating body filling at least a portion of the first through-hole; and a connecting member disposed in the core member, the semiconductor On the active surface of the chip and the at least one first passive component, the connection member includes a redistribution layer electrically connected to the connection pad and the at least one first passive component.

100A‧‧‧fan-out semiconductor package module

100B‧‧‧fan-out semiconductor package module

100C‧‧‧fan-out semiconductor package module

100D‧‧‧fan-out semiconductor package module

100E‧‧‧fan-out semiconductor package module

100F‧‧‧fan-out semiconductor package module

100G‧‧‧fan-out semiconductor package module

100H‧‧‧fan-out semiconductor package module

100I‧‧‧fan-out semiconductor package module

110‧‧‧Core components

111‧‧‧ Insulation

120‧‧‧Semiconductor wafer

121‧‧‧ Ontology

122‧‧‧Connecting pad

123‧‧‧Passive film

131‧‧‧ the first envelope

132‧‧‧Second Envelope

140‧‧‧ connecting member

141‧‧‧Insulation

142‧‧‧ redistribution layer

143‧‧‧through hole

150‧‧‧ passivation layer

160‧‧‧ metal layer under bump

170‧‧‧electrical connection structure

181‧‧‧metal layer

182‧‧‧Back metal layer

183‧‧‧back hole

190‧‧‧shielding structure

211‧‧‧first adhesive film

212‧‧‧Second adhesive film

500‧‧‧ panel

1000‧‧‧ electronic device

1010‧‧‧Motherboard

1020‧‧‧Chip-related components

1030‧‧‧Network related components

1040‧‧‧Other components

1050‧‧‧ Camera Module

1060‧‧‧antenna

1070‧‧‧Display device

1080‧‧‧ battery

1090‧‧‧Signal line

1100‧‧‧Smartphone

1101‧‧‧Body

1110‧‧‧Motherboard

1120‧‧‧components

1121‧‧‧Semiconductor Package

1130‧‧‧ Camera Module

1150‧‧‧Module

1180‧‧‧battery

2100‧‧‧fan-out semiconductor package

2120‧‧‧Semiconductor wafer

2121‧‧‧ Ontology

2122‧‧‧Connecting pad

2130‧‧‧Encapsulation body

2140‧‧‧Connecting member

2141‧‧‧Insulation

2142‧‧‧ Redistribution Layer

2143‧‧‧through hole

2150‧‧‧ passivation layer

2160‧‧‧Under bump metal layer

2170‧‧‧Solder Ball

2200‧‧‧fan-in semiconductor package

2220‧‧‧Semiconductor wafer

2221‧‧‧ Ontology

2222‧‧‧Connecting pad

2223‧‧‧ passivation layer

2240‧‧‧Connecting member

2241‧‧‧Insulation

2242‧‧‧ Redistribution Layer

2243‧‧‧through hole

2250‧‧‧ passivation layer

2251‧‧‧Opening

2260‧‧‧Under bump metal layer

2280‧‧‧ underfill resin

2290‧‧‧Molding material

2301‧‧‧Printed Circuit Board

2302‧‧‧Printed Circuit Board

2500‧‧‧ Motherboard

1100A‧‧‧mobile device

1100B‧‧‧mobile device

110HA‧‧‧The first through hole

110HB‧‧‧Second Through Hole

110HC‧‧‧Third through hole

110HD‧‧‧Fourth through hole

110HE‧‧‧Fifth through hole

110HF‧‧‧Sixth through hole

111a‧‧‧First insulation layer

111b‧‧‧Second insulation layer

111c‧‧‧Third insulation layer

112a‧‧‧conductive layer / first wiring layer

112b‧‧‧conductive layer / second wiring layer

112c‧‧‧Third wiring layer

112d‧‧‧Fourth wiring layer

113a‧‧‧First through hole

113b‧‧‧Second through hole

113c‧‧‧Third through hole

125A‧‧‧The first passive component

125B‧‧‧Second passive component

125C‧‧‧The third passive component

125D‧‧‧The fourth passive component

125E‧‧‧The fifth passive component

125F‧‧‧The sixth passive component

2243h‧‧‧Through Hole

I-I'‧‧‧ hatch

The embodiments are exemplified below and described in detail in conjunction with the accompanying drawings. The above and other aspects, features, and advantages of the present invention will be more obvious and understandable. In the attached drawings: FIG. 1 is a diagram illustrating an electronic device system. Block diagram of the example.

FIG. 2 is a schematic perspective view illustrating an example of an electronic device.

3A and 3B are schematic cross-sectional views illustrating a state of the fan-in semiconductor package before and after the package.

FIG. 4 is a schematic cross-sectional view illustrating a manufacturing process of a package fan-in semiconductor package.

5 is a schematic cross-sectional view illustrating a fan-in semiconductor package mounted on a printed circuit board (PCB) and finally mounted on a main board of an electronic device.

6 is a schematic cross-sectional view illustrating a fan-in semiconductor package embedded in a printed circuit board and finally mounted on a main board of an electronic device.

FIG. 7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package.

8 is a cross-sectional view illustrating a fan-out type semiconductor package mounted on a main board of an electronic device; 视 Schematic.

FIG. 9 is a schematic cross-sectional view illustrating an example of a fan-out type semiconductor package module.

FIG. 10 is a schematic plan view of a cutting plane taken along a section line II ′ of the fan-out semiconductor package module of FIG. 9.

11 is a schematic cross-sectional view illustrating an example of a panel used to manufacture the fan-out type semiconductor package module of FIG. 9.

12A, 12B, 12C, and 12D are schematic cross-sectional views illustrating an example of a manufacturing process of manufacturing the fan-out semiconductor package module of FIG. 9.

13 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package module.

FIG. 14 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package module.

15 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package module.

FIG. 16 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package module.

FIG. 17 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package module.

18 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package module.

19 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package module. as well as 20 is a schematic plan view illustrating an effect obtained by using a fan-out type semiconductor package module according to an exemplary embodiment in an electronic device.

FIG. 21 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package module.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

This disclosure may, however, be exemplified in many different forms and should not be construed as limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

Throughout this specification, it will be understood that when an element such as a layer, region, or wafer (substrate) is referred to as being "on another element", "connected to another element", or "coupled to another element" ", It can be" directly on, "" directly connected to, "or" coupled to, "another element, or there can be other elements in between. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there may be no other elements or layers in between. Identical symbols always refer to the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

Obviously, although the terms "first", "second", "third", etc. may be used herein to describe various components, components, regions, layers, and / or sections, but These components, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one component, component, region, layer or section from another region, layer or section. Thus, a first component, component, region, layer, or section discussed below can be termed a second component, component, region, layer, or section without departing from the teachings of the exemplary embodiments.

For ease of description, spatial relative terms, such as "above," "above," "below," and "below", can be used herein to describe the relationship of one element relative to another, as shown in the figure. It will be understood that in addition to the orientation depicted in the drawings, spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is turned over, elements described as “above” or “upper” relative to other elements would then be positioned “below” or “down” relative to the other elements or features. Therefore, the term "above" can cover both the upper and lower orientations, depending on the specific orientation of the drawing. The device may be otherwise positioned (rotated 90 degrees or positioned in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

The terminology used herein describes only specific embodiments, and the disclosure is not limited thereto. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "comprising" when used in this specification specifies the existence of stated features, wholes, steps, operations, components, elements and / or groups thereof, but does not exclude one or more other The presence or addition of features, wholes, steps, operations, components, elements, and / or groups thereof.

Hereinafter, the present invention will be described with reference to a schematic diagram illustrating an embodiment of the present disclosure. Disclosed examples. In the drawings, for example, modifications in the shapes shown can be estimated due to manufacturing techniques and / or tolerances. Therefore, the embodiments of the present disclosure should not be construed as being limited to the specific shape of the regions shown herein to include, for example, shape changes caused by manufacturing. The following embodiments may also be constituted individually or as a combination of several or all of them.

The contents of the present disclosure described below may have various configurations, and only the required configurations are proposed in this article, but the present disclosure is not limited thereto.

Hereinafter, exemplary embodiments in the present disclosure will be described with reference to the drawings. For clarity, the shapes or sizes of components shown in the drawings have been exaggerated.

Electronic device

FIG. 1 is a block diagram illustrating an example of an electronic device system.

Referring to FIG. 1, the electronic device 1000 can house a motherboard 1010. The motherboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, and the like, which are physically and / or electrically connected to the motherboard 1010. These components can be connected to other components described below to form various signal lines 1090.

The chip-related component 1020 may include a memory chip, such as a volatile memory (such as dynamic random access memory (DRAM)), a non-volatile memory (such as read only memory, ROM)), flash memory, etc .; application processor chips, such as a central processing unit (for example: central processing unit (CPU)), a graphics processor (for example: graphics processing unit (GPU)) ), Digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc .; and logic chips such as analog-to-digital converters converter), application-specific integrated circuit (ASIC), etc. However, the wafer-related component 1020 is not limited thereto, and may include other types of wafer-related components. In addition, the wafer-related components 1020 may be combined with each other.

The network-related component 1030 may include, for example, the following protocols: wireless fidelity (Wi-Fi) (Institute of Electrical And Electronics Engineers (IEEE) 802.11 family, etc.), global interoperable microwave access ( worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high-speed packet access + (high speed packet access +, HSPA +), high speed downlink packet access + (HSDPA +), high speed uplink packet access + (HSUPA +), enhanced data GSM environment (enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access ( code division multiple access (CDMA), time division multiple access (TDMA) Digital Enhanced Cordless Telecommunications (digital enhanced cordless telecommunications, DECT), Bluetooth, 3G agreement, 4G agreement, 5G agreements and any other wireless and wireline protocol agreement following the agreement specified above. However, the network related component 1030 is not limited to this, and may include a variety of Other wireless standards or protocols or wired standards or protocols. In addition, the network related components 1030 may be combined with each other together with the chip related components 1020 described above.

Other components 1040 may include high frequency inductors, ferrite inductors (ferrite inductors) inductor, power inductor, ferrite beads, low temperature co-fired ceramic (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (multilayer ceramic capacitor, MLCC). However, the other components 1040 are not limited thereto, and may include passive components and the like for various other purposes. In addition, other components 1040 may be combined with each other together with the chip-related component 1020 and / or the network-related component 1030.

Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may be physically and / or electrically connected to the motherboard 1010 or may not be physically and / or electrically connected to the motherboard 1010. Other components may include, for example, a camera module 1050, an antenna 1060, a display device 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass ( (Not shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage unit (such as a hard disk drive) (not shown), compact disk, CD) drive (not shown), digital versatile disk (DVD) drive (not shown), and the like. However, other components are not limited thereto, and other components for various other purposes may be included depending on the type of the electronic device 1000 and the like.

The electronic device 1000 may be a smart phone, a personal digital assistant (personal digital assistant (PDA), digital camera, digital still camera, network system, computer, monitor, tablet personal computer (PC), notebook personal computer, portable personal computer (netbook PC), TV, video game machine, smart watch or car component, etc. However, the electronic device 1000 is not limited thereto, and may be any other electronic device capable of processing data.

FIG. 2 is a schematic perspective view illustrating an example of an electronic device.

Referring to FIG. 2, the semiconductor package 1121 may be used in various electronic devices described above for various purposes. For example, the motherboard 1110 may be housed in the body 1101 of the smart phone 1100, and may have various components 1120 that are physically and / or electrically connected to the motherboard 1110. In addition, other components (for example, the camera module 1130) that can be physically or electrically connected to the motherboard 1110 or can be physically or electrically connected to the motherboard 1110 can be accommodated in the body 1101. Some of the components 1120 may be the aforementioned wafer-related components, such as the semiconductor package 1121, but the aforementioned wafer-related components are not limited thereto. The electronic device is not limited to the smart phone 1100, and may be other electronic devices described above.

Semiconductor package

Generally speaking, many microelectronic circuits are integrated in semiconductor wafers. However, the semiconductor wafer itself may not be used as a completed semiconductor product, and may be damaged due to external physical or chemical influences. Therefore, the semiconductor wafer itself is not used, but is packaged in an electronic device or the like and used in a packaged state.

In terms of electrical connection, a circuit width difference between a semiconductor chip and a motherboard of an electronic device requires a semiconductor package. In detail, semiconductor crystals The size of the connection pads of the wafer and the interval between the connection pads can be very fine, but the size of the component mounting pads and the interval between the component mounting pads for the motherboard of the electronic device can be significantly larger than the specifications of the semiconductor wafer. Therefore, it may be difficult to mount a semiconductor wafer directly on a motherboard, and packaging technology for reducing a difference in circuit width between the semiconductor wafer and the motherboard may be required.

Depending on the structure and purpose of the semiconductor package, semiconductor packages manufactured by such packaging technologies can be divided into fan-in semiconductor packages and fan-out semiconductor packages.

The fan-in type semiconductor package and the fan-out type semiconductor package will be described in more detail below with reference to the drawings.

Fan-in semiconductor package

3A and 3B are schematic cross-sectional views illustrating a state of the fan-in semiconductor package before and after the package.

FIG. 4 is a schematic cross-sectional view illustrating a manufacturing process of a package fan-in semiconductor package.

4, the semiconductor wafer 2220 may be, for example, an integrated circuit (IC) in an exposed state. The semiconductor wafer 2220 includes a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs), and the like; a connection pad 2222 Is formed on one surface of the body 2221 and includes a conductive material, such as aluminum (Al); and a passivation layer 2223, such as an oxide film, a nitride film, etc., is formed on one surface of the body 2221 and covers at least a part of Connection pad 2222. Because the connection pad 2222 is very small, it may be difficult to mount the integrated circuit on an intermediate-level printed circuit board (PCB) and on a motherboard of an electronic device.

Therefore, depending on the size of the semiconductor wafer 2220, A connection member 2240 is formed on 2220 to rewire the connection pad 2222. The connecting member 2240 can be formed by the following steps: forming an insulating layer 2241 on the semiconductor wafer 2220 using an insulating material such as a photosensitive insulating resin (PID); forming a through hole 2243h in the insulating layer 2241 exposing the connection pad 2222; And forming a redistribution layer 2242 and a through hole 2243. Next, a passivation layer 2250 for protecting the connection member 2240, an opening part 2251, and a under bump metal layer 2260, etc. may be formed. That is, the fan-in type semiconductor package 2200 including, for example, the semiconductor wafer 2220, the connection member 2240, the passivation layer 2250, and the under bump metal layer 2260 may be manufactured through a series of sub-processes.

As described above, the fan-in type semiconductor package may have a package form in which connection pads of a semiconductor wafer (for example, all input / output (I / O) terminals) may be arranged in the semiconductor wafer, may have improved electrical characteristics, and Can be produced at low cost. As a result, many components embedded in smart phones have been manufactured in the form of fan-in semiconductor packages. In detail, components have been developed that allow fast signal transmission while having a small size.

However, since all the input / output terminals need to be arranged inside the semiconductor wafer of the fan-in type semiconductor package, the fan-in type semiconductor package may have a significant space limitation. Therefore, it may be difficult to apply such a structure to a semiconductor wafer having a large number of input / output terminals, or to a semiconductor wafer having a small size. In addition, due to the above disadvantages, a fan-in semiconductor package may not be directly mounted on a motherboard of an electronic device for use. Even when the size of an input / output terminal of a semiconductor wafer and the interval therebetween are expanded by a rewiring process, a fan-in type semiconductor package There may not be a size or spacing sufficient for direct mounting on the motherboard of an electronic device.

5 is a schematic cross-sectional view illustrating a fan-in semiconductor package mounted on a printed circuit board and finally mounted on a motherboard of an electronic device.

6 is a schematic cross-sectional view illustrating a fan-in semiconductor package embedded in a printed circuit board and finally mounted on a main board of an electronic device.

Referring to FIG. 5, in the fan-in semiconductor package 2200, a second rewiring of the connection pads 2222 (for example, input / output terminals) of the semiconductor wafer 2220 through the printed circuit board 2301, and the fan-in semiconductor package 2200 It can be mounted on the printed circuit board 2301 and finally mounted on the main board 2500 of the electronic device. Here, the solder ball or the like can be fixed by underfill resin 2280 or the like, and the outer surface thereof can be covered with a molding material 2290 or the like. Alternatively, the fan-in type semiconductor package 2200 may be embedded in a separate printed circuit board 2302, while being embedded in the printed circuit board 2302, the printed circuit board 2302 may be used to connect the semiconductor wafer 2220 to the pad 2222 (for example, input / output terminals). ) For rewiring, and can finally be mounted on the motherboard 2500 of the electronic device.

As described above, it may be difficult to mount a fan-in semiconductor package directly on a motherboard of an electronic device for use. Therefore, the fan-in semiconductor package can be mounted on a separate printed circuit board, and then can be mounted on the main board of the electronic device through a packaging process, or can be mounted on the main board of the electronic device while being embedded in the printed circuit board. For use.

Fan-out semiconductor package

FIG. 7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package.

Referring to FIG. 7, in the fan-out type semiconductor package 2100, for example, the outer surface of the semiconductor wafer 2120 may be protected by the encapsulation body 2130, and the connection pad 2122 of the semiconductor wafer 2120 may be directed toward the outside of the semiconductor wafer 2120 by the connection member 2140. Perform rewiring. A passivation layer 2150 may be further formed on the connection member 2140, and an under bump metal layer 2160 may be further formed in an opening portion of the passivation layer 2150. A solder ball 2170 may be further formed on the under bump metal layer 2160. The semiconductor wafer 2120 may be an integrated circuit including a body 2121, a connection pad 2122, a passivation layer, and the like. The connection member 2140 may include an insulating layer 2141, a redistribution layer 2142 formed on the insulating layer 2141, and a through hole 2143 for electrically connecting the connection pad 2122 and the redistribution layer 2142.

As described above, the fan-out type semiconductor package may have a structure in which the input / output terminals of the semiconductor wafer can be re-wired out of the semiconductor wafer by the connection member formed on the semiconductor wafer. As described above, in a fan-in type semiconductor package, all input / output terminals of a semiconductor wafer need to be arranged inside the semiconductor wafer. Therefore, when the size of the semiconductor wafer is reduced, the size and pitch of the balls need to be reduced, so that a standardized ball layout may not be used in a fan-in semiconductor package. On the other hand, as described above, the fan-out type semiconductor package may have a structure in which the input / output terminals of the semiconductor wafer are rewired out of the semiconductor wafer by the connection member formed on the semiconductor wafer. Therefore, even when the size of the semiconductor wafer is reduced, the standardized solder ball layout can be used as it is in a fan-out type semiconductor package, so that the fan-out type semiconductor package can be mounted on the main board of an electronic device without a separate printed circuit board as follows As described.

FIG. 8 illustrates mounting of a fan-out semiconductor package on a motherboard of an electronic device Cutaway schematic.

Referring to FIG. 8, the fan-out type semiconductor package 2100 may be mounted on the main board 2500 of the electronic device through a solder ball 2170 or the like. For example, as described above, the fan-out type semiconductor package 2100 may include a connection member 2140 formed on the semiconductor wafer 2120 to enable rewiring of the connection pad 2122 to a fan-out type area outside the semiconductor wafer 2120, so that the standardized ball layout may be used as it is For fan-out semiconductor package 2100. Therefore, the fan-out type semiconductor package 2100 can be mounted on the main board 2500 of the electronic device without a separate printed circuit board or the like.

As described above, since a fan-out type semiconductor package can be mounted on a main board of an electronic device without a separate printed circuit board, the fan-out type semiconductor package can have a smaller thickness than a fan-in type semiconductor package using a printed circuit board. Therefore, the fan-out type semiconductor package can be miniaturized and thinned. In addition, the fan-out type semiconductor package may have improved thermal and electrical characteristics, and thus the fan-out type semiconductor package may be particularly suitable for use in mobile products. In addition, the fan-out type semiconductor package can be smaller in size than a general package-on-package (POP) type semiconductor package using a printed circuit board, and can solve problems caused by the warping phenomenon.

The fan-out type semiconductor package may refer to a packaging technology for mounting a semiconductor wafer on a motherboard or the like of an electronic device as described above and protecting the semiconductor wafer from external impact. The fan-out type semiconductor package may be conceptually different from a printed circuit board or the like having a different specification, purpose, etc. from the fan-out type semiconductor package and having the fan-in type semiconductor package embedded therein.

Semiconductor package module

FIG. 9 is a schematic cross-sectional view illustrating an example of a fan-out type semiconductor package module.

FIG. 10 is a schematic plan view of a cutting plane taken along a section line II ′ of the fan-out semiconductor package module of FIG. 9.

Referring to FIGS. 9 and 10, a fan-out semiconductor package module 100A according to an example may include: a core member 110 having first through holes 110HA to sixth through holes 110HF; and a semiconductor wafer 120 disposed at the first through holes 110HA. Inside, there is an active surface and a non-active surface opposite to the active surface, and the active surface is provided with a connection pad 122; at least one first passive component 125A is disposed in the second through hole 110HB; at least one second passive Module 125B is disposed in the third through-hole 110HC; at least one third passive component 125C is disposed in the fourth through-hole 110HD; at least one fourth passive component 125D is disposed in the fifth through-hole 110HE; at least one fifth The passive component 125E is disposed in the sixth through-hole 110HF; the first encapsulating body 131, encapsulating the core member 110 and at least a part of each of the first to fifth passive components 125A to 125E and filling the second through-hole At least a part of each of the holes 110HB to the sixth through-hole 110HF; the second encapsulation body 132 that encloses at least a portion of the non-active surface of the semiconductor wafer 120 and fills at least a portion of the first through-hole 110HA; The component 140 is disposed on the core member 110, the active surface of the semiconductor wafer 120, and the first passive component 125A to the fifth passive component 125E, and includes an electrical connection to the connection pad 122 and an electrical connection to the first passive component 125A. The redistribution layer 142 to the fifth passive component 125E; the passivation layer 150 is disposed on the connection member 140; the under bump metal layer 160 is formed in the opening portion of the passivation layer 150 and is electrically connected to the redistribution layer 142; And an electrical connection structure 170 disposed on the metal layer 160 under the bump And is electrically connected to the redistribution layer 142 through the under bump metal layer 160.

As the size of displays for mobile devices increases, so does the demand for increased battery capacity. Because the battery mounting area in mobile devices changes as battery capacity increases, the size of printed circuit boards needs to be reduced. The resulting reduction in the installation area of the components can continue to increase the interest in modularization. One example of a conventional technology for mounting multiple components is a chip-on-board (COB) technology. COB is a method of mounting individual passive components and semiconductor packages on a printed circuit board using surface mount technology (SMT). This approach may be advantageous in terms of cost, but may require a wider mounting area due to the significant reduction in the spacing reserved between components, which may result in a significant increase in electromagnetic interference (EMI) between components, and may be due to The relatively long distance between semiconductor wafers and passive components causes increased electrical noise.

In contrast, in the fan-out type semiconductor package module 100A, according to an example, the first passive component 125A to the fifth passive component 125E may be arranged in a single package together with the semiconductor wafer 120 to be modularized. Therefore, the significantly reduced spacing between components can significantly reduce the mounting area on a printed circuit board such as a motherboard. In addition, the length of the electrical path between the semiconductor wafer 120 and the first passive component 125A to the fifth passive component 125E can be significantly reduced, thereby solving the problem of noise. Specifically, the first passive component 125A to the fifth passive component 125E may undergo an encapsulation process of two or more steps instead of a one-step encapsulation process, thus significantly reducing the number of installations from the first passive component 125A to the fifth. The impact on the installation yield and the effects of foreign substances caused by the passive component 125E.

In detail, the surface mounting of the first to fifth passive components 125A to 125E may be relatively easy. However, since the surface mounting of the semiconductor wafer 120 may require high accuracy and a clean environment, the surface mounting of the semiconductor wafer 120 may be relatively difficult. Therefore, when the process of installing and encapsulating the first passive component 125A to the fifth passive element 125E and the process of installing and encapsulating the semiconductor wafer 120 are performed separately, the influence on the installation yield and the foreign material effect in the two processes, etc. Can be significantly reduced. Specifically, after mounting and encapsulating the first passive component 125A to the fifth passive component 125E, the relatively expensive semiconductor wafer 120 can be mounted only on a single good-quality unit by a precision process, and thus has a high yield. In addition, the first passive component 125A to the fifth passive component 125E and / or the semiconductor wafer 120 having various thicknesses can be stably fixed, and various problems caused by thickness variations can be solved.

Hereinafter, individual components included in the fan-out type semiconductor package module 100A according to an example will be described in more detail.

According to the material type, the core member 110 can further increase the rigidity of the fan-out semiconductor package module 100A, and can be used to ensure the uniform thickness of the first encapsulation body 131 and the second encapsulation body 132. The core member 110 may have a first through hole 110HA to a sixth through hole 110HF. The first through sixth through holes 110HA to 110HF may be physically separated from each other. The semiconductor wafer 120, the first passive component 125A, the second passive component 125B, the third passive component 125C, the fourth passive component 125D, and the fifth passive component 125E may be respectively disposed in the first through hole 110HA, the second through hole 110HB, and the first Within the three through holes 110HC, the fourth through holes 110HD, the fifth through holes 110HE, and the sixth through holes 110HF. Semiconductor wafer 120, first passive component 125A, second The passive component 125B, the third passive component 125C, the fourth passive component 125D, and the fifth passive component 125E may be separated from the wall surface of the first through hole 110HA, the wall surface of the second through hole 110HB, and the third through hole 110HC by a predetermined distance, respectively. The wall surface, the wall surface of the fourth through hole 110HD, the wall surface of the fifth through hole 110HE, and the wall surface of the sixth through hole 110HF are spaced to be surrounded by the wall surface. Such a structure can be modified.

The core member 110 may include an insulating layer 111. The material of the insulating layer 111 is not particularly limited. For example, the material of the insulating layer 111 may be an insulating material. The insulating material may be a thermosetting resin such as epoxy resin; a thermoplastic resin such as polyimide; or such as prepreg, Ajinomoto Build up Film (ABF), FR-4 or Shuangma Resin imide triazine (Bismaleimide Triazine, BT) and other resins, in which the core (such as inorganic fillers, glass fibers, glass cloth or glass fabric) is impregnated with thermosetting resins and thermoplastic resins. Alternatively, a photosensitive imaging dielectric (PID) resin may be used.

The core member 110 may include a conductive layer 112 a and a conductive layer 112 b disposed on opposite surfaces of the insulating layer 111. The conductive layer 112a and the conductive layer 112b may be used as a mark pattern to form the first through hole 110HA to the sixth through hole 110HF, or to configure the semiconductor wafer 120 and the first passive component 125A to the fifth passive component 125E. Alternatively, the conductive layer 112a and the conductive layer 112b may be used as a wiring pattern. For example, the conductive layer 112a and the conductive layer 112b may be a ground pattern. The material of each of the conductive layer 112a and the conductive layer 112b may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb) , Titanium (Ti) or its alloy, but Not limited to this.

The semiconductor wafer 120 may be an integrated circuit provided by integrating a number of components of hundreds to millions or more in a single wafer. The integrated circuit may be, for example, a power management integrated circuit (PMIC), but is not limited thereto. The semiconductor wafer may be an integrated circuit in an exposed state, in which a separate bump or a redistribution layer is not formed. Integrated circuits can be formed on the basis of active wafers. In this case, silicon (Si), germanium (Ge), or gallium arsenide (GaAs) may be used as a base material for forming the body 121 of the semiconductor wafer. The body 121 may have various types of circuits formed therein. The connection pad 122 can electrically connect the semiconductor wafer 120 to other components, and the material of the connection pad 122 can be a conductive material, such as aluminum (Al), but it is not particularly limited. The body 121 may have a passivation film 123 formed thereon so that the connection pad 122 is exposed, and the passivation film 123 may be an oxide film, a nitride film, or a double layer composed of an oxide film and a nitride film. An insulating film (not shown) and the like may be further disposed in other required positions.

Each of the first to fifth passive components 125A to 125E may be a multilayer ceramic capacitor (MLCC), a low inductance chip capacitor (LICC), an inductor, or a bead independently. The first to fifth passive components 125A to 125E may have different thicknesses. In addition, each of the first to fifth passive components 125A to 125E may have a thickness different from that of the semiconductor wafer 120. According to an example, the fan-out type semiconductor package module 100A may allow the first passive component 125A to the fifth passive component 125E and the semiconductor wafer 120 to be encapsulated in two or more steps, thereby significantly reducing the thickness-induced The number of defects. First passive component 125A The number of the fifth to fifth passive components 125E is not particularly limited, and may be more or less than that shown in the drawings.

The first encapsulation body 131 may encapsulate at least a part of each of the first to fifth passive components 125A to 125E. In addition, the first encapsulation body 131 may fill at least a part of each of the second through sixth through holes 110HB to 110HF. In addition, the first encapsulation body 131 may cover at least a part of the core member 110. The first encapsulation body 131 may include an insulating material. The insulating material may be a material including an inorganic filler and an insulating resin, such as a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or especially ABF, FR-4 resin, BT resin, PID resin, etc. Resins in which hardeners such as inorganic fillers are included in thermosetting resins and thermoplastic resins. In addition, a known molding material such as an epoxy molding compound, a molding compound (EMC), and the like, and a photosensitive material such as a photosensitive imaging encapsulant (PIE) can also be used. It is also possible to use a material (such as an inorganic filler, glass fiber, glass cloth, or glass fabric) impregnated with an insulating resin (such as a thermosetting resin or a thermoplastic resin).

The second encapsulation body 132 may encapsulate at least a portion of the semiconductor wafer 120. In addition, the second encapsulation body 132 may fill at least a portion of the first through hole 110HA. In addition, the second encapsulation body 132 may cover at least a portion of the first encapsulation body 131. The second encapsulation body 132 may also include an insulating material. The insulating material may be a material including an inorganic filler and an insulating resin, such as a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or especially ABF, FR-4 resin, BT resin, PID resin, etc. Resins, including hardeners (such as inorganic fillers) in thermosetting and thermoplastic resins material). In addition, known molding materials such as EMC can also be used. It is also possible to use a material (such as an inorganic filler, glass fiber, glass cloth, or glass fabric) impregnated with an insulating resin (such as a thermosetting resin or a thermoplastic resin).

The first encapsulation body 131 and the second encapsulation body 132 may include the same material, and may also include different materials. Even when the first encapsulation body 131 and the second encapsulation body 132 include the same material, a boundary or interface therebetween can be identified. The first encapsulation body 131 and the second encapsulation body 132 may include similar materials, but may have different colors. For example, the first encapsulation body 131 may be more transparent than the second encapsulation body 132. Therefore, the boundary or interface between them may be obvious.

The connection member 140 may rewire the connection pads 122 of the semiconductor wafer 120. In addition, the connection member 140 may electrically connect the semiconductor wafer 120 to the first to fifth passive components 125A to 125E. The connection pads 122 of tens to hundreds of semiconductor wafers 120 having various functions can be rewired by the connection member 140, and depending on their functions, they can be physically connected and / or electrically connected to an external power source through the electrical connection structure 170. connection. The connection member 140 may include an insulating layer 141; a redistribution layer 142 disposed on the insulating layer 141; and a through hole 143 passing through the insulating layer 141 and connecting the redistribution layer 142. The connection member 140 may include a single layer, and may also include a larger number of layers than those shown in the drawings.

The material of the insulating layer 141 may be an insulating material. In addition to the above-mentioned insulating material, the insulating material may be a photosensitive insulating material such as a PID resin. For example, the insulating layer 141 may be a photosensitive insulating layer. When the insulating layer 141 has a photosensitive property, the insulating layer 141 may have a further reduced thickness, and the precision of the through hole 143 may be more easily achieved. spacing. The insulating layer 141 may be a photosensitive insulating layer including an insulating resin and a filler. When the insulating layer 141 includes multiple layers, the materials of the insulating layers 141 may be the same as each other, and may also be different from each other. When the insulating layer 141 includes multiple layers, the multiple layers may be integrally formed depending on a process, so that a boundary therebetween may not be easily apparent.

The rewiring layer 142 may be used to substantially rewiring the connection pad 122. The material of the redistribution layer 142 may be a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti ) Or any of its alloys. Depending on the design of its layers, the redistribution layer 142 may perform various functions. For example, the redistribution layer 142 may include a ground pattern, a power pattern, a signal pattern, and the like. Here, the signal pattern may include various signals other than a ground pattern, a power pattern, and the like, such as a data signal. In addition, the redistribution layer 142 may include a via pad, a connection terminal pad, and the like.

The through-holes 143 may electrically connect the redistribution layer 142, the connection pad 122, the first passive component 125A to the fifth passive component 125E, etc. formed in different layers to each other to cause electrical conductivity in the fan-out semiconductor package module 100A. Formation of pathways. The through hole 143 may be in physical contact with the connection pad 122 and the first to fifth passive components 125A to 125E. For example, the semiconductor wafer 120 may be directly connected to the through-hole 143 of the connecting member 140 in a die form without a separate bump or the like, and the first passive component 125A to the fifth passive component 125E may use solder bumps or the like to be embedded. The surface mount form is directly connected to the through hole 143 of the connection member 140. The material of the through hole 143 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) Or any of its alloys. The through hole 143 can be made of conductive material A completely filled material or a conductive material may also be formed along the wall surface of the through hole 143. In addition, the through hole 143 may have all shapes known in the related art, such as a tapered shape, a cylindrical shape, and the like.

The passivation layer 150 may protect the connection member 140 from external physical or chemical damage. The passivation layer 150 may have an opening portion to expose at least a portion of the redistribution layer 142 of the connection member 140. The opening portion may be formed in the passivation layer 150 in a number of tens to thousands. The passivation layer 150 may include an insulating resin and an inorganic filler, and may not include glass fibers. For example, the passivation layer 150 may be ABF, but is not limited thereto.

The under-bump metal layer 160 can increase the connection reliability of the electrical connection structure 170, resulting in an increase in board-level reliability of the fan-out semiconductor package module 100A. The under bump metal layer 160 may be connected to the redistribution layer 142 of the connection member 140 exposed by the opening portion of the passivation layer 150. The under bump metal layer 160 may be formed in the opening portion of the passivation layer 150 by a known metallization method using a known conductive material (eg, metal), and the method of forming the under bump metal layer 160 is not limited to this.

The electrical connection structure 170 may be an additional component for physically and / or electrically connecting the fan-out semiconductor package module 100A to an external power source. For example, the fan-out type semiconductor package module 100A can be mounted on the motherboard of the electronic device through the electrical connection structure 170. The electrical connection structure 170 may be formed of a conductive material such as solder. However, this is merely an example, and the material of the electrical connection structure 170 is not particularly limited. The electrical connection structure 170 may be a pin, a ball, or a pin. The electrical connection structure 170 may include a single layer or multiple layers. When the electrical connection structure 170 includes multiple layers, the electrical connection structure 170 may include copper pillars and solder. When the electrical connection structure 170 includes a single layer, the electrical connection structure 170 may include tin-silver solder or copper. However, this is only an example, and the electrical connection The material of the connection structure 170 is not limited thereto. The number, interval, or configuration of the electrical connection structures 170 are not particularly limited, and can be easily modified by those with ordinary knowledge in the art based on design details. For example, tens to thousands of electrical connection structures 170 may be provided according to the number of connection pads 122, and electrical connection structures 170 may also be provided in an amount of not less than or not more than tens to thousands.

At least one of the electrical connection structures 170 may be disposed in the fan-out area. The fan-out area may refer to an area other than an area where the semiconductor wafer 120 may be disposed. Compared with a fan-in type semiconductor package, a fan-out type semiconductor package can have improved reliability, can have multiple input / output terminals, and can facilitate 3D interconnection. In addition, compared to ball grid array (BGA) semiconductor packages, land grid array (LGA) semiconductor packages, etc., fan-out semiconductor packages can be manufactured with reduced thickness and improved price competition force.

11 is a schematic cross-sectional view illustrating an example of a panel used to manufacture the fan-out type semiconductor package module of FIG. 9.

Referring to FIG. 11, according to an example, a fan-out type semiconductor package module 100A may be manufactured using a panel 500 having a large size. The size of the panel 500 may be two to four times more than the size of an ordinary wafer. Therefore, a larger number of fan-out semiconductor package modules 100A can be manufactured in a single process including a series of sub-processes. The panel 500 may have a square or a rectangle. As a result, productivity can increase significantly. Specifically, as the size of each fan-out semiconductor package module 100A increases, compared with the case where a wafer-out semiconductor package module 100A is manufactured using a wafer, productivity can be relatively increased. Each unit of the panel 500 may be a manufacturing fan-out type semiconductor package module which will be described later. The core member 110 is initially prepared in the method. The panel 500 may be used to simultaneously manufacture a plurality of fan-out semiconductor package modules 100A by a single process including a series of sub-processes, and then the fan-out semiconductor packages may be packaged by a known dicing process such as a dicing process. The module 100A is cut into individual fan-out semiconductor package modules 100A.

12A to 12D are schematic cross-sectional views illustrating an example of a manufacturing process of manufacturing the fan-out type semiconductor package module of FIG. 9.

Referring to FIG. 12A, a core member 110 may be first prepared. The core member 110 may be formed by preparing a copper clad laminate (CCL) as the panel 500 and then patterning the copper foil of the copper clad laminate into a conductive layer 112a and a conductive layer 112b. Subsequently, each of the second to sixth through holes 110HB to 110HF may be formed in the core member 110. FIG. 12A is a sectional view showing only the second through hole 110HB and the third through hole 110HC. However, the fourth through hole 110HD to the sixth through hole 110HF may be formed. Depending on the material of the insulating layer 111, each of the second through hole 110HB to the sixth through hole 110HF may be formed by a laser drilling process and / or a mechanical drilling process. In some cases, sandblasting or chemical processes can also be used. Subsequently, the first adhesive film 211 may be attached to the lower surface of the core member 110, and the first passive component 125A to the fifth passive component 125E may be disposed in the second through hole 110HB to the sixth through hole 110HF. The first adhesive film 211 may be a known tape, but is not limited thereto.

Referring to FIG. 12B, the core member 110 and the first to fifth passive components 125A to 125E may be encapsulated by the first encapsulation body 131. The first encapsulation body 131 can be A method of laminating a film in an uncured state and curing the film may also be formed by a method of applying and curing a liquid material. Subsequently, the first adhesive film 211 may be removed. The method of removing the first adhesive film 211 may be a mechanical method. Subsequently, the first through hole 110HA may be formed in the core member 110. The first through hole 110HA can penetrate the stacked structure including the core member 110 and a portion of the first encapsulation body 131 disposed on the core member 110. Depending on the material of the insulating layer 111, the first through hole 110HA may also be formed by a laser drilling process and / or a mechanical drilling process. In some cases, sandblasting or chemical processes can also be used. In the process of forming the first through hole 110HA, a region of the first encapsulation body 131 corresponding to the first through hole 110HA may be penetrated.

12C, the second adhesive film 212 may be attached to the lower surface of the core member 110, and the semiconductor wafer 120 may be disposed in the first through hole 110HA. The semiconductor wafer 120 may be configured in a face-down manner. The second adhesive film 212 may also be a known tape, but is not limited thereto. Subsequently, the first encapsulation body 131 and the semiconductor wafer 120 may be encapsulated by the second encapsulation body 132. The second encapsulant 132 may be formed by a method of laminating a film in an uncured state and curing the film, or may be formed by a method of applying and curing a liquid material.

Referring to FIG. 12D, the second adhesive film 212 may be removed. The method of removing the second adhesive film 212 may also be a mechanical method. Subsequently, the connection member 140 may be formed on a lower region from which the second adhesive film 212 has been removed. The connection member 140 may be formed by forming the insulating layer 141 by a known lamination or application method, and forming the via hole 143 by a lithography method or by a laser drilling process and / or a mechanical drilling process. Holes, and formed by known plating methods such as plating methods, electroless plating methods, etc. Redistribution layer 142 and via 143. Subsequently, the passivation layer 150 may be formed by a known lamination or application method, the under bump metal layer 160 may be formed by a known metallization method, and the electrical connection structure 170 may be formed by a known method.

When the panel 500 or the like in FIG. 11 is used, a plurality of fan-out semiconductor package modules 100A can be manufactured in a single process including a series of sub-processes. Then, the fan-out semiconductor package module 100A can be sliced into individual fan-out semiconductor package modules 100A by a slicing process or the like.

13 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package module.

Referring to FIG. 13, according to another example, in the fan-out type semiconductor package module 100B, the second encapsulation body 132 may not cover the first encapsulation body 131. Such a structure can be realized by forming the second encapsulation body 132 in the same manner as UF jetting. The upper surfaces of the first encapsulation body 131 and the second encapsulation body 132 may be substantially coplanar with each other. For example, the upper surfaces of the first encapsulation body 131 and the second encapsulation body 132 may be disposed at the same horizontal height. Conceptually, the same level may include slight differences in its level. For example, the same horizontal height means that the horizontal height of the first encapsulation body 131 and the horizontal height of the second encapsulation body 132 may be substantially the same. In this case, the thickness of the fan-out semiconductor package module 100B can be significantly reduced. Descriptions of elements or manufacturing methods that overlap with those previously provided will be omitted.

FIG. 14 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package module.

Referring to FIG. 14, according to another example, a fan-out type semiconductor package module In 100C, the first passive component 125A and the second passive component 125B, each having a relatively reduced thickness, may be respectively disposed in the second through-hole 110HB and the third through-hole 110HC of the semiconductor wafer 120, and have a relatively increased thickness. The sixth passive component 125F may be disposed in the first through hole 110HA in which the semiconductor wafer 120 is disposed. Since the first encapsulation body 131 itself encapsulating the first passive component 125A and the second passive component 125B each having a relatively reduced thickness may have a reduced thickness, the thickness of the fan-out semiconductor package module 100C may be reduced, and The problem caused by the thickness change can be solved more effectively. Specifically, when the sixth passive component 125F needs to be close to the semiconductor wafer 120 (such as a power inductor (PI) and the like), the length of the electrical path therebetween can be further significantly reduced, and thus the fan-out semiconductor The package module 100C may have various advantages. Although not shown in the cross-sectional view of FIG. 14, other through holes may be further formed, such as fourth to sixth through holes 110HD to 110HF, and passive components such as the third passive component 125C to the first through each having a relatively reduced thickness. Five passive components 125E) can be configured therein. Descriptions of elements or manufacturing methods that overlap with those previously provided will be omitted.

15 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package module.

Referring to FIG. 15, in addition to the fan-out type semiconductor package module 100A according to one example, according to another example, the fan-out type semiconductor package module 100D may further include a metal layer 181 and a back metal layer 182 for EMI shielding and heat dissipation. , And the back through hole 183. The metal layer 181 may be formed on a wall surface of each of the second through-hole 110HB and the third through-hole 110HC to have a plate shape, and thus surrounds the first passive hole. Component 125A and a second passive component 125B. The metal layer 181 having a plate shape may extend to the upper and lower surfaces of the core member 110. The back metal layer 182 may be formed on the second encapsulation body 132 to have a plate shape, and thus shields an upper portion of the fan-out type semiconductor package module 100D. The metal layer 181 and the back metal layer 182 can significantly increase the EMI shielding and heat dissipation effect. The back surface through-hole 183 may connect the metal layer 181 and the back metal layer 182 through at least part of the first encapsulation body 131 and at least part of the second encapsulation body 132. Each of the metal layer 181, the back metal layer 182, and the back via 183 may include a conductive material such as copper (Cu), and may be formed by a known plating method or the like. The metal layer 181 and the back metal layer 182 may be connected to a ground pattern included in the redistribution layer 142 of the connection member 140 for grounding.

The connection member 140 may include a shield structure 190 surrounding the redistribution layer 142. The redistribution layer 142 can shield the EMI by the shielding structure 190. The shielding structure 190 may be formed on the outer edge of the connection member 140, and in addition to the stacked through holes shown in FIG. 15, wire through holes, copper blocks, etc. may also be used. The shielding structure 190 may also be connected to the metal layer 181.

Deaeration holes for deaeration or deaeration may be formed in the back metal layer 182. For this purpose, the back metal layer 182 may also have a mesh shape.

The wall surface of the first through hole 110HA having the semiconductor wafer 120 disposed therein may not be coated with a metal layer. For example, the wall surface of the first through hole 110HA may be in physical contact with the second encapsulation body 132. The physical contact between the wall surface of the first through hole 110HA and the second encapsulation body 132 can be achieved by: firstly forming the second through hole 110HB and the third through hole 110HC, and forming a metal layer 181 by electroplating, The first passive component 125A and the second passive component 125B are arranged in the second through hole 110HB and the third through hole 110HC, respectively. When no defect is detected, the first through hole 110HA is formed, and the semiconductor wafer 120 is arranged therein. . Alternatively, the physical contact between the wall surface of the first through hole 110HA and the second encapsulation body 132 can be achieved by forming the first through hole 110HA, the second through hole 110HB, and the third through hole 110HC, While filling the first through hole 110HA with a dry film or the like, the metal layer 181 is formed by electroplating, and the first passive component 125A and the second passive component 125B are respectively arranged in the second through hole 110HB and the third through hole 110HC. When a defect is detected, the first through hole 110HA is opened, and the semiconductor wafer 120 is arranged therein. In addition, various methods can be used. The surface mounting of the first passive component 125A and the second passive component 125B may be relatively easy. However, since the surface mounting of the semiconductor wafer 120 may require high accuracy and a clean environment, the surface mounting of the semiconductor wafer 120 may be relatively difficult. Therefore, when the process of installing and encapsulating the first passive component 125A and the second passive element 125B and the process of installing and encapsulating the semiconductor wafer 120 are performed separately, the impact on the installation yield and the foreign material effect in the two processes Etc. can be significantly reduced. Specifically, after the first passive component 125A to the second passive component 125B are installed, the relatively expensive semiconductor wafer 120 can be mounted only on a single good-quality unit by a precision process, and thus has a high yield.

Although not shown in the cross-sectional view of FIG. 15, other through holes may be further formed, such as the fourth through hole 110HD to the sixth through hole 110HF, and the metal layer 181 may be disposed in the fourth through hole 110HD to the sixth through hole 110HF. On each of the wall surfaces, and the metal layer 181 may be connected to the back metal layer through the back through-hole 183 182. In addition, the metal layer 181 and the back metal layer 182 may be connected to a ground pattern included in the redistribution layer 142 or the shielding structure 190 of the connection member 140. Therefore, the third passive component 125C to the fifth passive component 125E disposed in the fourth through hole 110HD to the sixth through hole 110HF may be surrounded by the metal layer 181 to provide an EMI shielding and heat dissipation effect. Descriptions of elements or manufacturing methods that overlap with those previously provided will be omitted.

FIG. 16 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package module.

16, in addition to the fan-out type semiconductor package module 100B according to another example described above, according to another example, the fan-out type semiconductor package module 100E may further include a metal layer 181 and a back metal layer for EMI shielding and heat dissipation. 182 和 背 孔 孔 183. The rear through hole 183 may not pass through the second encapsulation body 132 and may pass through at least a part of the first encapsulation body 131. Descriptions of elements or manufacturing methods that overlap with those previously provided will be omitted.

FIG. 17 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package module.

Referring to FIG. 17, in addition to the above-mentioned fan-out semiconductor package module 100C according to another example, according to another example, the fan-out semiconductor package module 100F may further include a metal layer 181 and a back metal layer for EMI shielding and heat dissipation. 182 和 背 孔 孔 183. Descriptions of elements or manufacturing methods that overlap with those previously provided will be omitted.

18 is a cross-sectional view illustrating another example of a fan-out type semiconductor package module intention.

Referring to FIG. 18, in addition to the fan-out semiconductor package module 100A according to one example described above, according to another example, the fan-out semiconductor package module 100G may include a first insulating layer 111a, in which the core member 110 may contact the connection member 140; The first wiring layer 112a contacts the connection member 140 and is embedded in the first insulating layer 111a; the second wiring layer 112b is opposite to the first wiring layer 112a of the first insulating layer 111a; the second insulating layer 111b is disposed on the first insulation The second wiring layer 112b is covered on the layer 111a; and the third wiring layer 112c is arranged on the second wiring layer 112b. The first to third wiring layers 112 a to 112 c may be electrically connected to the connection pad 122. The first wiring layer 112a and the second wiring layer 112b may be electrically connected to each other through the first through hole 113a passing through the first insulating layer 111a, and the second wiring layer 112b and the third wiring layer 112c may pass through the first The second through holes 113b of the two insulating layers 111b are electrically connected to each other.

When the first wiring layer 112a is embedded in the first insulating layer 111a, the stepped portion caused by the thickness of the first wiring layer 112a may be significantly reduced, and thus the insulation distance of the connection member 140 may become fixed. For example, the difference between the distance from the redistribution layer 142 of the connection member 140 to the lower surface of the first insulating layer 111a and the distance from the redistribution layer 142 of the connection member 140 to the connection pad 122 of the semiconductor wafer 120 may be less than The thickness of a wiring layer 112a. Therefore, a high-density wiring design of the connection member 140 can be facilitated.

The lower surface of the first wiring layer 112 a of the core member 110 may be located above the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, the distance between the redistribution layer 142 of the connection member 140 and the first wiring layer 112a of the core member 110 may be The distance between the redistribution layer 142 of the connection member 140 and the connection pad 122 of the semiconductor wafer 120 is larger. This is because the first wiring layer 112a may be recessed toward the inside of the first insulating layer 111a. As described above, when the first wiring layer 112a is recessed toward the inside of the first insulating layer 111a, so that the lower surface of the first insulating layer 111a and the lower surface of the first wiring layer 112a are stepped to each other, the first wiring layer 112a can be prevented The first encapsulation body 131 is contaminated due to seepage of the material. The second wiring layer 112 b of the core member 110 may be located between the active surface and the non-active surface of the semiconductor wafer 120. The core member 110 may have a thickness corresponding to the thickness of the semiconductor wafer 120, and thus the second wiring layer 112 b formed inside the core member 110 may be disposed at a horizontal height between the active surface and the non-active surface of the semiconductor wafer 120.

The thicknesses of the first to third wiring layers 112 a to 112 c of the core member 110 may be greater than the thickness of the redistribution layer 142 of the connection member 140. Because the core member 110 may have a thickness equal to or greater than the thickness of the semiconductor wafer 120, the first to third wiring layers 112a to 112c may have a relatively large size depending on the specifications of the core member 110. In contrast, the redistribution layer 142 of the connection member 140 may have a size smaller than that of the first to third wiring layers 112a to 112c so as to be thinned.

The material of each of the first insulating layer 111a and the second insulating layer 111b is not particularly limited. For example, an insulating material may be used. The insulating material may be a thermosetting resin such as epoxy resin; a thermoplastic resin such as polyimide; or a resin such as a prepreg, Ajinomoto constituting film, FR-4 or bismaleimide triazine, in which the core is (Such as inorganic filler, glass fiber, glass cloth or glass fabric) impregnated with thermosetting resin and thermoplastic resin. PID resins can also be used.

The first to third wiring layers 112 a to 112 c may be used for rewiring the connection pads 122 of the semiconductor wafer 120. A material of each of the first to third wiring layers 112a to 112c may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or any alloy thereof. The first to third wiring layers 112a to 112c may perform various functions depending on their design. For example, each of the first to third wiring layers 112a to 112c may include a ground pattern, a power pattern, a signal pattern, and the like. Here, the signal pattern may include various signals other than a ground pattern, a power pattern, and the like, such as a data signal. In addition, the first to third wiring layers 112a to 112c may include through-hole pads, wiring pads, electrical connection structure pads, and the like.

The first through-hole 113 a and the second through-hole 113 b can electrically connect the first wiring layer 112 a to the third wiring layer 112 c formed on different layers, resulting in the formation of the electrical path of the core member 110. The material of each of the first through hole 113a and the second through hole 113b may also be a conductive material. Each of the first through hole 113a and the second through hole 113b may be completely filled with a conductive material or the conductive material may be formed along a wall surface of the first through hole 113a or the second through hole 113b. In addition, the first through hole 113a and the second through hole 113b may have all shapes known in the related art, such as a tapered shape, a cylindrical shape, and the like. When the hole of the first through hole 113a is formed, the pad disposed on part of the first wiring layer 112a can be used as a stopper. Therefore, in terms of the manufacturing process, the width of the upper surface of the first through hole 113a is greater than The tapered width of its lower surface may be advantageous. In this case, the first through hole 113a may be formed integrally with the pad pattern of the second wiring layer 112b. When a hole of the second through hole 113b is formed, it is arranged on a part of the second wiring layer 112b The upper pad may serve as a termination element, and therefore it may be advantageous for the manufacturing process that the second through hole 113b has a tapered shape whose width is greater than the width of the lower surface thereof. In this case, the second through hole 113b may be formed integrally with the pad pattern of the third wiring layer 112c.

According to another example, the core component 110 of the fan-out type semiconductor package module 100G can even be used in the fan-out type semiconductor package module 100B, 100C, 100D, 100E, or 100F according to another example. The description of the configuration overlapping with the previously described configuration will be omitted.

19 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package module.

Referring to FIG. 19, according to another example, in a fan-out semiconductor package 100H, the core member 110 may include a first insulating layer 111a; a first wiring layer 112a and a second wiring layer 112b, which are disposed opposite to the first insulating layer 111a. On the surface; a second insulating layer 111b is disposed on the first insulating layer 111a to cover the first wiring layer 112a; a third wiring layer 112c is disposed on the second insulating layer 111b; a third insulating layer 111c is disposed on the first The second wiring layer 112b is covered on the insulating layer 111a; and the fourth wiring layer 112d is disposed on the third insulating layer 111c. The first to fourth wiring layers 112 a to 112 d may be electrically connected to the connection pad 122. The core member 110 may include a larger number of the first to fourth wiring layers 112a to 112d, and thus the connection member 140 may be further simplified. Therefore, it is possible to reduce a decrease in the yield due to a defect generated in the process of forming the connection member 140. The first to fourth wiring layers 112a to 112d may pass through the first through holes 113a of the first to third insulating layers 111a to 111c, respectively. The third through holes 113c are electrically connected to each other.

The thickness of the first insulating layer 111a may be greater than the thickness of the second insulating layer 111b and the thickness of the third insulating layer 111c. Basically, the thickness of the first insulating layer 111a can be relatively increased to maintain its rigidity, and the second insulating layer 111b and the third insulating layer 111c can be used to form a larger number of the third wiring layer 112c and the fourth wiring layer 112d. The first insulating layer 111a may include an insulating material different from that of the second insulating layer 111b and the third insulating layer 111c. For example, the first insulating layer 111a may be, for example, a prepreg including a core, a filler, and an insulating resin, and each of the second insulating layer 111b and the third insulating layer 111c may be an ABF or PID including a filler and an insulating resin. However, the material of each of the first to third insulating layers 111a to 111c is not limited thereto. Similarly, the diameter of the first through hole 113a passing through the first insulating layer 111a may be larger than the diameters of the second through hole 113b and the third through hole 113c passing through the second insulating layer 111b and the third insulating layer 111c, respectively.

The lower surface of the third wiring layer 112 c of the core member 110 may be located below the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, a distance between the redistribution layer 142 of the connection member 140 and the third wiring layer 112 c of the core member 110 may be smaller than a distance between the redistribution layer 142 of the connection member 140 and the connection pad 122 of the semiconductor wafer 120. This is because the third wiring layer 112 c may be disposed on the second insulating layer 111 b to protrude and a passivation layer having a reduced thickness may be further formed on the connection pad 122 of the semiconductor wafer 120. The first wiring layer 112 a and the second wiring layer 112 b of the core member 110 may be disposed between the active and non-active surfaces of the semiconductor wafer 120. The core member 110 may have a thickness corresponding to the thickness of the semiconductor wafer 120, and thus a shape The first wiring layer 112 a and the second wiring layer 112 b formed inside the core member 110 may be disposed at a level between the active and non-active surfaces of the semiconductor wafer 120.

The thickness of the first to fourth wiring layers 112 a to 112 d of the core member 110 may be greater than the thickness of the redistribution layer 142 of the connection member 140. Because the core member 110 may have a thickness equal to or greater than that of the semiconductor wafer 120, the first wiring layer 112 a to the fourth wiring layer 112 d may also have a relatively large size. In contrast, the redistribution layer 142 of the connection member 140 may have a relatively reduced size so as to be thinned.

According to another example, the core component 110 of the above-mentioned fan-out type semiconductor package module 100H may be used even in the fan-out type semiconductor package module 100B, 100C, 100D, 100E, or 100F according to another example. The description of the configuration overlapping with the previously described configuration will be omitted.

20 is a schematic plan view illustrating an effect obtained by using a fan-out type semiconductor package module according to an exemplary embodiment in an electronic device.

Referring to FIG. 20, as the size of the display for the mobile device 1100A or the mobile device 1100B increases, the demand for increasing the battery capacity also increases. Because the area of the battery 1180 in the mobile device 1100A or 1100B increases according to the increase in the battery capacity, the size of the motherboard 1101 needs to be reduced. Therefore, the mounting area for the components can be reduced, and thus the area of the module 1150 (including the PMIC and the final passive component) can be continuously reduced. When the fan-out type semiconductor package module 100A, 100B, 100C, 100D, 100E, 100F, 100G, or 100H according to an exemplary embodiment is used for an electronic device, the size of the module 1150 may be significantly reduced. Therefore, an area other than the module 1150 can be effectively used.

FIG. 21 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package module.

Referring to FIG. 21, according to another example, in the fan-out type semiconductor package module 100I, the first passive component 125A and the second passive component 125B each having a relatively reduced thickness may be disposed in the second through-hole 110HB and the third The through-hole 110HC and the sixth passive component 125F having a relatively increased thickness may be disposed in the seventh through-hole 110HG. Moreover, the second encapsulation body 132 encapsulates at least a portion of the sixth passive component 125F. Since the first encapsulation body 131 itself encapsulating the first passive component 125A and the second passive component 125B each having a relatively reduced thickness may have a reduced thickness, the thickness of the fan-out semiconductor package module 100I may be reduced, and The problem caused by the thickness change can be solved more effectively. Although not shown in the cross-sectional view of FIG. 21, other through holes such as fourth to sixth through holes 110HD to 110HF, and passive components such as third passive components 125C to A fifth passive component 125E) may be disposed therein. Descriptions of elements or manufacturing methods that overlap with those previously provided will be omitted.

As explained above, according to the exemplary embodiment, a fan-out type semiconductor package module having a novel structure can be provided, which can significantly reduce the mounting area of a semiconductor wafer and a plurality of passive components, and can significantly reduce the semiconductor wafer and the passive components. The length of the electrical path between them can still solve the production yield problem, and electroplating can be used to obtain improved electromagnetic interference (EMI) shielding and heat dissipation effects.

Although the exemplary embodiments have been shown and described as above, it is obvious for those having ordinary knowledge in the technical field to do so without departing from the scope of the attached patent application. Modifications and changes are defined within the scope of this disclosure.

Claims (26)

A fan-out type semiconductor package module includes: a core member having first and second through holes spaced apart from each other; a semiconductor wafer disposed in the first through hole, the semiconductor wafer having an active surface and A non-active surface opposite to the active surface, the active surface having a connection pad disposed thereon; at least one first passive component disposed in the second through hole; a first encapsulation body encapsulating the A core member and at least a part of each of the at least one first passive component, the first encapsulating body fills at least a part of the second through hole; a second encapsulating body encapsulating the semiconductor wafer At least a part of the non-active surface, the second encapsulating body filling at least a part of the first through hole; and a connecting member disposed on the core member, the active surface of the semiconductor wafer, and On the at least one first passive component, the connection member includes a redistribution layer electrically connected to the connection pad and the at least one first passive component, wherein the second encapsulation body covers the first package. Enclosed table . The fan-out semiconductor package module according to item 1 of the scope of patent application, further comprising: a metal layer disposed on a wall surface of the second through hole. The fan-out type semiconductor package module according to item 2 of the patent application scope, wherein a wall surface of the first through hole is in physical contact with the second encapsulation body. The fan-out type semiconductor package module according to item 2 of the scope of patent application, wherein the metal layer is connected to a ground included in the redistribution layer of the connection member. The fan-out type semiconductor package module according to item 2 of the patent application scope, wherein the metal layer extends to an upper surface and a lower surface of the core member. The fan-out type semiconductor package module according to item 5 of the patent application scope, further comprising: a back metal layer disposed on the first encapsulation body or the second encapsulation body; Through at least a part of the first encapsulation body or the second encapsulation body, the back surface through hole connects the metal layer to the back metal layer. The fan-out type semiconductor package module according to item 5 of the patent application scope, wherein the connection member includes a shielding structure surrounding the redistribution layer. The fan-out type semiconductor package module according to item 7 of the patent application scope, wherein the shielding structure is connected to the metal layer. The fan-out type semiconductor package module according to item 1 of the patent application scope, wherein the semiconductor wafer and the at least one first passive component are arranged parallel to each other, and are electrically connected to each other through the redistribution layer of the connection member. Sexual connection. The fan-out type semiconductor package module according to item 9 of the patent application scope, wherein the connection member further includes a through hole that connects the connection pad and the at least one first passive component to the connection member. Each of the redistribution layer, the connection pad, and the at least one first passive component is in physical contact with the through hole of the connection member. The fan-out semiconductor package module according to item 1 of the patent application scope, wherein the semiconductor chip includes a power management integrated circuit (PMIC), and the at least one first passive component includes a capacitor. The fan-out type semiconductor package module according to item 1 of the patent application scope, wherein the core component further includes: a third through hole spaced from the first and second through holes; at least one A second passive component is disposed in the third through-hole, the first encapsulating body encapsulates at least a portion of the at least one second passive component, and fills at least a portion of the third through-hole, and the The redistribution layer of the connection member is electrically connected to the at least one second passive component. The fan-out type semiconductor package module according to item 1 of the patent application scope, further comprising: at least one third passive component disposed in the first through hole, wherein the second encapsulation body encapsulates the At least a portion of at least one third passive component, the redistribution layer of the connection member is electrically connected to the at least one third passive component, and a thickness of the at least one third passive component is greater than the at least one first passive component. The thickness of a passive component. The fan-out type semiconductor package module according to item 1 of the patent application scope, wherein the core component includes: a wiring layer, and is electrically connected to the connection pad and the connection layer through the rewiring layer of the connection component. At least one first passive component. The fan-out type semiconductor package module according to item 14 of the patent application scope, wherein the core member includes: a first insulating layer that contacts the connection member; a first wiring layer that contacts the connection member and is embedded in the A first insulating layer; and a second wiring layer disposed on a second surface of the first insulating layer opposite to a first surface of the first insulating layer in which the first wiring layer is embedded, wherein The first wiring layer and the second wiring layer are electrically connected to the connection pad. The fan-out type semiconductor package module according to item 15 of the patent application scope, wherein the core component further includes: a second insulating layer disposed on the first insulating layer to cover the second wiring layer; and A third wiring layer is disposed on the second insulating layer, and the third wiring layer is electrically connected to the connection pad. The fan-out type semiconductor package module according to item 1 of the patent application scope, wherein the core component includes a first insulating layer, a first wiring layer and a second wiring layer disposed on opposite surfaces of the first insulating layer. The wiring layer, the first wiring layer and the second wiring layer are electrically connected to the connection pad. The fan-out type semiconductor package module according to item 17 of the patent application scope, wherein the core component further includes: a second insulating layer disposed on the first insulating layer to cover the first wiring layer; Three wiring layers are disposed on the second insulation layer; a third insulation layer is disposed on the first insulation layer to cover the second wiring layer; and a fourth wiring layer is disposed on the third insulation layer On the layer, the third wiring layer and the fourth wiring layer are electrically connected to the connection pad. The fan-out type semiconductor package module according to item 1 of the scope of patent application, wherein the first encapsulation body and the second encapsulation body have an interface therebetween. According to the fan-out type semiconductor package module according to item 1 of the patent application scope, wherein the first encapsulation body and the second encapsulation body are made of different materials. A semiconductor packaging module includes: a core member having a second through-hole; a first passive component disposed in the second through-hole; a first encapsulating body that encapsulates the core member and the first passive At least a part of each of the components, the first encapsulation body fills at least a part of the second through hole; a first through hole penetrating the core member and the first encapsulation body; a semiconductor wafer, Disposed in the first through hole, the semiconductor wafer has an active surface and a non-active surface opposite to the active surface, and the active surface has a connection pad disposed thereon; a second encapsulation body, which encapsulates the At least a portion of the non-active surface of the semiconductor wafer, the second encapsulation body filling at least a portion of the first through-hole; and a connecting member disposed on the core member and the active portion of the semiconductor wafer And the first passive component, the connection member includes a redistribution layer electrically connected to the connection pad and the first passive component, wherein the second encapsulation body covers the first encapsulation body. The semiconductor package module according to item 21 of the scope of patent application, further comprising a metal layer disposed on a wall surface of the second through hole. The semiconductor package module according to item 21 of the scope of patent application, further comprising: a metal layer disposed on the core member and extending to a wall surface of the second through hole; a back metal layer disposed on the first through hole; An encapsulation body or the second encapsulation body; and a back surface through hole passing through at least a part of the first encapsulation body or the second encapsulation body, the back surface through hole connects the metal layer Connected to the back metal layer. The semiconductor package module according to claim 21, wherein the connection member includes a shielding structure surrounding the redistribution layer. The semiconductor package module according to item 21 of the scope of patent application, further comprising: a second passive component disposed in the first through hole, wherein an upper surface of the second passive component is opposite to the connection member. Above the upper surface of the first passive component. The semiconductor package module according to item 21 of the scope of application for a patent, wherein the core component includes: one or more wiring layers, and is electrically connected to the connection pad and the wiring layer through the redistribution layer of the connection component. The first passive component is described.