TWI793618B - Electronic package and manufacturing method thereof - Google Patents

Abstract

An electronic package includes at least a sub-package. The sub-package includes a plurality of chips, a metal layer, at least one bridge, and an intermediate via structure. Each of the chips has an active surface, a back surface, and side surfaces connecting the active surface and the back surface. The metal layer directly covers the back surface and the side surfaces of each of the chips, and exposes these active surfaces. The bridge partially overlaps with at least two of these chips, and is electrically connected to the corresponding active surfaces. The intermediate conductive structure is arranged on the metal layer and the chips and covers the bridge, and is electrically connected to the active surfaces. In addition, a manufacturing method of an electronic package is also provided here.

Description

Electronic package and manufacturing method thereof

The present invention relates to an electronic component, and in particular to an electronic packaging body and a manufacturing method thereof.

There are many types of electronic packaging technologies currently used for multi-chip, one of which is to make a redistribution circuit structure on a multi-chip, and in the process of making a redistribution circuit structure, a chip can be bridged across multiple adjacent Signal transmission between these adjacent chips on the chip. Another type is to stack multiple chips on a circuit carrier or an interposer, and provide a vertical conduction path through a through-silicon via (TSV) in the chip. However, the more chips are configured in the same package, the most common problem is heat dissipation, which needs to be solved at present.

The invention provides an electronic packaging body for providing good heat dissipation performance.

The invention provides a manufacturing method of an electronic packaging body, which is used for manufacturing the electronic packaging body.

The electronic package of the present invention comprises at least one primary package. The subpackage includes a plurality of chips, a metal layer, at least one bridge element, and an intermediate conducting structure. Each of these chips has an active surface, a back surface and a plurality of sides connecting the active surface and the back surface. A metal layer directly covers the backside and the sides of each of the wafers and exposes the active faces. The bridge element overlaps with at least two parts of the wafers and electrically connects the corresponding active surfaces. The intermediary conduction structure is disposed on the metal layer and the chips, covers the bridge elements, and electrically connects the active surfaces.

The manufacturing method of the electronic package of the present invention includes the following steps. Multiple wafers are provided. A masking layer is formed on the active face of each of the wafers. The wafers are secured to temporary carriers via a temporary bonding layer. A metal layer is formed over the back and sides of each of the wafers, the perimeter of the masking layer, and the temporary bonding layer, wherein the metal layer conforms to the back and sides of each of the wafers. Remove the temporary carrier and the temporary bonding layer. A portion of the metal layer is removed to expose the periphery of each of the masking layers, and the surface of the metal layer is flush with the active surface of each of the wafers. A bridge element is installed on the adjacent ones of the chips, so that the bridge element partially overlaps with the adjacent chips respectively, wherein the plurality of first bridge pads of the bridge element respectively directly bond the chip pads. An intervening conductive structure is formed on the wafers, metal layers and bridge elements.

Based on the above, the metal layer directly covers the back surface and multiple sides of the chip, so that the metal layer conforms to the back surface and multiple sides of the chip to form a directly contact interface (interface), which helps to reduce heat dissipation. Resistance and increase the heat conduction path from the chip to the outside world to provide good heat dissipation performance. The types of chips packaged are, for example, CPU chips, logic chips, graphics processing chips, input and output chips, memory chips, base band (base band) chips, radio frequency (RF) chips, special function integrated circuit chips, etc. It can be used in small chip (Chiplet) packaging technology, which is similar to System in a Packaging (SiP). Connecting adjacent chips through bridges can increase the circuit density of electronic packages.

Please refer to FIG. 1A to FIG. 1D , in the present embodiment, the electronic package 10 includes at least one package 100 . The subpackage 100 includes a plurality of chips 110 , a metal layer 120 , a bridge element 130 (bridge) and a via structure 140 . Each chip 110 has an active surface 110a, a back surface 110b and a plurality of side surfaces 110c connecting the active surface 110a and the back surface 110b. The metal layer 120 directly covers the back surface 110b and the side surfaces 110c of each chip 110, and exposes the active surfaces 110a. In other words, the metal layer 120 is conformal with the back surface 110 b and the side surfaces 110 c of each chip 110 , that is, has an interface that can directly contact. The presently shown FIG. 1A is a schematic diagram, and the conformal metal layer 120 is planarized or thinned. It is worth mentioning that the metal layer 120 in this embodiment can serve as a heat dissipation path, and in this embodiment, there is no heat dissipation material (TIM) disposed between the metal layer 120 and the chip 110 . In addition, compared with the use of the known pasty heat dissipation material, the use of the metal layer in this embodiment does not have the problem that air bubbles may be generated when the paste heat dissipation material is coated, thereby affecting the heat dissipation efficiency. In addition, the thickness of the metal layer 120 serving as a heat dissipation path may be greater than that of the chip 110 to provide better heat dissipation efficiency. In detail, since there is sufficient structural support under the conformal metal layer 120 , the thickness of the metal layer can be relatively thick. However, known metal heat dissipation covers or heat sinks for heat dissipation only partially contact the underlying structure, so the available support is relatively small, and the choice of metal heat dissipation covers or heat sinks is limited, so the thickness is relatively thin.

The bridge element 130 partially overlaps the chips 110 and is electrically connected to the corresponding active surfaces 110a. In one embodiment, the bridge element 130 is composed of multiple dielectric layers and multiple conductive layers without MOS transistor configuration. That is, the bridge element 130 is only used for signal transmission, without the switching effect of the MOS transistor. The intermediate via structure 140 is disposed on the metal layer 120 and the wafers 110 , covers the bridge element 130 , and is electrically connected to the active surfaces 110 a.

In this embodiment, each chip 110 has a chip pad 112 , and the bridge element 130 has a plurality of first bridge pads 132 . The first bridging pads 132 can directly bond to the die pads 112 respectively. In another non-illustrated embodiment, the first bridging pads 132 can also be respectively connected to the chip pads 112 via solder.

In this embodiment, one of these chips 110 may be a CPU chip, a logic chip, a graphics processing chip, an I/O chip, a memory chip, a base band chip, a radio frequency (RF) chip, or a specific function chip. Integrated circuit chip 110 . In other words, these chips 110 may include a combination of the aforementioned chips 110 of different functional types, so that the electronic package 10 may be used in a chiplet packaging technology, which is similar to System in a Packaging (SiP). Since the wafers 110 may have different functions, the dimensions of the wafers 110 may be different, as shown in FIG. 1B . In some embodiments, for example: a combination of a CPU chip and a logic chip, a combination of a CPU chip and an I/O chip, a combination of a graphics processing chip and a memory chip, a combination of a radio frequency chip and a baseband chip.

In this embodiment, the material of the metal layer 120 is, for example, copper, silver, gold, or aluminum to provide good thermal conductivity. In terms of thermal conductivity, the thermal conductivity of the selected metal layer 120 may be greater than 300 W/mK (watts/(meter x degree)). In some embodiments, copper has a thermal conductivity of about 398 W/mK, silver has a thermal conductivity of about 429 W/mK, and gold has a thermal conductivity of about 315 W/mK.

In this embodiment, the material of the dielectric layer of the bridge element 130 may be the same as or similar to the base material of the chips 110 . The bridge element 130 may have a plurality of bridge vias 136 (FIG. 1A only shows one of these bridge vias 136 for illustration), and the chips 110 electrically connected to the bridge element 130 are connected to the intermediate through the bridge vias 136. The structure 140 is electrically connected. In one embodiment, the bridge element 130 is only used for signal transmission without MOS transistor configuration.

In this embodiment, the intermediate via structure 140 has an intermediate dielectric layer 142 and a plurality of intermediate vias 144 . The intermediate vias 144 pass through the intermediate dielectric layer 142 and respectively connect the chip pads 112 of the chips 110 and the plurality of second bridge pads 134 of the bridge element 130 .

In this embodiment, the subpackage 100 may further include a plurality of conductive bumps 150 . Each conductive bump 150 is disposed at the end of the corresponding central via 144 .

It is worth mentioning that because the chip 110 of this embodiment has at least five heat dissipation paths, that is, the heat of the chip 110 can be directly transferred to the metal layer 120 through the back surface 110b (upper surface) and the four side surfaces 110c of the chip 110. Compared with the known heat dissipation material (TIM) to dissipate heat, only a single heat dissipation on the upper surface, this embodiment can greatly improve the heat dissipation effect. In addition, the active surface 110 a of the chip 110 may also be another heat dissipation path. Please refer to FIG. 2 . Compared with the embodiment in FIG. 1A , in this embodiment, the electronic package 10 further includes a circuit carrier 12 , and the subpackage 100 is installed on the circuit carrier 12 . In addition, the electronic package 10 may further include a plurality of conductive balls 14 , such as solder balls, which are connected to the circuit carrier 12 for connecting next-level electronic components.

Please refer to FIG. 3 . Compared with the embodiment in FIG. 2 , in this embodiment, there are more sub-packages 100 , and these sub-packages 100 are mounted on the same surface of the circuit carrier 12 .

Please refer to FIG. 4 . Compared with the embodiment in FIG. 2 , in this embodiment, there are more sub-packages 100 , and these sub-packages 100 are mounted on opposite sides of the circuit carrier 12 respectively.

Please refer to FIG. 5. Compared with the embodiment in FIG. and the plurality of second bridge pads 134 of the bridge element 130 are rearranged. In this embodiment, the bridge element 130 may have a plurality of bridge vias 136 , and the chips 110 are electrically connected to the redistribution wiring structure 160 through the bridge vias 136 . Compared with FIG. 1 to FIG. 4 , FIG. 5 has a redistribution circuit structure 160 . The signals of the chip pads 112 on these chips 110 can be routed to both sides of the chip 110 through the redistribution circuit structure 160 to increase the flexibility of the signal layout. For a reference projection plane, the projection of the wafer 110 falls inside the projection of the redistribution wiring structure 160 .

Please refer to FIG. 6 . Compared with the embodiment in FIG. 5 , in this embodiment, the electronic package 10 further includes a circuit carrier 12 , and the subpackage 100 is installed on the circuit carrier 12 . In addition, the electronic package 10 may further include a plurality of conductive balls 14 , such as solder balls, which are connected to the circuit carrier 12 for connecting to next-level electronic components (such as PCB).

The manufacturing process of an electronic package 10 according to an embodiment of the present invention will be described below with reference to FIGS. 7A to 7N , which can produce an electronic package 10 like the embodiment of FIG. 1A .

Referring to FIG. 7A , a plurality of wafers 110 are provided.

Referring to FIG. 7B , a shielding layer 202 is formed on the active surface 110 a of each chip 110 .

Referring to FIG. 7C , the wafers 110 are fixed to the temporary carrier 206 through a temporary bonding layer 204 or release layer (not shown).

Referring to FIG. 7D , an electroplating seed layer 208 is comprehensively formed on the wafers 110 , the shielding layers 202 and the temporary bonding layer 204 . In one embodiment, the conformal plating seed layer 208 can be formed by sputtering.

Please refer to FIG. 7E, a metal material layer 120a is electroplated on the electroplating seed layer 208, to cover the back side 110b of each wafer 110 under the electroplating seed layer 208 and these side surfaces 110c, the periphery of each shielding layer 202 and the temporary bonding layer 204, so that The metal material layer 120 a is conformal to the back surface 110 b and the side surfaces 110 c of each wafer 110 .

Referring to FIG. 7F , after the metal material layer 120 a is formed, the metal material layer 120 a can be planarized and thinned at the same time to form a metal layer 120 . The planarization method is, for example, general polishing or chemical-mechanical polishing (CMP). In one embodiment, the thermal conductivity of the material used to form the metal layer 120 may be greater than 300 W/mK (watts/(meter x degree)), such as copper, silver, gold, aluminum. In some embodiments, copper has a thermal conductivity of about 398 W/mK, silver has a thermal conductivity of about 429 W/mK, and gold has a thermal conductivity of about 315 W/mK. In addition, the electroplating seed layer 208 will constitute a part of the metal layer 120 , so in other embodiments, the electroplating seed layer 208 will be omitted from illustration. In this embodiment, the metal layer 120 can be used as a heat dissipation path, and there is no heat dissipation material (TIM) disposed between the metal layer 120 and the chip 110 . In addition, compared with the use of the known pasty heat dissipation material, the use of the metal layer in this embodiment does not have the problem that air bubbles may be generated when the paste heat dissipation material is coated, thereby affecting the heat dissipation efficiency. In addition, the thickness of the metal layer 120 serving as a heat dissipation path can be greater than that of the chip 110 through the manufacturing method of this embodiment, so as to provide better heat dissipation efficiency. In detail, since there is sufficient structural support under the conformal metal layer 120 , a larger thickness can be formed. However, known metal heat dissipation covers or heat sinks for heat dissipation only partially contact the underlying structure, so the available support is relatively small, and the choice of metal heat dissipation covers or heat sinks is limited, so the thickness is relatively thin.

Referring to FIG. 7G , the temporary carrier 206 and the temporary bonding layer 204 are removed.

Referring to FIG. 7H , part of the metal layer 120 and the electroplating seed layer 208 are removed to expose the periphery of each shielding layer 202 , and make the surface of the metal layer 120 flush with the active surface 110 a of each chip 110 . A method of removing part of the metal layer 120 is, for example, etching. In one embodiment, the surface of the metal layer 120 and the active surface 110 a of each chip 110 are, for example, coplanar.

Referring to FIG. 7I , each masking layer 202 is removed to expose the active surface 110 a of each chip 110 .

Referring to FIG. 7J , a bridge element 130 is mounted on a plurality of adjacent chips 110 such that the bridge element 130 partially overlaps the chips 110 respectively, and the first bridge pads 132 can directly bond the chip pads 112 respectively. In one embodiment, the bridge element 130 is composed of multiple layers of dielectric layers and multiple conductive layers, without MOS transistor configuration. That is, the bridge element 130 is only used for signal transmission, without the switching effect of the MOS transistor.

Referring to FIG. 7K , an intervening dielectric layer 142 is formed entirely on the wafer 110 , the metal layer 120 and the bridge element 130 .

Referring to FIG. 7L , a plurality of through holes 142 a are formed on the intervening dielectric layer 142 to expose the plurality of chip pads 112 of each chip 110 and the plurality of second bridge pads 134 of the bridge element 130 . The intermediate dielectric layer 142 is, for example, a photosensitive dielectric layer, and the through holes 142a are formed on the intermediate dielectric layer 142 by exposure and development.

Referring to FIG. 7M , each through hole 142 a is filled with a conductive material to form an intermediate conductive channel 144 , and these intermediate conductive channels 144 are respectively connected to the chips 110 and the bridge elements 130 . The intervening dielectric layer 142 and the intervening conductive channels 144 form the intervening conductive structure 140 as in the embodiment of FIG. 1A .

Referring to FIG. 7N , a conductive bump 150 is formed at the end of each intermediate conductive hole 144 . So far, the electronic package 10 of the embodiment shown in FIG. 1A is completed.

In another embodiment, the steps of FIG. 8A and FIG. 8B can also be continued from FIG. 7L , which can produce the electronic package 10 like the embodiment of FIG. 5 .

Specifically, after the step in FIG. 7L , please refer to FIG. 8A , a redistribution circuit structure 160 is formed on the intermediary conductive structure 140 by, for example, a build-up process. Next, please refer to FIG. 8B , a plurality of conductive bumps 150 are formed on the redistribution wiring structure 160 . So far, the electronic package 10 of the embodiment shown in FIG. 5 is completed.

In this embodiment, the redistribution circuit structure 160 includes a plurality of redistribution patterned conductive layers 162 , a plurality of redistribution dielectric layers 164 and a plurality of redistribution conductive holes 166 . The redistribution patterned conductive layers 162 are alternately stacked with the redistribution dielectric layers 164 . The redistribution conductive holes 166 are respectively connected to the redistribution patterned conductive layers 162 . In addition, a plurality of under bump metallurgy layers 168 are further formed on the portions of the redistributed patterned conductive layer 162 farthest from the wafers 110 . In addition, a conductive bump 150 is formed on each under bump metallurgy layer 168 .

To sum up, in the above-mentioned embodiments of the present invention, the metal layer directly covers the back surface and multiple side surfaces of the wafer, so that the metal layer conforms to the back surface and multiple side surfaces of the wafer to form a directly contact. Interface (interface), which helps to reduce thermal resistance and increase the heat conduction path from the chip to the outside world, so as to provide good heat dissipation performance. In this embodiment, the chip has at least five heat dissipation paths including the back and the side. It is worth mentioning that, because the chip of this embodiment has at least five heat dissipation paths, compared with the known heat dissipation material (TIM) for heat dissipation, which only has a single heat dissipation on the upper surface, this embodiment can greatly improve the heat dissipation effect.

In addition, the types of chips packaged are, for example, CPU chips, logic chips, graphics processing chips, I/O chips, memory chips, base band chips, radio frequency (RF) chips, special function integrated circuit chips, etc. , so it can be used in small chip (Chiplet) packaging technology, which is similar to System in a Packaging (SiP). In some embodiments, for example: a combination of a CPU chip and a logic chip, a combination of a CPU chip and an I/O chip, a combination of a graphics processing chip and a memory chip, a combination of a radio frequency chip and a baseband chip. Connecting adjacent chips through bridges can increase the circuit density of electronic packages.

10: Electronic package 12: Circuit carrier board 14: conductive ball 100: Subpackage 110: Wafer 110a: active face 110b: back 110c: side 112: chip pad 120: metal layer 120a: metal material layer 130: bridge element 132: First Bridge Pad 134: Second bridge pad 136: Bridge Via 140: Mediated conduction structure 142: intervening dielectric layer 142a: Through hole 144: Meso-mediated channel 150: Conductive bump 160: Rewiring Structure 162: Redistribution patterned conductive layer 164: Redistribute Dielectric Layer 166: Redistribute Conductive Channels 168: Subbump metallization layer 202: masking layer 204: Temporary bonding layer 206: Temporary Vehicle 208: Plating seed layer

FIG. 1A is a schematic cross-sectional view of an electronic package according to an embodiment of the present invention. FIG. 1B is a schematic cross-sectional view of an electronic package along line A-A of another embodiment similar to FIG. 1A . FIG. 1C is a schematic cross-sectional view of the electronic package of FIG. 1A along line B-B. FIG. 1D is a schematic cross-sectional view of the electronic package of FIG. 1A along line C-C. FIG. 2 is a schematic diagram of an electronic package according to another embodiment of the present invention. FIG. 3 is a schematic diagram of an electronic package according to another embodiment of the present invention. FIG. 4 is a schematic diagram of an electronic package according to another embodiment of the present invention. FIG. 5 is a schematic diagram of an electronic package according to another embodiment of the present invention. FIG. 6 is a schematic diagram of an electronic package according to another embodiment of the present invention. 7A to 7N illustrate a manufacturing process of an electronic package according to an embodiment of the present invention. FIG. 8A to FIG. 8B illustrate the post-production process of an electronic package according to an embodiment of the present invention.

10: Electronic package 100: Subpackage 110: Wafer 110a: active face 110b: back 110c: side 112: chip pad 120: metal layer 130: bridge element 132: First Bridge Pad 134: Second bridge pad 136: Bridge Via 140: Mediated conduction structure 142: intervening dielectric layer 144: Meso-mediated channel 150: Conductive bump

Claims (28)

An electronic package comprising: At least one package, including: a plurality of wafers, each of the wafers has an active surface, a back surface and a plurality of sides connecting the active surface and the back surface; a metal layer directly covering the back surface and the side surfaces of each of the chips and exposing the active surfaces; At least one bridge element partially overlaps with at least two of the chips and is electrically connected to the corresponding active surfaces; and An intermediary conduction structure is disposed on the metal layer and the chips, covers the at least one bridge element, and is electrically connected to the active surfaces. The electronic package as claimed in claim 1, wherein the thickness of the metal layer is greater than the thickness of the chip. The electronic package as claimed in claim 1, wherein the bridge element is composed of a plurality of dielectric layers and a plurality of conductive layers, without semiconductor transistor configuration. The electronic package as claimed in claim 1, wherein the heat dissipation path of the chip at least includes the back surface and the side surfaces of each chip. The electronic package as claimed in claim 1, wherein for a reference projection plane, the projection of the wafer falls inside the projection of the redistribution wiring structure. The electronic package as claimed in item 1, wherein the sub-package further includes: A redistribution line structure is configured on the intermediate conduction structure. The electronic package as claimed in item 6, wherein the sub-package further includes: A plurality of conductive bumps are arranged on the redistribution circuit structure. The electronic package as claimed in item 1, wherein the sub-package further includes: A plurality of conductive bumps are arranged on the intermediate conduction structure. The electronic package as claimed in claim 1, wherein the intermediate conduction structure has an intermediate dielectric layer and a plurality of intermediate conduction vias, and these intermediate conduction vias pass through the intermediate dielectric layer and are respectively connected to the chip contacts of these chips. pad. The electronic package as claimed in item 9, wherein the sub-package further includes: A plurality of conductive bumps are arranged on the intermediate conduction structure, wherein each of the conductive bumps is connected to the end of the corresponding intermediate conduction channel. The electronic package as claimed in claim 1, wherein the at least one bridge element has a plurality of bridge vias, and the chips electrically connected to the bridge element are electrically connected to the intermediate via through the bridge vias. The electronic package as described in claim 1, further comprising: A circuit carrier, on which the subpackage is mounted. The electronic package as claimed in claim 12, wherein the number of the sub-packages is multiple, and the sub-packages are mounted on the same surface of the circuit carrier. The electronic package as claimed in claim 12, wherein the number of the sub-packages is multiple, and the sub-packages are mounted on opposite sides of the circuit carrier respectively. The electronic package as described in claim 12, further comprising: A plurality of conductive balls are connected to the circuit carrier. The electronic package as claimed in claim 1, wherein the thermal conductivity of the metal layer is greater than 300W/mK. The electronic package as claimed in claim 1, wherein one of the chips includes a central processing unit chip, a logic chip, a graphics processing chip, an input/output chip, a memory chip, a baseband chip, a radio frequency chip or a special function integrated circuit wafer. A method of manufacturing an electronic package, comprising: Provide multiple wafers; forming a shielding layer on the active surface of each of the wafers; fixing the wafers to temporary carriers via a temporary bonding layer; forming a metal layer over the back and sides of each of the wafers, the periphery of the masking layer and the temporary bonding layer, wherein the metal layer conforms to the back and sides of each of the wafers; removing the temporary carrier and the temporary bonding layer; removing a part of the metal layer to expose the periphery of each of the shielding layers, and making the surface of the metal layer flush with the active surface of each of the wafers; mounting a bridge element on adjacent ones of the chips such that the bridge element partially overlaps the adjacent chips respectively, wherein the plurality of first bridge pads of the bridge element directly bond to the chip pads respectively; and forming an intermediate conductive structure on the chips, the metal layer and the bridge element. The method for manufacturing an electronic package as claimed in item 18, wherein the step of forming the metal layer includes: comprehensively forming an electroplating seed layer on the wafers, the masking layers and the temporary bonding layer; A metal material layer is electroplated on the electroplating seed layer to cover the back and side surfaces of each of the wafers, the periphery of each of the masking layers and the temporary bonding layer, so that the metal material layer and the wafers the back and sides of each conform; and planarizing and thinning the metal material layer to form the metal layer. The method for manufacturing an electronic package as claimed in claim 18, wherein the step of forming the intermediate conductive structure includes: forming an interposer dielectric layer over the wafers, the metal layer and the bridge element; and Forming a plurality of intermediate conductive holes in the intermediate dielectric layer to form the intermediate conductive structure, wherein the intermediate conductive holes are respectively connected to the chips and the bridge element. The method for manufacturing an electronic package as claimed in claim 20, wherein the step of forming the intervening conductive channels includes: forming a plurality of through holes in the interposer dielectric layer to expose a plurality of die pads and a plurality of second bridge pads of the bridge element; and Each of the through holes is filled with conductive material to form a plurality of intermediary conductive channels. The method for making an electronic package as described in claim 20, further comprising: A conductive bump is formed at the end of each of the intervening conductive holes. The method for making an electronic package as described in Claim 18, further comprising: A redistribution circuit structure is formed on the intermediate conductive structure. The method for making an electronic package as described in Claim 18, further comprising: A plurality of conductive bumps are formed on the redistribution wiring structure. The method of manufacturing an electronic package as claimed in claim 18, wherein the thickness of the metal layer is greater than the thickness of the chip. The method for manufacturing an electronic package as claimed in claim 18, wherein the bridge element is composed of a plurality of dielectric layers and a plurality of conductive layers, without semiconductor transistor configuration. The method for manufacturing an electronic package as claimed in claim 18, wherein the heat dissipation path of the chip at least includes the back surface and the side surfaces of each chip. The method of manufacturing an electronic package as claimed in claim 18, wherein the thermal conductivity of the metal layer is greater than 300W/mK.

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