TWI666773B - 半導體功率元件 - Google Patents

半導體功率元件 Download PDF

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TWI666773B
TWI666773B TW103117722A TW103117722A TWI666773B TW I666773 B TWI666773 B TW I666773B TW 103117722 A TW103117722 A TW 103117722A TW 103117722 A TW103117722 A TW 103117722A TW I666773 B TWI666773 B TW I666773B
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semiconductor layer
semiconductor
power device
semiconductor power
electrode
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楊亞諭
林恒光
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晶元光電股份有限公司
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Abstract

一半導體功率元件,包含一基板、一第一半導體層、一第二半導體層、一第三半導體層、一源極電極、一背向電極以及一P型金屬氧化層。第一半導體層具有一第一能隙,且位於基板上方;第二半導體層具有一第二能隙大於第一能隙,且位於第一半導體層上方;第三半導體層具有一第三能隙小於第二能隙,且位於第二半導體層上方;源極電極位於第三半導體層上方;背向電極電性連接源極電極;P型金屬氧化層位於背向電極以及第三半導體層之間。

Description

半導體功率元件
本發明是關於一種半導體功率元件,更具體而言,係關於一種p型金屬氧化層上具有背向電極之半導體功率元件。
近年來氮化鎵材料在光電及電子元件的商業應用上,有相當大幅度的成長,以氮化鎵為材料的半導體功率元件,如氮化鋁鎵-氮化鎵(AlGaN/GaN),具高速電子遷移率、可在惡劣和高溫的環境下操作,以及提供高功率之操作特性。然而,在高功率元件的運用上,如何抑制閘極通道邊緣處的高電場區域,以提升元件電特性及防止電流崩塌,將是重要的議題。
本發明係關於一種半導體功率元件,包含一基板;一第一半導體材料具有一第一能隙,且位於基板上方;一第二半導體層具有一第二能隙大於第一能隙,且位於第一半導體層上方;一第三半導體層具有一第三能隙小於第二能隙,且位於第二半導體層上方;一源極電極位於第三半導體層上方;一背向電極電性連接源極電極;一背向電極電性連接源極電 極;以及一p型金屬氧化層位於背向電極以及第三半導體層之間。
為讓本發明之上述和其他目的、特徵和優點能更明顯易懂,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下
11‧‧‧基板
12‧‧‧緩衝層
13‧‧‧第一半導體層
1314‧‧‧第一介面
14‧‧‧第二半導體層
1415‧‧‧第二介面
15‧‧‧第三半導體層
16、26‧‧‧P型金屬氧化層
17‧‧‧背向電極
18‧‧‧源極電極
19‧‧‧汲極電極
20‧‧‧閘極電極
2DEG‧‧‧二維電子氣
2DHG‧‧‧二維電洞氣
第1A~1F圖係顯示本發明之一實施例中一半導體功率元件100之製作流程圖。
第2圖係顯示本發明一實施例中半導體功率元件之開啟狀態示意圖。
第3圖係顯示本發明另一實施例之一半導體功率元件示意圖。
以下實施例將伴隨著圖式說明本發明之概念,在圖式或說明中,相似或相同之部分係使用相同之標號,並且在圖式中,元件之形狀或厚度可擴大或縮小。需特別注意的是,圖中未繪示或描述之元件,可以是熟習此技藝之人士所知之形式。
第1A~1F圖係顯示本發明之一實施例中一半導體功率元件100之製作流程圖。參照第1A~1D圖,首先在基板11上形成一緩衝層12,接著依序形成一第一半導體層13在緩衝層12之上,一第二半導體層14在第一半導體層13之上,以及一第三半導體層15在第二半導體層14之上。參照第1E~1F圖,形成一p型金屬氧化層16於第三半導體層15之上,接著形成一背向電極 17於p型金屬氧化層16之上,一源極電極18以及一汲極電極19分別形成於p型金屬氧化層16之兩側,以及一閘極電極20形成在源極電極18與背向電極17之間,即完成本實施例之半導體功率元件100。在本實施例中,背向電極可影響元件之極化特性,以達到正負電荷平衡,使得整體電場分布均勻。
基板11之材料包含藍寶石、碳化矽、氮化鎵或矽;緩衝層12包含III-V族材料,例如但不限定為氮化鋁(AlN)或氮化鋁(AlN)及氮化鋁鎵(AlGaN)之疊層。以矽基板為例,緩衝層係形成於矽基板的[111]面上,並朝(0001)的方向成長,用來減少矽基板與後續成長的磊晶疊層之間的晶格常數差異,以提升晶格品質。需注意的是,藉由完全或部分移除基板,可使後續形成本實施例所述之半導體功率元件時減少元件的漏電路徑,以達到降低漏電的效果。
第一半導體層13具有一第一能隙,第二半導體層14具有一第二能隙大於第一半導體13之第一能隙,意即第二半導體層14之晶格常數係小於第一半導體層13之晶格常數。具體而言,本實施例中組成第一半導體層13之材料包含InxGa(1-x)N,且0≦x<1,例如但不限定為氮化鎵(GaN);組成第二半導體層之材料包含AlyInzGa(1-z)N,且0<y<1以及0≦z<1,例如但不限定為氮化鋁鎵(AlGaN)。在本實施例中,藉由第一半導體層13與第二半導體層14本身的自發極化,以及第一半導體層11與第二半導體層12之間晶格常數不同所造成的壓電極化,在第一半導體層13與第二半導體層14之間的一第一介面1314形成一二維電子氣2DEG。需注意的是,本實施例所述之第一半導體層13及第二半導體層14皆為未摻雜的半導體材料,但依據實際應用亦可為摻雜的半導體材料,摻雜物質例如但不限定為矽甲烷,用以增加壓電極化 與自發極化的效果,進而提升第一介面1314中二維電子氣2DEG的濃度。
第三半導體層15具有一第三能隙小於第二半導體14之第二能隙,意即第三半導體層15之晶格常數係大於第二半導體層14之晶格常數。具體而言,本實施例中組成第三半導體層15之材料包含InxGa(1-x)N,且0≦x<1,例如但不限定為氮化鎵(GaN)。如1E圖所示,p型金屬氧化層形成於第三半導體層之一上表面151。於本實施例中,係利用黃光微影技術定義出p型金屬氧化層16之預定形成區域,接著藉由射頻濺鍍系統,於製程溫度低於500℃的條件下,將p型金屬氧化層16沉積於預定區域中,而p型金屬氧化層16之材料包含NiO、MoO、CuO、ZnO或SnO2等,但亦可為其他金屬氧化物材料。在本實施例中,藉由第二半導體層14與第三半導體層15之間晶格常數不同,以及p型金屬氧化層16形成於第三半導體層15上方所造成的反極化效應,將第二半導體層14表面的價帶(Ev)提高至費米能階之上(Ef)之上,進而在第二半導體層14與第三半導體層15之間的一第二介面1415且位於p型金屬氧化層16下方的位置,形成一二維電洞氣2DHG。需注意的是,本實施例所述之第三半導體層15為未摻雜的半導體材料,但依據實際應用亦可為摻雜的半導體材料,摻雜物質例如但不限定為矽甲烷。此外,第三半導體層15係具有保護層作用以防止第二半導體層14表面因後續製程受到損害,亦可避免二維電子氣2DEG直接受到p型金屬氧化層16的影響,造成電子濃度下降。本實施例所形成之p型金屬氧化物,不易受到製程過程影響其摻雜濃度,故具有較高濃度摻雜(>1E19),元件特性較佳。其製程簡單,不須經過乾/濕蝕刻製程,防止元件表面被嚴重損壞;低溫的製程溫度,可降低製程過程中造成元件特性的衰退;黃光微影技術所採用去除光阻的化學 液體為有機去光阻液,例如丙酮,屬弱鹼性,相較於乾/濕蝕刻製程所使用之強酸性去光阻液,例如氫氟酸,較不易損害元件表面。
如第1F圖所示,p型金屬氧化層16係位於背向電極17極第三半導體層15之間,背向電極17之材料可例如為鎳/金合金材料或其他合金材料,並與p型金屬氧化層16形成歐姆接觸;源極電極18以及汲極電極19分別形成於背向電極17之兩側,位於第三半導體層15之上,其形成材料可例如為鈦/鋁/鈦/金合金、鈦/鋁/鎳/金合金或其他鈦/鋁合金材料,並與第三半導體層15形成歐姆接觸,且源極電極18電性連接背向電極17;一閘極電極20形成於源極電極18與p型金屬氧化層16之間,其形成材料可例如為鎳/金合金材料或其他合金材料,且位於第三半導體層15之上,與第三半導體層15形成蕭特基接觸,即完成本實施例之半導體功率元件100。其中,源極電極18、汲極電極19以及閘極電極20係用以作為與外部電性連接的端點,且可根據實際需求來控制半導體功率元件的操作狀態以及二維電子氣的分布情況。需注意的是,本實施例所述之閘極電極20係位於遠離汲極電極19且較接近源極電極18的位置,以利於提高元件之崩潰電壓。
第2圖顯示本發明一實施例中半導體功率元件之開啟狀態示意圖。本實施例之半導體功率元件100係一常開型半導體功率元件,當給予汲極電極19一正偏壓(如+600~+1000V),背向電極17電性連接源極電極18並同時接地(0V),給予閘極電極20一負偏壓(如-10~-20V),使閘極電極20下方之導帶(Ec)拉升至費米能階(Ef)之上,以消散閘極電極20下方之二維電子氣2DEG,半導體功率元件100呈現關閉狀態(逆向偏壓狀態),此時藉由p型金屬氧化層16下方二維電洞氣2DHG與二維電子氣2DEG的形成,可 有效改善電場過度集中於閘極電極20下方,以利於分散電場強度,使整體電場分布更加均勻,進而防止電流崩塌導致元件燒毀。此外,本實施例中,將背向電極17接地(0V),以固定背向電極之電位,以防止電位浮動,增加元件之穩定性。需注意的是,本實施例之半導體功率元件係利用氮化鎵(GaN)與氮化鋁鎵(AlGaN)所形成之異質結構,使得元件具有較高的電子遷移率,達到非常快的切換速度,且具有可在高頻、高功率及高溫工作環境下操作的元件特性。
第3圖係顯示本發明另一實施例之一半導體功率元件300。本實施例之半導體功率元件與前一實施例具有相似的結構,除了將p型金屬氧化層26形成一奈米柱結構,得以局部加強二維電洞氣2DHG之濃度,有效改善電場過度集中於閘極電極下方,以利於分散電場強度,使整體電場分布更加均勻,進而防止電流崩塌導致元件燒毀。
需了解的是,本發明中上述之實施例在適當的情況下,是可互相組合或替換,而非僅限於所描述之特定實施例。本發明所列舉之各實施例僅用以說明本發明,並非用以限制本發明之範圍。任何人對本發明所作之任何顯而易見之修飾或變更接不脫離本發明之精神與範圍。

Claims (10)

  1. 一種半導體功率元件,包含:一基板;一第一半導體層,具有一第一能隙,且位於該基板上方;一第二半導體層,具有一第二能隙大於該第一能隙,且位於該第一半導體層上方;一第三半導體層,具有一第三能隙小於該第二能隙,且位於該第二半導體層上方;一源極電極,位於該第三半導體層上方;一背向電極,電性連接該源極電極;以及一p型金屬氧化層,位於該背向電極以及該第三半導體層之間;一汲極電極,且該p型金屬氧化層位於該源極電極以及該汲極電極之間;以及一閘極電極,位於該源極電極以及該背向電極之間。
  2. 如申請專利範圍第1項所述之半導體功率元件,其中該p型金屬氧化層包括NiO、MoO、CuO、ZnO或SnO2
  3. 如申請專利範圍第1項所述之半導體功率元件,其中該p型金屬氧化層包括一奈米柱結構。
  4. 如申請專利範圍第1項所述之半導體功率元件,更包括一二維電子氣以及一第一介面位於該第一半導體層以及該第二半導體層之間,其中當該半導體功率元件處於開啟狀態時,該二維電子氣形成於該第一介面。
  5. 如申請專利範圍第1項所述之半導體功率元件,更包括一二維電洞氣以及一第二介面位於該第二半導體層以及該第三半導體層之間,其中當該半導體功率元件處於開啟狀態時,該二維電洞氣形成於該第二介面。
  6. 如申請專利範圍第1項所述之半導體功率元件,其中該第一半導體層包括InxGa(1-x)N,且0≦x<1。
  7. 申請專利範圍第1項所述之半導體功率元件,其中該第二半導體層包括AlyInzGa(1-y-z)N,且0<y<1以及0≦z<1。
  8. 申請專利範圍第1項所述之半導體功率元件,其中該第三半導體層包括InwGa(1-w)N,且0≦w<1。
  9. 申請專利範圍第1項所述之半導體功率元件,其中該p型金屬氧化層與該背向電極形成歐姆接觸。
  10. 申請專利範圍第1項所述之半導體功率元件,其中該閘極電極與該第三半導體層形成蕭特基接觸。
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US20080121876A1 (en) * 2005-07-13 2008-05-29 Sanken Electric Co., Ltd. Surface-stabilized semiconductor device

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