TWI653735B - 輻射硬式高速光二極體裝置 - Google Patents

輻射硬式高速光二極體裝置 Download PDF

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TWI653735B
TWI653735B TW106138130A TW106138130A TWI653735B TW I653735 B TWI653735 B TW I653735B TW 106138130 A TW106138130 A TW 106138130A TW 106138130 A TW106138130 A TW 106138130A TW I653735 B TWI653735 B TW I653735B
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吉瑞德 曼哈特
艾渥德 瓦奇曼
馬汀 沙格梅斯特
傑恩斯 荷夫萊奇特
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瑞士商Ａｍｓ國際有限公司
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Abstract

光二極體裝置，包含：基板(1)，其由半導體材料製成並具有主面(10)；第一導電類型的複數個摻雜井(3)，其在該主面(10)處間隔開；以及保護環(7)，其包括第二導電類型的摻雜區域，該第二導電類型與該第一導電類型相反。該保護環(7)圍繞包括複數個摻雜井(3)的主面(10)的區域而不分割該區域。導體軌(4)與摻雜井(3)電連接，摻雜井(3)因此互連，並且額外導體軌(5)與第二導電類型的區域電連接。第二導電類型的摻雜表面區(2)存在於主面(10)處並且覆蓋保護環(7)和摻雜井(3)之間的整個區域。

Description

輻射硬式高速光二極體裝置
電腦斷層掃描(computed tomography)使用X射線生成例如人體的固體物體的三維圖像。閃爍器(scintillator)將X射線轉換為可見光，然後藉由光二極體陣列進行檢測。光二極體可以藉由晶圓接合(wafer-to-wafer bonding)、由半導體晶片的覆晶(flip-chip)組裝、或者由在相同的半導體裝置中CMOS元件和光二極體的單片集成(monolithic integration)等方式來與CMOS電路連接。單片集成提供了光二極體和CMOS電路之間的最佳互連，但是適用於CMOS電路的半導體材料在低漏電流、低電容、高靈敏度、短反應時間和輻射硬化方面可能會同時導致光二極體的集成困難。而且，響應度的低溫係數對CMOS兼容光二極體帶來了挑戰；這是最新技術無法達到的要求。
WO 2006/131209 A2公開了一種具有積體半導體電路的光二極體。光二極體由晶圓接合的方式而形成為分層結構。該電路由穿透半導體本體的觸點連接至二極體。
US 6 690 074 B1公開了一種用於減少由入射電離輻射引起的電流的半導體裝置結構。它包含p基板、n井內的n+摻雜表面區，以及用於阻擋其它位於n井附近的半導體裝置的n井和n摻雜區之間的輻射誘導寄生電流流動的p+摻雜保護環。
US 2015/0287847 A1公開了一種具有可縮小的空間電荷區的光二極體裝置。該裝置包括與位於基板表面具有相同導電類型的接觸區鄰接的摻雜區域、附屬的陽極或陰極連接、在基板表面具有相反導電類型的額外接觸區，以及額外的陽極或陰極連接。橫向pn接面在基板表面處由其中一個接觸區的邊界形成。場電極佈置在橫向pn接面之上，經由介電材料與橫向pn接面分離，並且設有與陽極和陰極連接分開的額外電連接，用於由減少在表面處的空間電荷區來減少暗電流(dark current)。
N.V.Loukianova等人的“Leakage Current Modeling of Test Structures for Characterization of Dark Current in CMOS Image Sensors”，IEEETransactions on Electron Devices期刊 第50(1)冊，第77至83頁，2003，描述了一種光二極體，其包括用以減少暗電流而被p井包圍的n井。經由淺p+植入物鈍化橫向pn接面，將位於表面的空間電荷區的寬度減半。
M.Battaglia等人的“Development of a Radiation Hard CMOS Monolithic Pixel Sensor”，2008年IEEE核科學研討會會議記錄，第3501至3504頁，描述了 一種著重在優異的輻射耐受性的CMOS單片像素感測器原型。光二極體陣列的像素佈局包括由浮置的p+保護環包圍的n井二極體、在二極體上方的薄氧化層、以及覆蓋該n井周圍區域的多晶矽環。
儘管先前技術滿足低漏電和/或低電容的要求，但要同時匹配高速和響應度的低溫係數仍然是一個未解決的挑戰。此外，光二極體與CMOS電路的單片集成能夠保證製造這種裝置的成本效益的方式。
本發明的目的是提供一種具有低電容、低漏電流、以及低溫係數的響應度的輻射硬式高速光二極體。
本目的根據申請專利範圍第1項的光二極體裝置來實現。實施例源於附屬項。
輻射硬式高速光二極體裝置包含：基板，其由半導體材料製成並具有主面；具有第一導電類型的多個摻雜井，其在主面處間隔開；保護環，其包含第二導電類型摻雜區的保護環，該第二導電類型與第一導電類型相反；導體軌，其與摻雜井電連接；以及額外導體軌，其與該第二導電類型之區域電連接。導體軌將摻雜井互連。保護環圍繞包括複數個摻雜井的主面之區域，而不分割該區域。第二導電類型的摻雜表面區存在於主面並覆蓋保護環及摻雜井之間的整個區域。
在光二極體裝置的一個實施例中，額外導體軌與摻雜表面區電連接。
另一個實施例包含保護環的邊界區，邊界區包含第二導電類型，以及佈置在邊界區內的保護環的核心區，核心區包含第一導電類型。
另一個實施例包含沿保護環設置的金屬層，以及與保護環接觸的金屬層的接觸塞。額外導體軌連接至金屬層。
在另一個實施例中，金屬層的接觸塞接觸邊界區和核心區。
在另一個實施例中，導體軌與額外導體軌彼此平行且交替地佈置。
另一個實施例包含佈置在摻雜井內的主面的接觸區以及將導體軌與接觸區連接的接觸塞，接觸區具有比摻雜井的摻雜濃度更高的摻雜濃度。
另一個實施例包含佈置在摻雜井附近的摻雜表面區上的額外接觸塞。額外接觸塞連接至額外導體軌。其中一個接觸塞和最靠近該接觸塞的額外接觸塞之間的距離，小於與該接觸塞連接的導體軌和與該額外接觸塞連接的額外導體軌之間的距離。
另一個實施例包含周邊導體軌。導體軌與周邊導體軌連接。
在另一個實施例中，第一導電類型是n型導電性，第二導電類型是p型導電性。周邊導體軌被提供為陰極端，而額外導體軌被提供為陽極端。
另一個實施例包含在主面上或之上的介電 質。導體軌和額外導體軌嵌入在介電質中。
在另一個實施例中，基板包含半導體本體與在半導體本體上生長的磊晶層，並且主面由磊晶層的表面形成。
在另一個實施例中，磊晶層被摻雜用於第二導電類型。摻雜表面區形成在磊晶層內並具有比磊晶層的摻雜濃度更高的摻雜濃度。
在另一個實施例中，複數個摻雜井被提供用於像素之陣列的其中一個像素，該陣列之像素由保護環分開。
在另一個實施例中，導體軌分別針對每個像素互連，而額外導體軌針對陣列的所有共同像素互連。
另一個實施例包含複數個第二導電類型的環形摻雜井，每個環形摻雜井橫向圍繞其中一個摻雜井。
以下結合附圖對輻射硬式高速光二極體裝置的實施例進行更詳細的描述。
1‧‧‧基板
2‧‧‧摻雜表面區
3‧‧‧摻雜井
4‧‧‧導體軌
5‧‧‧額外導體軌
6‧‧‧金屬層
7‧‧‧保護環
8‧‧‧周邊導體軌
9‧‧‧介電質
10‧‧‧主面
11‧‧‧半導體本體
12‧‧‧磊晶層
13‧‧‧接觸區
14‧‧‧接觸塞
15‧‧‧額外接觸塞
16‧‧‧接觸塞
17‧‧‧邊界區
18‧‧‧核心區
19‧‧‧環形摻雜井
第1圖顯示包括一個像素的光二極體裝置的一部分的俯視圖。
第2圖顯示第1圖所示的剖面圖。
第3圖是根據第2圖的具有不同導體軌的另一個實施例的剖面圖。
第4圖是根據第3圖的實施例的一部分的俯視圖。
第5圖是根據第2圖的具有額外摻雜井的另一實施例的剖面圖。
第1圖是沒有覆蓋介電質的光二極體裝置的俯視圖。隱藏的輪廓由虛線表示。基板1包含例如像矽一樣的半導體材料。摻雜表面區2佔據了整個表面，除了在基板1的上表面形成並且彼此間隔開的摻雜井3的區域以外。因此，避免了像淺溝槽隔離或場氧化物區那樣的絕緣區的佈置。
摻雜井3的數量以及它們的佈置是任意的。第1圖所示的佈置只是一個合適模式的範例。摻雜井3之間的距離及其形狀也可以被修改和調整以滿足各個實施例的要求。摻雜表面區2和摻雜井3具有相反的導電類型。
摻雜井3經由導體軌4電連接。額外導體軌5與導體軌4分開佈置。額外導體軌5電連接至與摻雜表面區2相同導電類型的半導體材料，並且可以特別地電連接至摻雜表面區2。相反地，摻雜表面區2的電勢可以保持浮動。作為範例，如第1圖所示，導體軌4和額外導體軌5可以是平行且交替的順序。
為一個像素提供複數個摻雜井3，其可以是用於圖像檢測的像素陣列的像素。該複數個摻雜井3被保護環7包圍，該保護環7不與該複數個摻雜井3所佈置的區域分開或交叉。保護環7可以至少部分地包含與摻雜表 面區2相同的導電類型。
金屬層6可視需要地沿著保護環7上方佈置。如第1圖所示，金屬層6可以提供作為用於額外導體軌5的共用電端(electricsl terminal)。周邊導體軌8可以類似地提供為導體軌4的共用電端。周邊導體軌8可以連接至在像素陣列外圍上的控制或讀出電路，從而提供所討論的像素的單獨的電端。
第2圖顯示第1圖所示的剖面圖。在第1圖和第2圖中，對應的元件帶有相同的符號。在第1圖中，基板1被示出為包含半導體本體11，半導體本體11提供有形成主面10的視需要的磊晶層12。如果磊晶層12磊晶生長，則其具有與半導體本體11基本上相同的晶體結構。磊晶層12被摻雜用於與摻雜井3的導電類型相反的導電類型。半導體本體11可以是未摻雜的或本徵摻雜的，或者可以與磊晶層12摻雜為相同的導電類型。如果基板1不包含磊晶層，則其可視需要地摻雜用於與摻雜井3的導電類型相反的導電類型。
第2圖顯示摻雜表面區2覆蓋摻雜井3和保護環7之間的主面10的整個區域。摻雜表面區2的摻雜濃度高於基板1的摻雜濃度，特別是磊晶層12的摻雜濃度。
導體軌4和額外導體軌5可以嵌入介電質9中，介電質9是鋪設在主面10上或之上。例如，介電質9可以是諸如氧化矽的金屬間介電質，其通常用於CMOS裝置的佈線。在第1圖的俯視圖中，基板表面和佈置在基板 表面之上的導體的輪廓則顯示為好像它們沒有被介電質9隱藏。
導體軌4經由接觸塞14與摻雜井3電連接，接觸塞14被鋪設在摻雜井3的接觸區13上。接觸區13包括高於摻雜井3的摻雜濃度的摻雜濃度，並且因此能夠在摻雜阱3的區域內的主面10上與接觸塞14形成歐姆接觸。
額外導體軌5可以由額外接觸塞15電連接至摻雜表面區2。摻雜表面區2的相對較高的摻雜濃度允許形成歐姆接觸。如第2圖所示，額外接觸塞15可以緊鄰佈置在摻雜井3的附近，靠近在摻雜井3與具有相反導電類型的周圍半導體材料之間形成的pn接面。
第1圖顯示位在摻雜井3對面具有短分支的額外導體軌5。這些分支局部地減少了額外導體軌5和摻雜井3之間的距離，而不減少導體軌4與額外導體軌5的平行部分之間的距離。因此，可以使額外導體軌5和相鄰的導體軌4之間的距離盡可能地大，而不必增加接觸塞14和額外接觸塞15之間的距離。考慮到導體軌4和額外導體軌5之間的低電容，這可能是期望的。類似的分支可以替代地或附加地提供在導體軌4上，在這種情況下可以佈置在從摻雜井3的中心之上的位置橫向偏移的位置。
第2圖顯示作為結構化低金屬化層級的部分的導體軌4，以及作為結構化高金屬化層級的部分的額外導體軌5。導體軌4的高度可以反而高於額外導體軌5 的高度，或者導體軌4和額外導體軌5可以形成在相同的金屬化層中。額外導體軌5可以替代地直接鋪設在摻雜井3之間區域中的摻雜表面區2上。
第2圖顯示保護環7，其減少了相鄰像素之間的串擾。在第2圖所示的範例中，保護環7包含視需要的邊界區17及核心區18。邊界區17具有與摻雜表面區2相同的導電類型，並且核心區18具有相反的導電類型。視需要的金屬層6，其可以提供在保護環7之上並且沿著保護環7，係藉由複數個接觸塞16而電連接至邊界區17和核心區18兩者。金屬層6可以提供給整個像素陣列作為額外導體軌5的共用電端。
如果摻雜表面區2具有p型導電性，則摻雜井3尤其可以具有n型導電性。在這種情況下，導體軌4和周邊導體軌8被提供為陰極端，並且額外導體軌5及視需要的金屬層6被提供為陽極端。導電類型可以反過來。
第3圖是根據第2圖的另一個實施例的剖面圖。對應於根據第2圖實施例之元件的第3圖實施例元件係用相同的符號表示。在根據第3圖的實施例中，額外導體軌5佈置在導體軌4之上。因此，導體軌4與相應的額外導體軌5之間沒有橫向距離。在根據第3圖的堆疊佈置中，導體軌4和額外導體軌5形成在不同的金屬化平面中，這些金屬化平面經由介電質9彼此隔離。堆疊佈置的優點在於入射輻射被導體軌4和額外導體軌5屏蔽的區域是最小的。此外，考慮到減小裝置的尺寸，堆疊佈置可以 是合適的。
第4圖是根據第3圖的實施例的一部分的俯視圖。第4圖示出了兩個摻雜井3和附屬的接觸區13。這些區域的輪廓用虛線表示。在第4圖的俯視圖中，額外導體軌5覆蓋導體軌4，因此也用虛線表示。額外導體軌5係提供分支，這些分支將額外導體軌5與額外接觸塞15連接。第4圖還示出根據第5圖所示的另一實施例的橫向圍繞摻雜井3的環形摻雜井19。
第5圖是根據第2圖的另一個實施例的剖面圖。對應於根據第2圖實施例之元件的第5圖實施例元件係用相同的符號表示。在根據第5圖的實施例中，摻雜井3橫向地被環形摻雜井19圍繞，環形摻雜井19被摻雜用於第二導電類型並且因此具有與摻雜表面區2相同的導電類型。環形摻雜井19具有減少光二極體的電容的優點。低電容特別有利於改進信號對雜訊比。
在根據第5圖的實施例中，根據第2圖所示的實施例或者根據第3圖所示的實施例，額外導體軌5可以在任一側分支。第5圖以範例的方式示出與根據第3圖的實施例的額外導體軌5類似的額外導體軌5。
對於CMOS裝置來說，通常1016cm-3的半導體本體的摻雜濃度是導致空間電荷區的尺寸減小並且因此具有相對高的電容的原因。這是所謂kBT/C雜訊的主要來源，其中kB是玻爾茲曼常數，T是絕對溫度而C是光二極體的電容。與使用引線接合或矽通孔的互連以及非常短 的互連長度相比，所描述的光二極體裝置藉由低接面電容、光二極體與CMOS讀出電路之間的非常低的互連電容，來顯著降低kBT/C雜訊行為。摻雜表面區實質上增強了光二極體裝置的反應，而不會惡化電容或對電容具有不利影響。
所描述的光二極體裝置包含低電容、低漏電流、良好的光譜響應度、輻射硬度，特別是對於至少在低於100keV的範圍內的X射線，以及相對短的上升和下降時間以及低響應度溫度係數。與更複雜的三維光二極體結構相比，這些特徵使得該光二極體有利地以較低的價格提供較高的產量。

Claims (16)

  1. 一種光二極體裝置，包含：- 基板(1)，其由半導體材料製成並具有主面(10)，- 複數個摻雜井(3)，其具有第一導電類型並在該主面(10)處間隔開，- 保護環(7)，其包含第二導電類型的摻雜區(17)，該第二導電類型與該第一導電類型相反，- 導體軌(4)，其與該摻雜井(3)電連接，以及- 額外導體軌(5)，其與該第二導電類型的區域電連接，其特徵在於- 該導體軌(4)將該摻雜井(3)互連，- 該保護環(7)圍繞包括該複數個摻雜井(3)的該主面(10)之區域，而不分割此區域，以及- 該第二導電類型的摻雜表面區(2)存在於該主面(10)並覆蓋該保護環(7)與該摻雜井(3)之間的整個區域，其中，該保護環(7)及該摻雜井(3)沒有被該摻雜表面區(2)覆蓋。
  2. 如申請專利範圍第1項所述之光二極體裝置，其中，該額外導體軌(5)與該摻雜表面區(2)電連接。
  3. 如申請專利範圍第1或2項所述之光二極體裝置，更包含：該保護環(7)的邊界區(17)以及佈置在該邊界區(17)內的該保護環(7)的核心區(18)，該邊界區(17)包含該第二導電類型，該核心區(18)包含該第一導電類型。
  4. 如申請專利範圍第1或2項所述之光二極體裝置，更包含：沿該保護環(7)設置的金屬層(6)、與該保護環(7)接觸的該金屬層(6)的接觸塞(16)，以及該額外導體軌(5)連接至該金屬層(6)。
  5. 如申請專利範圍第4項所述之光二極體裝置，更包含：該保護環(7)的邊界區(17)以及佈置在該邊界區(17)內的該保護環(7)的核心區(18)，該邊界區(17)包含該第二導電類型，該核心區(18)包含該第一導電類型，其中，該金屬層(6)的該接觸塞(16)接觸該邊界區(17)及該核心區(18)。
  6. 如申請專利範圍第1或2項所述之光二極體裝置，其中，該導體軌(4)與該額外導體軌(5)彼此平行且交替地佈置。
  7. 如申請專利範圍第1或2項所述之光二極體裝置，更包含：佈置在該摻雜井(3)內的該主面(10)的接觸區(13)以及將該導體軌(4)與該接觸區(13)連接的接觸塞(14)，該接觸區(13)具有比該摻雜井(3)的摻雜濃度更高的摻雜濃度。
  8. 如申請專利範圍第7項所述之光二極體裝置，更包含：佈置在該摻雜井(3)附近的該摻雜表面區(2)上的額外接觸塞(15)，該額外接觸塞(15)連接至該額外導體軌(5)，並且其中一個該接觸塞(14)和最靠近該接觸塞(14)的該額外接觸塞(15)之間的距離，小於與該接觸塞(14)連接的該導體軌(4)和與該額外接觸塞(15)連接的該額外導體軌(5)之間的距離。
  9. 如申請專利範圍第1或2項所述之光二極體裝置，更包含：周邊導體軌(8)，該導體軌(4)與該周邊導體軌(8)連接。
  10. 如申請專利範圍第9項所述之光二極體裝置，其中，該第一導電類型是n型導電性，而該第二導電類型是p型導電性，該周邊導體軌(8)被提供為陰極端，並且該額外導體軌(5)被提供為陽極端。
  11. 如申請專利範圍第1或2項所述之光二極體裝置，更包含：在該主面(10)上或之上的介電質(9)，該導體軌(4)和該額外導體軌(5)嵌入在該介電質(9)中。
  12. 如申請專利範圍第1或2項所述之光二極體裝置，更包含：包含半導體本體(11)與在該半導體本體(11)上生長的磊晶層(12)的該基板(1)，該主面(10)由該磊晶層(12)的表面形成。
  13. 如申請專利範圍第12項所述之光二極體裝置，其中，該磊晶層(12)被摻雜用於該第二導電類型，該摻雜表面區(2)形成在該磊晶層(12)內，以及該摻雜表面區(2)具有比該磊晶層(12)的摻雜濃度更高的摻雜濃度。
  14. 如申請專利範圍第1或2項所述之光二極體裝置，其中，該複數個摻雜井(3)被提供用於一陣列之像素的其中一個像素，該陣列之該像素由該保護環(7)分開。
  15. 如申請專利範圍第14項所述之光二極體裝置，其中，該導體軌(4)分別針對每個像素互連，以及該額外導體軌(5)針對該陣列的所有共同像素互連。
  16. 如申請專利範圍第1或2項所述之光二極體裝置，更包含：複數個該第二導電類型的環形摻雜井(19)，每個該環形摻雜井(19)橫向圍繞其中一個該摻雜井(3)。
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US10854646B2 (en) * 2018-10-19 2020-12-01 Attollo Engineering, LLC PIN photodetector

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WO2018104111A1 (en) 2018-06-14
CN109983587A (zh) 2019-07-05
TW201826493A (zh) 2018-07-16
EP3331034A1 (en) 2018-06-06
EP3331034B1 (en) 2022-02-02
US20190319156A1 (en) 2019-10-17

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