TWI650568B - Test system and method for testing an integrated circuit and a circuit board including the integrated circuit - Google Patents

Test system and method for testing an integrated circuit and a circuit board including the integrated circuit Download PDF

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TWI650568B
TWI650568B TW106138138A TW106138138A TWI650568B TW I650568 B TWI650568 B TW I650568B TW 106138138 A TW106138138 A TW 106138138A TW 106138138 A TW106138138 A TW 106138138A TW I650568 B TWI650568 B TW I650568B
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current
voltage
circuit
resistance
pin
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TW201918724A (en
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張佑榕
廖緯凱
林明慶
曾奎皓
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日月光半導體製造股份有限公司
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Abstract

一種測試系統包括一減法器及一除法器。該減法器經組態以接收正測試的一電路之一第一電壓及該電路之一第二電壓,且導出該第一電壓與該第二電壓之間的一差。該除法器經組態以接收該第一電壓與該第二電壓之間的該差,且藉由將(i)該第一電壓與該第二電壓之間的該差除以(ii)施加至該電路之一第一電流與施加至該電路之一第二電流之間的一差,導出該電路之一電阻。該第一電壓對應於該第一電流,且該第二電壓對應於該第二電流。A test system includes a subtractor and a divider. The subtractor is configured to receive a first voltage of a circuit being tested and a second voltage of the circuit, and derive a difference between the first voltage and the second voltage. The divider is configured to receive the difference between the first voltage and the second voltage, and by dividing (i) the difference between the first voltage and the second voltage by (ii) applying A difference between a first current to the circuit and a second current applied to the circuit leads to a resistance of the circuit. The first voltage corresponds to the first current, and the second voltage corresponds to the second current.

Description

用於測試積體電路及包括該積體電路之電路板之測試系統、方法Test system and method for testing integrated circuit and circuit board including the integrated circuit

本發明係關於一種測試系統及一種用於操作該測試系統之方法,且更明確而言係關於一種用於一積體電路之測試系統及一種用於操作該測試系統的方法。The present invention relates to a test system and a method for operating the test system, and more specifically to a test system for an integrated circuit and a method for operating the test system.

由於積體電路(IC)之效能及複雜度數年來已增加,因此輸入/輸出(I/O)接腳之數目或接腳計數亦已顯著地增加。具有高輸出接腳計數之高密度裝置可具有可要求輸出測試之大量輸出接腳。需要具有一種測試系統以驗證IC之功能性。As the performance and complexity of integrated circuits (ICs) have increased over the years, the number of input / output (I / O) pins or the pin counts have also increased significantly. High density devices with high output pin counts can have a large number of output pins that can require output testing. A test system is needed to verify the functionality of the IC.

根據本發明之一些實施例,一種測試系統包括:(a)一減法器,其經組態以接收正測試之一電路之一第一電壓及該電路之一第二電壓且導出該第一電壓與該第二電壓之間的一差;及(b)一除法器,其經組態以接收該第一電壓與該第二電壓之間的該差且藉由將(i)該第一電壓與該第二電壓之間的該差除以(ii)施加至該電路之一第一電流與施加至該電路之一第二電流之間的一差,導出該電路之一電阻,其中該第一電壓對應於該第一電流,且該第二電壓對應於該第二電流。 根據本發明之一些實施例,一種測試一IC之方法包括:(a)將一第一電流施加至該IC之一接腳;(b) 量測該IC之該接腳處的一第一電壓;(c)將一第二電流施加至該IC之該接腳;(d)量測該IC之該接腳處的一第二電壓;及(e)將(i)該第一電壓與該第二電壓之間的一差除以(ii)該第一電流與該第二電流之間的一差以導出該IC之一電阻,其中該第二電壓與該第二電流之一比率給出為該第一電壓與該第一電流之一比率乘以β,且β係在約0.98至約1之一範圍內。 根據本發明之一些實施例,一種測試一電路板之方法包括:(a)施加一第一電流至該電路板之一導電襯墊,該導電襯墊連接至一IC之一接腳;(b)量測該電路板之該導電襯墊處的一第一電壓;(c)施加一第二電流至該電路板之該導電襯墊;(d)量測該電路板之該導電襯墊處的一第二電壓;(e)將(i)該第一電壓與該第二電壓之間的一差除以(ii)該第一電流與該第二電流之間的一差以導出一第一電阻(R esd+R pr);及(f)藉由自該第一電阻(R esd+R pr)減去一第三電阻(R esd)導出一第二電阻(R pr),該第三電阻(R esd)係與電連接至該IC之該接腳的一電路相關聯。 According to some embodiments of the present invention, a test system includes: (a) a subtractor configured to receive a first voltage of a circuit being tested and a second voltage of the circuit and derive the first voltage A difference from the second voltage; and (b) a divider configured to receive the difference between the first voltage and the second voltage and by (i) the first voltage The difference from the second voltage is divided by (ii) a difference between a first current applied to the circuit and a second current applied to the circuit to derive a resistance of the circuit, where the first A voltage corresponds to the first current, and the second voltage corresponds to the second current. According to some embodiments of the present invention, a method for testing an IC includes: (a) applying a first current to a pin of the IC; (b) measuring a first voltage at the pin of the IC (C) applying a second current to the pin of the IC; (d) measuring a second voltage at the pin of the IC; and (e) applying (i) the first voltage to the pin A difference between the second voltages is divided by (ii) a difference between the first current and the second current to derive a resistance of the IC, where a ratio of the second voltage to a second current is given The ratio of the first voltage to the first current is multiplied by β, and β is in a range of about 0.98 to about 1. According to some embodiments of the present invention, a method for testing a circuit board includes: (a) applying a first current to a conductive pad of the circuit board, the conductive pad being connected to a pin of an IC; (b) ) Measure a first voltage at the conductive pad of the circuit board; (c) Apply a second current to the conductive pad of the circuit board; (d) Measure the conductive pad of the circuit board (E) divide (i) a difference between the first voltage and the second voltage by (ii) a difference between the first current and the second current to derive a first a resistor (R esd + R pr); and (f) from the first by resistor (R esd + R pr) minus a third resistor (R esd) deriving a second resistor (R pr), said first Three resistors ( Resd ) are associated with a circuit electrically connected to the pins of the IC.

本發明之實例實施例之態樣、特徵及優點結合附圖關於以下描述將得到更好地理解。對於熟習此項技術者而言應為顯而易見的是,本文中提供之本發明的所描述實施例為說明性且非限制性的,從而藉助於實例來呈現。揭示於本說明書中之所有特徵可藉由起到相同或類似用途之替代性特徵來替換,除非以其他方式明確陳述。因此,其修改之大量其他實施例預期為係在本發明之如本文中所界定之範疇及其等效物的範疇內。另外,絕對性術語(諸如「必須」及「必須不」)關於一些實例實施例的使用並非意謂限制本發明之範疇,此係由於本文中揭示之實施例係藉助於實例進行。 此外,如本說明書及隨附申請專利範圍中所使用,單數量詞形式「一」及「該」包括單數及複數參考,除非其使用之上下文以其他方式清楚地指示。因此,例如,對「一」輸入之參考包括多個輸入以及單一輸入,對「一輸出」之參考包括一單一輸出以及多個輸出及類似者。 圖1說明根據本發明之一些實施例的測試系統1之方塊圖。測試系統1包括待測試之電路10、電流供應器11及測試模組12。 電流供應器11連接至待測試之電路10從而將電流施加至該電路,且因此獲得對應於所施加電流之電壓。在一個實施例中,電流供應器11為恆定電流源。 測試模組12經組態以接收對應於所施加電流的電壓。測試模組12包括緩衝器121、減法器122及除法器123。緩衝器121經組態以延遲接收自緩衝器121之輸入的信號且將經延遲之信號傳送至減法器122。減法器122具有兩個輸入以接收兩個信號且執行對接收自兩個輸入之信號的減法。減法器122連接至除法器123以提供兩個信號之間的差至除法器123。在一些實施例中,緩衝器121可整合至減法器122中。測試模組12之其他組件可經組合或整合在一起,或可經進一步再分。 在操作期間,第一電流I m1施加至待測試之電路10以獲得第一電壓V m1。第一電壓V m1接著發送至測試模組12之緩衝器121。第二不同電流I m2施加至待測試之電路10以獲得第二電壓V m2,且第二電壓V m2發送至測試模組12之減法器122。在一些實施例中,I m1及I m2為大體上連續的。即,當滿足 時,I m2=I m1+ΔI,其中β係在約0.98與1之間的範圍內,且ΔI係在約50 μA與約500 μA之間的範圍內(例如,電流之間的表達為絕對值之差)。減法器122經組態以自第一電壓V m1減去第二電壓V m2以導出第一電壓V m1與第二電壓V m2之間的差。第一電壓V m1與第二電壓V m2之間的差接著藉由除法器123除以第一電流I m1與第二電流I m2之間的差以導出待測試之電路10的總電阻RL。 待測試之電路10是否正常地起作用可藉由比較待測試之電路10的總電阻RL與預定參考電阻值來檢查。若待測試之電路10之總電阻RL大體上等於參考電阻值,則電路10判定為正常的;否則可對電路10進行進一步檢查或檢驗。替代地或組合地,電路10之總電阻RL可與臨限參考電阻值相比較,且若電阻RL係在0與臨限值之間,則此可指示電路10為正常的。如圖1中所展示,比較器124經包括以執行電路10之總電阻RL與參考值之比較,且可包括顯示單元以提供比較之結果及電路10正常(或不正常)的視覺指示。儘管與測試模組12分離地展示,但比較器124可整合至測試模組12中。在一些實施例中,測試模組12之組件可使用合適電路板以硬體實施。 圖2說明根據本發明之一些實施例的測試系統2之方塊圖。測試系統2包括待測試之IC 20、電流供應器21、電壓計(voltage meter、voltmeter) 22及測試模組23。 IC 20包括內部電路20A及保護電路20B。在一些實施例中,內部電路20A可為數位電路、類比電路、射頻(RF)電路、微機電系統(MEMS)、混合式信號電路或其組合。保護電路20B包括多個二極體。在一些實施例中,保護電路20B可進一步包括被動組件(諸如電流限制電阻器)、主動組件(諸如金屬氧化物半導體場效電晶體(MOSFET)或雙極接面電晶體(BJT))或其一組合。IC 20進一步包括多個接腳201、202及203。在一些實施例中,接腳201電連接至外部電源,且接腳203電連接外部接地源。 電流供應器21連接至IC 20之接腳202用於將電流供應至該接腳,且對應於所施加電流之電壓藉由電壓計22來量測。 在操作期間,第一電流I m1施加至IC 20之接腳202,且第一電壓V m1藉由電壓計22量測。第一電壓V m1與第一電流I m1之間的關係展示為以下等式,其中V esd1為二極體20B1的在第一電流I m1施加至IC 20之接腳202時所量測的電壓,且R esd為保護電路20B之總電阻: (1) 若第一電壓V m1為0,則電連接至IC 20之接腳202的保護電路20B判定為短路連接。若第一電壓V m1大體上等於電流供應器21之(非零)保護電壓,則電連接至IC 20之接腳202的保護電路20B判定為斷開。若第一電壓V m1並非等於0或電流供應器21之保護電壓,則第二電流I m2接著施加至IC 20之接腳202,且第二電壓V m2由電壓計22來量測。第二電壓V m2與第二電流I m2之間的關係展示為以下等式,其中V esd2為二極體20B1的在第二電流I m2施加至該IC 20之接腳202時量測的電壓: (2) 以下等式可藉由自等式(1)減去等式(2)來導出: (3) 二極體20B1之電壓V esd與施加至二極體20B1之電流I m之間的關係展示為以下等式,其中I s為反向偏壓飽和電流,V T為熱電壓,且n為理想性因數: (4) 在一些實施例中,當施加約1 mA之電流I m時,二極體20B1之電壓V esd為約0.53 V (對於矽二極體)或約0.18 V (對於鍺二極體)。替代地,當施加約100 mA之電流I m時,二極體20B1之電壓V esd為約0.65 V (對於矽二極體)或約0.30 V (對於鍺二極體)。基於以上內容,歸因於二極體20B1之本質,即使電流I m改變相對大程度,二極體20B1之電壓V esd仍不顯著地改變。藉由選擇接近於第一電流I m1之第二電流I m2,第二電壓V esd2將大體上等於第一電壓V esd1。在一些實施例中,第一電流I m1與第二電流I m2之間的差大於約300 μA。在其他實施例中,第一電流I m1與第一電壓V m1之比率大於約1。在其他實施例中,第二電流I m2與第二電壓V m2的比率大於約1。因此,等式(3)可簡化如下: (5) 測試模組23連接至電流供應器21及電壓計22以接收所施加電流及所量測電壓。保護電路20B之總電阻R esd可藉由測試模組23基於所施加之第一電流I m1及第二電流I m2以及所量測之第一電壓V m1及第二電流V m2來判定。舉例而言,若電阻R esd藉由測試模組23判定為0,此可指示電連接至IC 20之接腳202的保護電路20B經短路連接。在其他實施例中,若第一電壓為V m1為0,此亦可指示保護電路20B經短路連接。對於另一實例,若電阻R esd高於臨限參考值,則此可指示電連接至該IC 20之接腳202的保護電路20B經斷開。在其他實施例中,若第一電壓V m1高於臨限值,則此可指示保護電路20B經斷開。作為另一實例,若電阻R esd係在0與臨限值之間,則此可指示電連接至IC之接腳202的保護電路20B良好或正常。在一些實施例中,測試模組23可類似於展示於圖1中之測試模組12地實施。在一些實施例中,電壓計22可整合至模組23中。測試系統2之其他組件可組合或整合在一起,或可經進一步再分。 在一些實施例中,IC可藉由在不向IC供電情況下量測IC之接腳處的電壓來測試,其中一旦所量測電壓係在0與臨限值之間,IC便被視為良好或正常的。然而,此測試方法可具有相對大之容許度。藉由保護電路20B之所量測電壓及總電阻R esd兩者判定IC 20之接腳202之功能性的展示於圖2中之測試系統2獲得較高準確性及可靠性。 在一些實施例中,IC經供電並藉由在線測試(in-circuit-test;ICT)裝備測試,且至少兩個測試端子或襯墊在ICT裝備上指定以供測試。可指定僅一個接腳、一個端子或一個襯墊用於測試的展示於圖2中之測試系統2可節省成本及時間。此外,與不可量測R esd之值的ICT裝備相比較,展示於圖2中之測試系統2獲得較高準確性及精度。 圖3說明根據本發明之一些實施例的測試系統3之方塊圖。測試系統3包括待測試之IC 30、電流供應器31、電壓計32、測試模組33及載體34。 載體34由(例如)印刷電路板(PCB)形成,諸如由紙類銅箔層合物、複合銅箔層合物或聚合物浸漬玻璃纖維類銅箔層合物形成。載體34可具有電互連件(圖中未示),諸如再分佈層(RDL)。 IC 30位於載體34上。IC 30包括內部電路30A及保護電路30B。在一些實施例中,內部電路30A可為數位電路、類比電路、RF電路、MEMS、混合式信號電路或其組合。保護電路30B包括多個二極體。在一些實施例中,保護電路30B可進一步包括被動組件(諸如電阻器)、主動組件(諸如MOSFET或BJT)或其組合。IC 30進一步包括電連接至載體34上之導電襯墊的多個接腳301、302及303。在一些實施例中,IC 30之接腳302與載體34之導電襯墊342之間的等效阻抗34A(包括接合於載體上之組件)可表示為藉由如展示於圖3中之電阻器R pr、電容器C pr及電感器L pr形成的電路。 電流供應器31連接至載體34之導電襯墊342用於施加電流至該導電襯墊,且對應於所施加電流之電壓藉由電壓計32來量測。 在操作期間,第一電流I m1經由導電襯墊342施加至IC 30之接腳302,且第一電壓V m1藉由電壓計32來量測。電流供應器31可施加直流電(DC),使得電容器C pr及電感器L pr之效應可被忽略。因此,第一電壓V m1與第一電流I m1之間的關係展示為以下等式,其中V esd1為二極體30B1的在第一電流I m1施加至載體34之導電襯墊342時量測的電壓,且R esd為保護電路30B之總電阻: (6) 若所量測第一電壓V m1為0,則等效阻抗34A或保護電路30B或兩者可判定為經短路連接。若所量測之第一電壓V m1大體上等於電流供應器31之保護電壓,則等效阻抗34A或保護電路30B或兩者可判定為斷開。若所量測之第一電壓V m1並非等於0或電流供應器31之保護電壓,則第二電流I m2接著施加至載體34之導電襯墊342,且第二電壓V m2藉由電壓計32來量測。第二電壓V m2與第二電流I m2之間的關係展示為以下等式,其中V esd2為二極體30B1在第二電流I m2下的電壓: (7) 以下等式可藉由自等式(7)減去等式(6)來導出: (8) 二極體30B1之電壓V esd與施加至二極體30B1之電流I m之間的關係藉由上文展示之等式(4)表示。在一些實施例中,當施加約1 mA之電流I m時,二極體30B1之電壓V esd為約0.53 V (對於矽二極體)或約0.18 V (對於鍺二極體)。替代地,當施加約100 mA之電流I m時,二極體30B1之電壓V esd為約0.65 V (對於矽二極體)或約0.30 V (對於鍺二極體)。基於以上內容,歸因於二極體30B1之本質,即使電流I m改變相對大程度,二極體30B1之電壓V esd仍不顯著地改變。藉由選擇接近第一電流I m1之第二電流I m2,第二電壓V esd2將大體上等於第一電壓V esd1。在一些實施例中,第一電流I m1與第二電流I m2之間的差大於約300 μA。在其他實施例中,第一電流I m1與第一電壓V m1之比率大於約1。在其他實施例中,第二電流I m2與第二電壓V m2的比率大於約1。因此,等式(8)可簡化如下: (9) 測試模組33連接至電流供應器31及電壓計32以接收所施加電流及所量測電壓。保護電路30B之電阻R esd與載體34的導電襯墊342與接腳302之間的電阻R pr之總和可藉由測試模組23基於所施加之第一電流I m1及第二電流I m2以及所量測之第一電壓V m1及第二電壓V m2來計算。由於保護電路30B之電阻R esd可經由展示於圖2中之測試系統2計算,因此電阻R pr可藉由自電阻R esd與電阻R pr之總和減去電阻R esd來獲得。若電阻R pr大體上等於載體34之電阻的預定參考值,則載體34上之組件(導電襯墊342與接腳302之間)可判定為良好或正常的;否則載體34上之組件可判定為未通過測試或待進一步測試或替換。在一些實施例中,測試模組33可類似於展示於圖1中之測試模組12地實施。在一些實施例中,電壓計32可整合至模組33中。測試系統3之其他組件可組合或整合在一起,或可經進一步再分。 在一些實施例中,載體34上之組件是否正常地起作用藉由在不計算載體34之電阻R pr的情況下檢驗所量測電壓判定。與此等實施例相比較,展示於圖3中之比較載體34之電阻R pr與參考電阻的測試系統3獲得較高準確性及可靠性。此外,可無必要的是藉由使用展示於圖3中之測試系統3接通IC 30或為該IC供電用於功能性檢查,該測試系統可減小用於測試載體34的時間及成本。 在一些實施例中,載體34之電阻R pr可藉由ICT裝備來量測,該ICT裝備指定至載體34之兩個節點的連接以進行量測。與使用ICT相比,圖3中之測試系統3可藉由連接至僅一個節點而獲得載體34的電阻R pr,其可減小用於測試載體34的時間及成本。 圖4說明根據本發明之一些實施例的用於測試IC之操作的流程圖。 參看操作S41,將第一電流I m1施加至待測試之IC的接腳。在一些實施例中,第一電流I m1可由電流供應器施加。 參考操作S42,在IC之接腳處量測對應於所施加第一電流I m1的第一電壓V m1。在一些實施例中,第一電壓V m1可藉由電壓計來量測。 參看操作S43,檢查第一電壓V m1以判定第一電壓V m1等於0抑或電流供應器的保護電壓。若第一電壓V m1等於0,則電連接至IC之接腳的電路判定為經短路連接。若第一電壓V m1大體上等於電流供應器之保護電壓,則電連接至IC之接腳的電路判定為斷開。 參考操作S44,若第一電壓V m1並非等於0或電流供應器之保護電壓,則將第二電流I m2施加至IC之接腳以獲得對應於所施加第二電流I m2的第二電壓V m2。在一些實施例中,第一電流I m1與第二電流I m2之間的差大於約300 μA。在其他實施例中,第一電流I m1與第一電壓V m1之比率大於約1。在其他實施例中,第二電流I m2與第二電壓V m2之比率大於約1。 參考操作S45,IC之保護電路的電阻R esd藉由上文展示之等式(5)來計算。 參考操作S46,比較電阻R esd與預定臨限值以檢查IC之接腳的功能性。若電阻R esd判定為0,則電連接至IC之接腳的電路判定為經短路連接,且若電阻R esd高於臨限值,則電連接至IC之接腳的電路判定為斷開;否則電連接至之IC之接腳的電路判定為正常。在其他實施例中,若第一電壓V m1為0,則此亦可指示電連接至IC之接腳的電路經短路連接,且若第一電壓V m1高於臨限值,則此可指示電路經斷開。 在一些實施例中,IC之接腳是否正常地起作用藉由在不計算保護電路之總電阻的情況下檢驗所量測電壓來判定。與此等實施例相比較,藉由所量測電壓及保護電路之電阻R esd兩者判定IC之接腳之功能性的展示於圖4中之測試操作提供較高準確性及可靠性。此外,可能不必要的是接通IC或對IC供電用於功能性檢查,其可減小用於測試IC之時間及成本。 圖5說明根據本發明之一些實施例的用於測試上面定位有IC之電路板(或其他載體)之操作的流程圖。 參考操作S51,將第一電流I m1施加至連接至IC之接腳之電路板的導電襯墊。在一些實施例中,第一電流I m1可由電流供應器施加。對應於所施加第一電流I m1的第一電壓V m1在電路板之導電襯墊處量測。在一些實施例中,第一電壓V m1可由電壓計來量測。 參考操作S52,將第二電流I m2施加至電路板之導電襯墊。對應於所施加第二電流I m2的第二電壓V m2在電路板之導電襯墊處量測。 參考操作S53,電路板的在導電襯墊與IC之接腳之間的總電阻R pr及IC之保護電路的電阻R esd藉由以上所展示之等式(9)來計算。由於IC之保護電路之電阻R esd可藉由展示於圖4中之操作計算,因此電阻R pr可藉由自電阻R esd與電阻R pr之總和減去電阻R esd來獲得。 參考操作S54,比較電阻R pr與電路板之電阻的預定參考值。若電阻R pr大體上等於電路板之電阻的參考值,則電路板上之組件判定為良好或正常的;否則,電路板上之組件判定為未通過測試或將進一步進行測試或替換。 在一些實施例中,電路板之導電襯墊是否正常地起作用藉由在不計算電路板之總電阻情況下檢驗所量測電壓來判定。與此等實施例相比較,比較電路板之所計算電阻與參考電阻的展示於圖5中之測試操作獲得更高準確性及可靠性。此外,可不必要的是藉由使用展示於圖5中之測試操作接通IC或對IC供電用於功能性測試,其可減小用於測試電路板的時間及成本。 在一些實施例中,電路板之電阻R pr可藉由ICT裝備來量測,該ICT裝備指定至電路板之兩個節點的連接以進行量測。與使用ICT相比,圖5中之測試操作可藉由連接至僅一個節點而獲得電路板的電阻R pr,其可減小用於測試電路板的時間及成本。 如本文中所使用,術語「大體上」、「大體」、「大約」及「約」用以描述及慮及小變化。當結合事件或情形使用時,術語「大體上」、「大體」、「大約」及「約」可指事件或情形精確發生之情況以及事件或情形近似發生之情況。舉例而言,當結合數值使用時,術語可涵蓋小於或等於彼數值之±10%的變化範圍,諸如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%或小於或等於±0.05%的變化範圍。舉例而言,當比較第一數值與第二參考數值時,若第一數值位於小於或等於第二數值之±10%諸如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%或小於或等於±0.05%的變化範圍內,則第一數值可被認為是「大體上」與第二數值相等或相同。 另外,有時在本文中按範圍格式呈現量、比率及其他數值。可理解,此類範圍格式係為了便利及簡潔,且應靈活地理解為不僅包括明確地指定為範圍限值之數值,而且包括涵蓋於該範圍內之所有個別數值或子範圍,如同明確地指定每一數值及子範圍一般。 儘管已參考本發明之特定實施例描述並說明了本發明,但此等描述及說明並不限制本發明。熟習此項技術者可清楚地理解,可進行各種改變,且可在實施例內取代等效元件而不脫離如由所附申請專利範圍所界定之本發明之真實精神及範疇。說明可不必按比例繪製。歸因於製造製程等等中的變數,本發明中之藝術再現與實際設備之間可存在區別。可存在並未特定說明的本發明之其他實施例。應將本說明書及圖式視為說明性而非約束性的。可作出修改,以使特定情形、材料、物質組成、方法或製程適應於本發明之目標、精神及範疇。所有此類修改均意欲屬於此處所附之申請專利範圍的範疇內。儘管已參看按特定次序執行之特定操作描述本文中所揭示的方法,但可理解,在不脫離本發明之教示的情況下,可組合、再分,或重新定序此等操作以形成等效方法。因此,除非在本文中特定指示,否則操作之次序及分組並非本發明之限制。 Aspects, features, and advantages of example embodiments of the present invention will be better understood with reference to the following description in conjunction with the accompanying drawings. It should be apparent to those skilled in the art that the described embodiments of the invention provided herein are illustrative and non-limiting, and are presented by way of example. All features disclosed in this specification may be replaced by alternative features serving the same or similar purpose, unless expressly stated otherwise. Therefore, a number of other embodiments of its modifications are intended to be within the scope of the invention as defined herein and the equivalents thereof. In addition, the use of absolute terms (such as "must" and "must not") with respect to some example embodiments is not meant to limit the scope of the invention, as the embodiments disclosed herein are performed by way of example. In addition, as used in this specification and the scope of the accompanying patent application, the singular forms "a" and "the" include singular and plural references unless the context of their use clearly indicates otherwise. Thus, for example, a reference to "one" input includes multiple inputs and a single input, and a reference to "one output" includes a single output and multiple outputs and the like. FIG. 1 illustrates a block diagram of a test system 1 according to some embodiments of the invention. The test system 1 includes a circuit 10 to be tested, a current supplier 11 and a test module 12. The current supplier 11 is connected to the circuit 10 to be tested so as to apply a current to the circuit, and thus obtains a voltage corresponding to the applied current. In one embodiment, the current supply 11 is a constant current source. The test module 12 is configured to receive a voltage corresponding to an applied current. The test module 12 includes a buffer 121, a subtracter 122 and a divider 123. The buffer 121 is configured to delay the input signal received from the buffer 121 and transmit the delayed signal to the subtractor 122. The subtracter 122 has two inputs to receive two signals and performs subtraction of signals received from the two inputs. The subtracter 122 is connected to the divider 123 to provide a difference between the two signals to the divider 123. In some embodiments, the buffer 121 may be integrated into the subtractor 122. Other components of the test module 12 may be combined or integrated together, or may be further subdivided. During operation, a first current I m1 is applied to the circuit 10 to be tested to obtain a first voltage V m1 . The first voltage V m1 is then sent to the buffer 121 of the test module 12. A second different current I m2 is applied to the circuit 10 to be tested to obtain a second voltage V m2 , and the second voltage V m2 is sent to the subtractor 122 of the test module 12. In some embodiments, I m1 and I m2 are substantially continuous. That is, when satisfied I m2 = I m1 + ΔI, where β is in the range between about 0.98 and 1, and ΔI is in the range between about 50 μA and about 500 μA (for example, the expression between currents is absolute Value difference). The subtracter 122 is configured from the first to the second voltage minus the voltage V m1 V m2 to derive a difference between the first voltage and the second voltage V m1 V m2. The difference between the first voltage V m1 and the second voltage V m2 is then divided by the divider 123 by the difference between the first current I m1 and the second current I m2 to derive the total resistance RL of the circuit 10 to be tested. Whether the circuit 10 to be tested works normally can be checked by comparing the total resistance RL of the circuit 10 to be tested with a predetermined reference resistance value. If the total resistance RL of the circuit 10 to be tested is substantially equal to the reference resistance value, the circuit 10 is determined to be normal; otherwise, the circuit 10 may be further inspected or checked. Alternatively or in combination, the total resistance RL of the circuit 10 may be compared with a threshold reference resistance value, and if the resistance RL is between 0 and a threshold value, this may indicate that the circuit 10 is normal. As shown in FIG. 1, the comparator 124 is included to perform a comparison of the total resistance RL of the circuit 10 with a reference value, and may include a display unit to provide a comparison result and a visual indication that the circuit 10 is normal (or abnormal). Although shown separately from the test module 12, the comparator 124 may be integrated into the test module 12. In some embodiments, the components of the test module 12 may be implemented in hardware using a suitable circuit board. FIG. 2 illustrates a block diagram of a test system 2 according to some embodiments of the invention. The test system 2 includes an IC 20 to be tested, a current supply 21, a voltage meter (voltmeter) 22, and a test module 23. The IC 20 includes an internal circuit 20A and a protection circuit 20B. In some embodiments, the internal circuit 20A may be a digital circuit, an analog circuit, a radio frequency (RF) circuit, a microelectromechanical system (MEMS), a mixed signal circuit, or a combination thereof. The protection circuit 20B includes a plurality of diodes. In some embodiments, the protection circuit 20B may further include a passive component such as a current limiting resistor, an active component such as a metal oxide semiconductor field effect transistor (MOSFET) or a bipolar junction transistor (BJT), or the like A combination. The IC 20 further includes a plurality of pins 201, 202, and 203. In some embodiments, the pin 201 is electrically connected to an external power source, and the pin 203 is electrically connected to an external ground source. The current supply 21 is connected to a pin 202 of the IC 20 for supplying a current to the pin, and a voltage corresponding to the applied current is measured by a voltmeter 22. During operation, the first current I m1 is applied to the pin 202 of the IC 20, and the first voltage V m1 is measured by the voltmeter 22. The relationship between the first voltage V m1 and the first current I m1 is shown as the following equation, where V esd1 is the voltage measured by the diode 20B1 when the first current I m1 is applied to the pin 202 of the IC 20 , And Resd is the total resistance of the protection circuit 20B: (1) If the first voltage V m1 is 0, the protection circuit 20B electrically connected to the pin 202 of the IC 20 is determined as a short-circuit connection. If the first voltage V m1 is substantially equal to the (non-zero) protection voltage of the current supplier 21, the protection circuit 20B electrically connected to the pin 202 of the IC 20 is determined to be open. If the first voltage V m1 is not equal to 0 or the protection voltage of the current supply 21, the second current I m2 is then applied to the pin 202 of the IC 20, and the second voltage V m2 is measured by the voltmeter 22. The relationship between the second voltage V m2 and the second current I m2 is shown as the following equation, where V esd2 is the voltage measured by the diode 20B1 when the second current I m2 is applied to the pin 202 of the IC 20 : (2) The following equation can be derived by subtracting equation (2) from equation (1): (3) The relationship between the voltage V esd of the diode 20B1 and the current I m applied to the diode 20B1 is shown as the following equation, where I s is the reverse bias saturation current, V T is the thermal voltage, and n is the ideality factor: (4) In some embodiments, when applied for about 1 mA of current I m, diode 20B1 of the voltage V esd of about 0.53 V (for a silicon diode), or about 0.18 V (for the germanium diode) . Alternatively, when a current I m of about 100 mA is applied, the voltage V esd of the diode 20B1 is about 0.65 V (for a silicon diode) or about 0.30 V (for a germanium diode). Based on the above, due to the nature of the diode 20B1, the voltage V esd of the diode 20B1 does not change significantly even if the current I m changes to a relatively large extent. By selecting a second current I m2 that is close to the first current I m1 , the second voltage V esd2 will be substantially equal to the first voltage V esd1 . In some embodiments, the difference between the first current I m1 and the second current I m2 is greater than about 300 μA. In other embodiments, the ratio of the first current I m1 to the first voltage V m1 is greater than about 1. In other embodiments, the ratio of the second current I m2 to the second voltage V m2 is greater than about 1. Therefore, equation (3) can be simplified as follows: (5) The test module 23 is connected to the current supply 21 and the voltmeter 22 to receive the applied current and the measured voltage. The total resistance Resd of the protection circuit 20B can be determined by the test module 23 based on the applied first current I m1 and the second current I m2 and the measured first voltage V m1 and the second current V m2 . For example, if the resistance Resd is determined to be 0 by the test module 23, this may indicate that the protection circuit 20B electrically connected to the pin 202 of the IC 20 is connected by a short circuit. In other embodiments, if the first voltage V m1 is 0, this may also indicate that the protection circuit 20B is connected via a short circuit. For another example, if the resistance Resd is higher than the threshold reference value, this may indicate that the protection circuit 20B electrically connected to the pin 202 of the IC 20 is disconnected. In other embodiments, if the first voltage V m1 is higher than a threshold value, this may indicate that the protection circuit 20B is turned off. As another example, if the resistance Resd is between 0 and a threshold value, this may indicate that the protection circuit 20B electrically connected to the pin 202 of the IC is good or normal. In some embodiments, the test module 23 may be implemented similarly to the test module 12 shown in FIG. 1. In some embodiments, the voltmeter 22 may be integrated into the module 23. Other components of the test system 2 may be combined or integrated together, or may be further subdivided. In some embodiments, the IC can be tested by measuring the voltage at the pins of the IC without supplying power to the IC. Once the measured voltage is between 0 and a threshold value, the IC is considered as Good or normal. However, this test method can have a relatively large tolerance. The functionality of the pin 202 of the IC 20 is determined by both the measured voltage of the protection circuit 20B and the total resistance Resd . The test system 2 in FIG. 2 is shown to obtain higher accuracy and reliability. In some embodiments, the IC is powered and tested by in-circuit-test (ICT) equipment, and at least two test terminals or pads are designated on the ICT equipment for testing. The test system 2 shown in FIG. 2 which can specify only one pin, one terminal or one pad for testing can save cost and time. In addition, compared with non-measured values of R esd ICT equipment, the test system shown in FIG. 22 to obtain the high accuracy and precision. FIG. 3 illustrates a block diagram of a test system 3 according to some embodiments of the invention. The test system 3 includes an IC 30 to be tested, a current supply 31, a voltmeter 32, a test module 33, and a carrier 34. The carrier 34 is formed of, for example, a printed circuit board (PCB), such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. The carrier 34 may have an electrical interconnect (not shown), such as a redistribution layer (RDL). The IC 30 is located on a carrier 34. The IC 30 includes an internal circuit 30A and a protection circuit 30B. In some embodiments, the internal circuit 30A may be a digital circuit, an analog circuit, an RF circuit, a MEMS, a mixed signal circuit, or a combination thereof. The protection circuit 30B includes a plurality of diodes. In some embodiments, the protection circuit 30B may further include a passive component (such as a resistor), an active component (such as a MOSFET or BJT), or a combination thereof. The IC 30 further includes a plurality of pins 301, 302, and 303 electrically connected to a conductive pad on the carrier 34. In some embodiments, the equivalent impedance 34A (including components bonded to the carrier) between the pin 302 of the IC 30 and the conductive pad 342 of the carrier 34 can be expressed as a resistor as shown in FIG. A circuit formed by R pr , capacitor C pr and inductor L pr . The current supply 31 is connected to the conductive pad 342 of the carrier 34 for applying a current to the conductive pad, and a voltage corresponding to the applied current is measured by a voltmeter 32. During operation, the first current I m1 is applied to the pin 302 of the IC 30 via the conductive pad 342, and the first voltage V m1 is measured by the voltmeter 32. The current supplier 31 can apply direct current (DC), so that the effects of the capacitor C pr and the inductor L pr can be ignored. Therefore, the relationship between the first voltage V m1 and the first current I m1 is shown as the following equation, where V esd1 is a diode 30B1 measured when the first current I m1 is applied to the conductive pad 342 of the carrier 34 Voltage, and Resd is the total resistance of the protection circuit 30B: (6) If the measured first voltage V m1 is 0, the equivalent impedance 34A or the protection circuit 30B or both can be determined to be connected via a short circuit. If the measured first voltage V m1 is substantially equal to the protection voltage of the current supplier 31, the equivalent impedance 34A or the protection circuit 30B or both can be determined as disconnected. If the measured first voltage V m1 is not equal to 0 or the protection voltage of the current supplier 31, the second current I m2 is then applied to the conductive pad 342 of the carrier 34, and the second voltage V m2 is passed through the voltmeter 32. To measure. The relationship between the second voltage V m2 and the second current I m2 is shown as the following equation, where V esd2 is the voltage of the diode 30B1 at the second current I m2 : (7) The following equation can be derived by subtracting equation (6) from equation (7): (8) The relationship between the voltage V esd of the diode 30B1 and the current I m applied to the diode 30B1 is expressed by the equation (4) shown above. In some embodiments, when a current I m of about 1 mA is applied, the voltage V esd of the diode 30B1 is about 0.53 V (for a silicon diode) or about 0.18 V (for a germanium diode). Alternatively, when a current I m of about 100 mA is applied, the voltage V esd of the diode 30B1 is about 0.65 V (for a silicon diode) or about 0.30 V (for a germanium diode). Based on the above, due to the nature of the diode 30B1, the voltage V esd of the diode 30B1 does not change significantly even if the current I m changes to a relatively large extent. By selecting a second current I m2 that is close to the first current I m1 , the second voltage V esd2 will be substantially equal to the first voltage V esd1 . In some embodiments, the difference between the first current I m1 and the second current I m2 is greater than about 300 μA. In other embodiments, the ratio of the first current I m1 to the first voltage V m1 is greater than about 1. In other embodiments, the ratio of the second current I m2 to the second voltage V m2 is greater than about 1. Therefore, equation (8) can be simplified as follows: (9) The test module 33 is connected to the current supplier 31 and the voltmeter 32 to receive the applied current and the measured voltage. The sum of the resistance R esd of the protection circuit 30B and the resistance R pr between the conductive pad 342 of the carrier 34 and the pin 302 can be determined by the test module 23 based on the applied first current I m1 and the second current I m2 and The measured first voltage V m1 and second voltage V m2 are calculated. Since the resistance R esd of the protection circuit 30B can be calculated by the test system 2 shown in FIG. 2, the resistance R pr can be obtained by subtracting the resistance R esd from the sum of the resistance R esd and the resistance R pr . If the resistance R pr is substantially equal to the predetermined reference value of the resistance of the carrier 34, the component on the carrier 34 (between the conductive pad 342 and the pin 302) can be judged as good or normal; otherwise, the component on the carrier 34 can be judged Is failed or pending further testing or replacement. In some embodiments, the test module 33 may be implemented similarly to the test module 12 shown in FIG. 1. In some embodiments, the voltmeter 32 may be integrated into the module 33. Other components of the test system 3 may be combined or integrated together, or may be further subdivided. In some embodiments, whether the components on the carrier 34 are functioning normally is determined by checking the measured voltage without calculating the resistance R pr of the carrier 34. Compared with these embodiments, the test system 3 of the resistance R pr of the comparison carrier 34 and the reference resistance shown in FIG. 3 obtains higher accuracy and reliability. In addition, it is unnecessary to switch on the IC 30 or power the IC for functional inspection by using the test system 3 shown in FIG. 3, which can reduce the time and cost for testing the carrier 34. In some embodiments, the resistance R pr of the carrier 34 may be measured by an ICT device that specifies the connection to two nodes of the carrier 34 for measurement. Compared with using ICT, the test system 3 in FIG. 3 can obtain the resistance R pr of the carrier 34 by connecting to only one node, which can reduce the time and cost for testing the carrier 34. FIG. 4 illustrates a flowchart of operations for testing an IC according to some embodiments of the invention. Referring to operation S41, a first current I m1 is applied to the pins of the IC to be tested. In some embodiments, the first current I m1 may be applied by a current supplier. Referring to operation S42, a first voltage V m1 corresponding to the applied first current I m1 is measured at the pins of the IC. In some embodiments, the first voltage V m1 can be measured by a voltmeter. Referring to operation S43, the first voltage V m1 is checked to determine whether the first voltage V m1 is equal to 0 or the protection voltage of the current supplier. If the first voltage V m1 is equal to 0, the circuit electrically connected to the pins of the IC is determined to be short-circuited. If the first voltage V m1 is substantially equal to the protection voltage of the current supplier, the circuit electrically connected to the pins of the IC is determined to be open. Referring to operation S44, if the first voltage V m1 is not equal to 0 or the protection voltage of the current supplier, a second current I m2 is applied to the pins of the IC to obtain a second voltage V corresponding to the applied second current I m2 m2 . In some embodiments, the difference between the first current I m1 and the second current I m2 is greater than about 300 μA. In other embodiments, the ratio of the first current I m1 to the first voltage V m1 is greater than about 1. In other embodiments, the ratio of the second current I m2 to the second voltage V m2 is greater than about 1. Referring to operation S45, the resistance R esd of the protection circuit of the IC is calculated by the equation (5) shown above. Referring to operation S46, the resistance Resd is compared with a predetermined threshold to check the functionality of the pins of the IC. If the resistance Resd is determined to be 0, the circuit electrically connected to the pins of the IC is determined to be short-circuited, and if the resistance Resd is higher than a threshold value, the circuit electrically connected to the pins of the IC is determined to be open; Otherwise, the circuit of the pin of the IC to which it is electrically connected is judged to be normal. In other embodiments, if the first voltage V m1 is 0, this may also indicate that the circuit electrically connected to the pins of the IC is connected via a short circuit, and if the first voltage V m1 is higher than a threshold value, this may indicate The circuit was opened. In some embodiments, whether the pins of the IC are functioning properly is determined by checking the measured voltage without calculating the total resistance of the protection circuit. Compared with these embodiments, the functionality of the pins of the IC determined by both the measured voltage and the resistance R esd of the protection circuit is shown in the test operation in FIG. 4 to provide higher accuracy and reliability. In addition, it may be unnecessary to turn on the IC or power the IC for a functional check, which can reduce the time and cost for testing the IC. FIG. 5 illustrates a flowchart of an operation for testing a circuit board (or other carrier) on which an IC is positioned according to some embodiments of the present invention. Referring to operation S51, a first current I m1 is applied to a conductive pad of a circuit board connected to a pin of the IC. In some embodiments, the first current I m1 may be applied by a current supplier. A first voltage V m1 corresponding to the applied first current I m1 is measured at the conductive pad of the circuit board. In some embodiments, the first voltage V m1 can be measured by a voltmeter. Referring to operation S52, a second current I m2 is applied to the conductive pad of the circuit board. A second voltage V m2 corresponding to the applied second current I m2 is measured at the conductive pad of the circuit board. Referring to operation S53, the total resistance R pr between the conductive pad of the circuit board and the pins of the IC and the resistance R esd of the protection circuit of the IC are calculated by the equation (9) shown above. Since the resistance R esd of the protection circuit of the IC can be calculated by the operation shown in FIG. 4, the resistance R pr can be obtained by subtracting the resistance R esd from the sum of the resistance R esd and the resistance R pr . Referring to operation S54, the resistance R pr is compared with a predetermined reference value of the resistance of the circuit board. If the resistance R pr is substantially equal to the reference value of the resistance of the circuit board, the components on the circuit board are judged to be good or normal; otherwise, the components on the circuit board are judged to fail the test or will be further tested or replaced. In some embodiments, whether the conductive pad of the circuit board is functioning properly is determined by checking the measured voltage without calculating the total resistance of the circuit board. Compared with these embodiments, the calculated resistance of the comparison circuit board and the reference resistance are shown in the test operation in FIG. 5 to obtain higher accuracy and reliability. In addition, it may be unnecessary to turn on the IC or power the IC for functional testing by using the test operation shown in FIG. 5, which can reduce the time and cost for testing the circuit board. In some embodiments, the resistance R pr of the circuit board can be measured by ICT equipment, which is assigned to the connection of two nodes of the circuit board for measurement. Compared with using ICT, the test operation in FIG. 5 can obtain the resistance R pr of the circuit board by connecting to only one node, which can reduce the time and cost for testing the circuit board. As used herein, the terms "substantially", "substantially", "about" and "about" are used to describe and take into account small changes. When used in conjunction with an event or situation, the terms "substantially", "substantially", "approximately" and "approximately" may refer to situations in which the event or situation occurs precisely and situations in which the event or situation occurs approximately. For example, when used in conjunction with a numerical value, the term may cover a range of variation that is less than or equal to ± 10% of the value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or A range of variation equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, when comparing the first value with the second reference value, if the first value is less than or equal to ± 10% of the second value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± Within the range of 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%, the first value can be considered as "Substantially" is equal to or the same as the second value. In addition, quantities, ratios, and other numerical values are sometimes presented in a range format herein. Understandably, such a range format is for convenience and brevity, and should be flexibly understood not only to include values explicitly specified as range limits, but also to include all individual values or subranges covered by the range, as explicitly specified Each value and subrange is average. Although the invention has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the invention. Those skilled in the art will clearly understand that various changes can be made, and equivalent elements can be replaced in the embodiments without departing from the true spirit and scope of the present invention as defined by the scope of the attached patent application. Instructions need not be drawn to scale. Due to variables in the manufacturing process and the like, there may be a difference between the artistic reproduction in the present invention and the actual device. There may be other embodiments of the present invention that are not specifically described. This specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, material composition, method, or process to the objectives, spirit, and scope of the present invention. All such modifications are intended to be within the scope of the patentable applications attached hereto. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it is understood that such operations may be combined, subdivided, or reordered to form an equivalent without departing from the teachings of the present invention method. Therefore, unless specifically indicated herein, the order and grouping of operations is not a limitation of the present invention.

1‧‧‧測試系統1‧‧‧test system

2‧‧‧測試系統2‧‧‧test system

3‧‧‧測試系統3‧‧‧test system

10‧‧‧待測試之電路10‧‧‧Circuit to be tested

11‧‧‧電流供應器11‧‧‧Current Supply

12‧‧‧測試模組12‧‧‧test module

20‧‧‧待測試之積體電路(IC)20‧‧‧Integrated Circuit (IC) to be tested

20A‧‧‧內部電路20A‧‧‧Internal circuit

20B‧‧‧保護電路20B‧‧‧Protection circuit

20B1‧‧‧二極體20B1‧‧‧Diode

21‧‧‧電流供應器21‧‧‧Current Supply

22‧‧‧電壓計22‧‧‧Voltmeter

23‧‧‧測試模組23‧‧‧test module

30‧‧‧待測試之積體電路(IC)30‧‧‧Integrated Circuit (IC) to be tested

30A‧‧‧內部電路30A‧‧‧Internal circuit

30B‧‧‧保護電路30B‧‧‧Protection circuit

30B1‧‧‧二極體30B1‧‧‧diode

31‧‧‧電流供應器31‧‧‧Current Supply

32‧‧‧電壓計32‧‧‧Voltmeter

33‧‧‧測試模組33‧‧‧Test Module

34‧‧‧載體34‧‧‧ carrier

34A‧‧‧等效阻抗34A‧‧‧ equivalent impedance

121‧‧‧緩衝器121‧‧‧Buffer

122‧‧‧減法器122‧‧‧Subtractor

123‧‧‧除法器123‧‧‧Divider

124‧‧‧比較器124‧‧‧ Comparator

201‧‧‧接腳201‧‧‧pin

202‧‧‧接腳202‧‧‧pin

203‧‧‧接腳203‧‧‧pin

301‧‧‧接腳301‧‧‧pin

302‧‧‧接腳302‧‧‧pin

303‧‧‧接腳303‧‧‧pin

342‧‧‧導電襯墊342‧‧‧Conductive gasket

Rpr‧‧‧電阻器R pr ‧‧‧ resistor

Cpr‧‧‧電容器C pr ‧‧‧capacitor

Lpr‧‧‧電感器L pr ‧‧‧ inductor

圖1說明根據本發明之一些實施例的測試系統之方塊圖。 圖2說明根據本發明之一些實施例的測試系統。 圖3說明根據本發明之一些實施例的測試系統。 圖4說明根據本發明之一些實施例的用於測試IC之操作的流程圖。 圖5說明根據本發明之一些實施例的用於測試電路板之操作的流程圖。 貫穿圖式及實施方式使用共同參考編號來指示相同或類似組件。本發明結合隨附圖式自以下實施方式將係更顯而易見的。FIG. 1 illustrates a block diagram of a test system according to some embodiments of the invention. Figure 2 illustrates a test system according to some embodiments of the invention. Figure 3 illustrates a test system according to some embodiments of the invention. FIG. 4 illustrates a flowchart of operations for testing an IC according to some embodiments of the invention. FIG. 5 illustrates a flowchart for operation of a test circuit board according to some embodiments of the invention. Common reference numbers are used throughout the drawings and the embodiments to indicate the same or similar components. The invention will be more apparent from the following embodiments in conjunction with the accompanying drawings.

Claims (23)

一種測試系統,其包含:一減法器,其經組態以接收正測試的一電路之一第一電壓及該電路之一第二電壓,且導出該第一電壓與該第二電壓之間的一差;及一除法器,其經組態以接收該第一電壓與該第二電壓之間的該差,且藉由將(i)該第一電壓與該第二電壓之間的該差除以(ii)施加至該電路之一第一電流與施加至該電路之一第二電流之間的一差,導出該電路之一電阻,其中該第一電壓對應於該第一電流,且該第二電壓對應於該第二電流。A test system includes: a subtractor configured to receive a first voltage of a circuit being tested and a second voltage of the circuit, and derive a voltage between the first voltage and the second voltage A difference; and a divider configured to receive the difference between the first voltage and the second voltage, and by (i) the difference between the first voltage and the second voltage Divide by (ii) a difference between a first current applied to the circuit and a second current applied to the circuit to derive a resistance of the circuit, where the first voltage corresponds to the first current, and The second voltage corresponds to the second current. 如請求項1之測試系統,其進一步包含一電流源,該電流源經組態以施加該第一電流及該第二電流,且其中該第一電流與該第二電流之間的一差係在約50μA至約500μA之一範圍內。The test system of claim 1, further comprising a current source configured to apply the first current and the second current, and wherein a difference between the first current and the second current is It is in a range of about 50 μA to about 500 μA. 如請求項1之測試系統,其進一步包含一電流源,該電流源經組態以施加該第一電流及該第二電流,且其中該第二電壓與該第二電流之一比率經給出為該第一電壓與該第一電流之一比率乘以β,且β係在約0.98與約1之一範圍內。The test system of claim 1, further comprising a current source configured to apply the first current and the second current, and wherein a ratio of the second voltage to the second current is given The ratio of one of the first voltage to the first current is multiplied by β, and β is in a range of about 0.98 and about 1. 如請求項1之測試系統,其進一步包含一電流源,該電流源經組態以施加該第一電流及該第二電流至正測試之一積體電路(IC)的一接腳,且其中對應於該第一電流之該第一電壓在該IC之該接腳處獲得,且對應於該第二電流之該第二電壓在該IC之該接腳處獲得。The test system of claim 1, further comprising a current source configured to apply the first current and the second current to a pin of an integrated circuit (IC) being tested, and wherein The first voltage corresponding to the first current is obtained at the pin of the IC, and the second voltage corresponding to the second current is obtained at the pin of the IC. 如請求項1之測試系統,其進一步包含一比較器,該比較器經組態以在該電阻為0之情況下判定該電路經短路連接。The test system of claim 1, further comprising a comparator configured to determine that the circuit is short-circuited when the resistance is zero. 如請求項1之測試系統,其進一步包含一比較器,該比較器經組態以在該電阻高於一臨限值情況下判定該電路經斷開。The test system of claim 1, further comprising a comparator configured to determine that the circuit is disconnected if the resistance is above a threshold value. 如請求項1之測試系統,其進一步包含一比較器,該比較器經組態以在該電阻大體上等於一參考值情況下判定該電路為正常的。The test system of claim 1, further comprising a comparator configured to determine that the circuit is normal if the resistance is substantially equal to a reference value. 如請求項1之測試系統,其進一步包含一電流源,該電流源經組態以將該第一電流及該第二電流施加至正測試之一電路板的一導電襯墊,且其中對應於該第一電流之該第一電壓在該電路板之該導電襯墊處獲得,且對應於該第二電流之該第二電壓在該電路板之該導電襯墊處獲得。The test system of claim 1, further comprising a current source configured to apply the first current and the second current to a conductive pad of a circuit board being tested, and which corresponds to The first voltage of the first current is obtained at the conductive pad of the circuit board, and the second voltage corresponding to the second current is obtained at the conductive pad of the circuit board. 如請求項1之測試系統,其中該電路進一步包含一保護電路,且該電阻為該保護電路之電阻。The test system of claim 1, wherein the circuit further includes a protection circuit, and the resistor is a resistance of the protection circuit. 一種測試一積體電路(IC)之方法,其包含:(a)施加一第一電流至該IC之一接腳;(b)在該IC之該接腳處量測一第一電壓;(c)施加一第二電流至該IC之該接腳;(d)在該IC之該接腳處量測一第二電壓;及(e)將(i)該第一電壓與該第二電壓之間的一差除以(ii)該第一電流與該第二電流之間的一差以導出該IC之一電阻,其中該第二電壓與該第二電流之一比率給出為該第一電壓與該第一電流之一比率乘以β,且β係在約0.98至約1之一範圍內。A method for testing an integrated circuit (IC), comprising: (a) applying a first current to a pin of the IC; (b) measuring a first voltage at the pin of the IC; ( c) applying a second current to the pin of the IC; (d) measuring a second voltage at the pin of the IC; and (e) combining (i) the first voltage and the second voltage A difference between is divided by (ii) a difference between the first current and the second current to derive a resistance of the IC, wherein a ratio of the second voltage to the second current is given as the first A ratio of a voltage to one of the first currents is multiplied by β, and β is in a range of about 0.98 to about 1. 如請求項10之方法,其中該第一電流與該第二電流之間的一差係在約50μA至約500μA之一範圍內。The method of claim 10, wherein a difference between the first current and the second current is in a range of about 50 μA to about 500 μA. 如請求項10之方法,其中在操作(b)中,若該第一電壓為0,則電連接至該IC之該接腳之一電路判定為經短路連接。The method of claim 10, wherein in operation (b), if the first voltage is 0, one of the pins electrically connected to the IC is determined to be short-circuited. 如請求項10之方法,其中在操作(b)中,若該第一電壓大體上等於施加該第一電流之一電流供應器的一保護電壓,則電連接至該IC之該接腳的一電路判定為經斷開。The method as claimed in claim 10, wherein in operation (b), if the first voltage is substantially equal to a protection voltage of a current supplier to which the first current is applied, then one of the pins of the IC is electrically connected. The circuit is judged to be open. 如請求項10之方法,其中在操作(e)中,若該電阻為0,則電連接至該IC之該接腳之一電路判定為經短路連接。The method of claim 10, wherein in operation (e), if the resistance is 0, one of the pins electrically connected to the IC is determined to be short-circuited. 如請求項10之方法,其中在操作(e)中,若該電阻高於一臨限值,則電連接至該IC之該接腳的一電路判定為經斷開。The method of claim 10, wherein in operation (e), if the resistance is higher than a threshold value, a circuit electrically connected to the pin of the IC is determined to be disconnected. 如請求項10之方法,其中該IC進一步包含一保護電路,且該電阻為該保護電路之電阻。The method of claim 10, wherein the IC further includes a protection circuit, and the resistor is a resistance of the protection circuit. 一種測試包括一積體電路(IC)之一電路板的方法,其包含:(a)施加一第一電流至該電路板之一導電襯墊,該導電襯墊連接至該IC之一接腳;(b)在該電路板之該導電襯墊處量測一第一電壓;(c)將一第二電流施加至該電路板之該導電襯墊;(d)在該電路板之該導電襯墊處量測一第二電壓;(e)將(i)該第一電壓與該第二電壓之間的一差除以(ii)該第一電流與該第二電流之間的一差以導出一第一電阻(Resd+Rpr);及(f)藉由自該第一電阻(Resd+Rpr)減去一第三電阻(Resd)來導出一第二電阻(Rpr),該第三電阻(Resd)與電連接至該IC之該接腳的一電路相關聯。A method of testing a circuit board including an integrated circuit (IC) includes: (a) applying a first current to a conductive pad of the circuit board, the conductive pad being connected to a pin of the IC (B) measuring a first voltage at the conductive pad of the circuit board; (c) applying a second current to the conductive pad of the circuit board; (d) the conductive pad of the circuit board Measure a second voltage at the pad; (e) divide (i) a difference between the first voltage and the second voltage by (ii) a difference between the first current and the second current To derive a first resistance (R esd + R pr ); and (f) to derive a second resistance (R) by subtracting a third resistance (R esd ) from the first resistance ( Resd + R pr ) pr ), the third resistor ( Resd ) is associated with a circuit electrically connected to the pin of the IC. 如請求項17之方法,其中該第二電壓與該第二電流之一比率給出為該第一電壓與該第一電流之一比率乘以β,且β係在約0.98與約1之一範圍內。The method of claim 17, wherein a ratio of the second voltage to the second current is given as a ratio of the first voltage to the first current multiplied by β, and β is between about 0.98 and about 1. Within range. 如請求項17之方法,其進一步包含藉由以下操作導出該第三電阻:(g)施加一第三電流至該IC之該接腳;(h)在該IC之該接腳處量測一第三電壓;(i)施加一第四電流至該IC之該接腳;(j)在該IC之該接腳處量測一第四電壓;及(k)將該第三電壓與該第四電壓之間的一差除以該第三電流與該第四電流之間的一差。The method of claim 17, further comprising deriving the third resistor by: (g) applying a third current to the pin of the IC; (h) measuring a pin at the pin of the IC A third voltage; (i) applying a fourth current to the pin of the IC; (j) measuring a fourth voltage at the pin of the IC; and (k) comparing the third voltage with the first voltage A difference between the four voltages is divided by a difference between the third current and the fourth current. 如請求項19之方法,其中該第三電流與該第四電流之間的一差係在約50μA至約500μA之間的一範圍內。The method of claim 19, wherein a difference between the third current and the fourth current is in a range between about 50 μA and about 500 μA. 如請求項17之方法,其進一步包含比較該第二電阻與該電路板之一參考電阻。The method of claim 17, further comprising comparing the second resistor to a reference resistor of the circuit board. 如請求項21之方法,其進一步包含:若該第二電阻大體上等於該參考電阻,則判定該電路板為正常的;否則,判定該電路板為不正常的。The method of claim 21, further comprising: if the second resistance is substantially equal to the reference resistance, determining that the circuit board is normal; otherwise, determining that the circuit board is abnormal. 如請求項21之方法,其中該IC進一步包含一保護電路,且該第三電阻為該保護電路之電阻。The method of claim 21, wherein the IC further includes a protection circuit, and the third resistor is a resistance of the protection circuit.
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Citations (3)

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Publication number Priority date Publication date Assignee Title
US5194709A (en) * 1990-10-08 1993-03-16 Kabushiki Kaisha Sg Method for checking a spot welded portion and spot welding machine
TWI243521B (en) * 2003-02-28 2005-11-11 Oht Inc Inspecting apparatus of conductor position and inspecting method of conductor position
TWI266886B (en) * 2003-02-28 2006-11-21 Oht Inc Conductor inspecting device and conductor inspecting method

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5194709A (en) * 1990-10-08 1993-03-16 Kabushiki Kaisha Sg Method for checking a spot welded portion and spot welding machine
TWI243521B (en) * 2003-02-28 2005-11-11 Oht Inc Inspecting apparatus of conductor position and inspecting method of conductor position
TWI266886B (en) * 2003-02-28 2006-11-21 Oht Inc Conductor inspecting device and conductor inspecting method

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