TWI637262B - Translation layer partitioned between host and controller - Google Patents

Abstract

A method for using a divided flash transition layer is disclosed. Step (A) receives a write command having a first write data from a host at a device. Step (B) generates a second write data by compressing the first write data in the device. The second write data typically has a variable size. Step (C) storing the second written data in one of the non-volatile memory locations. This entity location is the next unwritten location. Step (D) in response to the write command indicates that one of the physical locations is returned from the device to the host.

Description

Conversion layer division between host and controller

This application is filed on US Provisional Application No. 61/893,383, filed on October 21, 2013, and US Provisional Application No. 61/888,681, filed on October 9, 2013, and filed on September 3, 2013. Application US Provisional Application No. 61/873,357, US Provisional Application No. 61/866,672, filed on August 16, 2013, and US Provisional Application No. 61/755,169, filed on January 22, 2013, Each of these U.S. Provisional Applications is hereby incorporated by reference in its entirety.

This application is related to US Provisional Application No. 13/053,175, filed on March 21, 2011, which is incorporated herein by reference. Each of the US Provisional Application Nos.

This application is also related to the international application PCT/US2012/058583, which has the international filing date of October 4, 2012, which claims the US Provisional Application No. 61/543,707 filed on October 5, 2011. Equity, each of the International Application and the U.S. Provisional Application is incorporated by reference in its entirety.

This application is related to US Patent No. 13/936,010 filed on July 10, 2013, which is hereby incorporated herein by reference in its entirety the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire The international application claims to be filed on September 6, 2011. U.S. Provisional Application No. 61/531,551 and U.S. Provisional Application No. 61/521,739, filed on August 9, 2011, the U.S. Serial No. 13/936,010, the International Application, and the U.S. Provisional Each of the applications is incorporated by reference in its entirety.

The present invention relates generally to computing mainframe and input/output device technology, and more particularly to a method and/or apparatus for providing a transition layer between a host and a controller.

A conventional solid state disk drive stores a fixed number of host logical blocks in each page of a non-volatile memory. A storage efficiency problem occurs when the size of a user data or the available size of one of each page of the non-volatile memory is not fixed. The architecture for variable size flash transition layers in solid state drives is hardware intensive. The page header is used to identify where the user data is stored in a plurality of reading units within a plurality of pages of the solid state disk drive, and extracting the data involves first reading and parsing the page header.

The present invention relates to a method for using a divided flash transition layer. Step (A) receives a write command having a first write data from a host at a device. Step (B) generates a second write data by compressing the first write data in the device. The second write data typically has a variable size. Step (C) storing the second written data in one of the non-volatile memory locations. This entity location is the next unwritten location. Step (D) in response to the write command indicates that one of the physical locations is returned from the device to the host.

100‧‧‧Non-volatile memory page

104‧‧‧Subpage address

110‧‧‧Address/Label LBA[M:U]

111‧‧‧Logic block address LBA[U-1:0]

113‧‧‧ Sections within the subpage

204‧‧‧Complete byte address

206‧‧‧byte data length

404‧‧‧Reading unit address

406‧‧‧ span

500‧‧‧Reading unit

501‧‧‧ Header

510‧‧‧Reading unit

610‧‧‧ main header

620‧‧‧Redundant block headers

630‧‧‧Additional tightening header

640‧‧‧Continuation information

650‧‧‧ condensed data

810‧‧‧Information Header

820‧‧‧Second level mapping header/log/checkpoint header

830‧‧‧ period header

840‧‧‧Other types of headers

870‧‧‧ main header

880‧‧‧Redundant block headers

900‧‧‧ mapping project

1010‧‧‧Uncompressed mapping project

1020‧‧‧A mapping item with one of the same non-volatile memory page addresses as a previously mapped project

1030‧‧‧ has one of the same non-volatile memory page address as the previous mapping item and starts at one of the displacements of the previous data Mapping project

1040‧‧‧A mapping item with one of the same non-volatile memory page address as the previous mapping item, starting at one of the previous data ends and having the same length as the previous mapping item

1100‧‧‧Solid Disk Drive Controller/Controller

1100a to 1100n‧‧‧Solid Disk Drive Controller

1101a to 1101n‧‧‧ solid state disk drive

1102‧‧‧Host

1103‧‧‧Switch/Mesh Architecture/Intermediate Controller

1104‧‧‧Intermediate interface

1105‧‧‧Operating system

1106a to 1106n‧‧‧ firmware

1107‧‧‧Driver

1107D‧‧‧dotted arrow

1108‧‧‧ mapping

1109‧‧‧Application

1109D‧‧‧dotted arrow

1109V‧‧‧dotted arrow

1110‧‧‧Reader

1111‧‧‧ external interface

1111a to 1111n‧‧‧ external interface

1112C‧‧‧ card memory

1112H‧‧‧Host memory

1114‧‧‧Multi-device management software

1115‧‧‧Host software

1116‧‧‧Input/Output Card

1117‧‧‧Input/Output and Storage Devices/Resources

1118‧‧‧Server

1119‧‧‧Regional/Wide Area Network

1120‧‧‧Writer

1130‧‧‧Read sequencer

1140‧‧‧Write sequencer

1141a to 1141n‧‧‧ mapping

1150-1‧‧‧ Data Path Unit

1150-2‧‧‧ Data Path Unit

1180‧‧‧ memory interface

1190‧‧‧ Data path segmentation

1190a to 1190n‧‧‧ device interface

1199a to 1199n‧‧‧ non-volatile memory

Embodiments of the present invention will be apparent from the following detailed description and the accompanying claims and claims, wherein: FIG. 1 is a logical block address to a fixed size area within a non-volatile memory page. One of the selected details of one of the embodiments is illustrated; Figure 2 is one of the selected details of one of the embodiments of a logical block address to a mapping of one of the variable size regions of the non-volatile memory page as appropriate Figure 3 is an illustration of one of the embodiments of a non-volatile memory page comprising one of a plurality of read cells; Figure 4 is a logical block address variable to one of the one or more read cells One of the selected details of one of the embodiments of the mapping of the size regions; Figure 5 is an illustration of one of the selected details of an embodiment of the reading unit including the header and the data; Figure 6 includes one of the headers and the data. One of the selected details of one embodiment of a volatile memory page; Figure 7 is an illustration of one of the selected details of another embodiment of a non-volatile memory page including a header and data; Figure 8 is of various types One of the selected details of one of the embodiments of the header; Figure 9 is an illustration of one of the selected details of one of the embodiments of the mapping; Figure 10 is an illustration of one of the selected details of one of the various compressed mapping items; 11A is a solid state disk drive controller One of the selected details of the embodiment is illustrated; Figure 11B is an illustration of selected details of one embodiment of a data path segment; Figure 11C is an illustration of selected details of various embodiments of the system in accordance with an embodiment of the present invention Figure 12 is a flow chart for writing data to a non-volatile memory; Figure 13 is a flow chart for reading data from a non-volatile memory; and Figure 14 is for making the data in a non-volatile memory. One of the flow diagrams in the body recovery.

Embodiments of the invention include providing a transition layer between a host and a controller, the transition layer: (i) supporting a wide range of data sizes; (ii) non-based blocks (iii) returning a control point to a host in response to writing data; (iv) using the handle to read data; and/or (v) implementing one or more integrated bodies Circuit and / or associated firmware.

A host is coupled to an input/output device (such as a solid state disk drive (eg, SSD) controller) and the input/output device is coupled to and/or includes a non-volatile memory (eg, NVM). An example of a host includes a computing host, a server, a personal computer, a laptop, a notebook, a workstation computer, a number of assistants, a smart phone, a cellular phone, a media player or a record , an input/output controller, a redundant/independent disk redundant array (eg, RAID) (eg, ROC) controller on a die, and any other device including a processor or computer. The host initiates a request to access (eg, read or write) non-volatile memory via the input/output device, and the requests are combined by one of the hosts (eg, at least partially by software running on the host) And performed by an input/output device (eg, at least partially by a firmware running on the input/output device).

In some embodiments, a flash translation layer (e.g., FTL) places a logical block address in a logical block address space, such as used by a host to perform input/output operations on an input/output device. (eg, LBA) maps to (or translates to) an entity location in a non-volatile memory (such as a NAND flash non-volatile memory) (eg, a physical storage address in a physical address space). According to various embodiments, the mapping of one of the logical block addresses in a logical block address space is performed by one or more of: a one-level mapping; a two-level mapping; a multi-level mapping a direct mapping; an associated mapping; a hash table; a B-tree; a clue; one of the mapping parts of the cache memory; and the logical block address associated with the physical location in the non-volatile memory Any other component. In other embodiments, the mapping includes a plurality of items, such as an item for each logical block address in the logical block address space.

In other embodiments, the flash transition layer labels or otherwise uniquely identifies the individual data. The ambiguity maps to the physical location in a non-volatile memory. For example, the tag can be a hash function of a separate piece of data (such as a SHA-256 or SHA-512 hash function), or can be stored as a separate piece of data or an object stored in one of the individual items. An identifier, or one of the individual files, a file system identifier (such as an index node) (where the individual data is a file system object). According to various embodiments, the mapping of tags or other unique identifiers of individual data is performed via one or more of: a one-level mapping; a two-level mapping; a multi-level mapping; a direct mapping; An associated map; a hash table; a B-tree; a clue; one of the portions of the map cache memory; and any other component that associates the label or other unique identifier with the physical location of the non-volatile memory. In other embodiments, the mapping includes a plurality of items, such as an item for each existing tag or other unique identifier. In still other embodiments, the mapping is dynamic in size and it grows or contracts as the number of existing tags or other unique identifiers increases or decreases. In one example, the size of the map grows or contracts linearly as the number of existing tags or other unique identifiers increases or decreases. In another example, the size of the map grows or contracts stepwise (in discrete blocks) as the number of existing tags or other unique identifiers increases or decreases by more than a respective threshold.

In various embodiments, a multi-level mapping is used to provide a unique identifier and/or to limit a range of unique identifiers. For example, a tag is looked up in a first associated map to produce a unique identifier that is shorter than the tag. The unique identifier is then looked up in a second map to produce one of the physical locations in the non-volatile memory. In other embodiments, the second mapping is a plurality of mappings, such as a plurality of physically separate portions for non-volatile memory (eg, present in different solid state disks) and/or functionally distinct portions (eg, A mapping of each of the different types).

Each of a plurality of tags (or handles or logical block addresses or identifiers or other similar terms) generally corresponds to a respective data item (or section or block or item or other similar term), and The flash transition layer causes each of the labels and the corresponding data object to be non-volatile One of the physical locations in the memory is associated. The association of the tag with the physical location of the corresponding data item in the non-volatile memory is said to be made via a mapping regardless of how the association is performed. Although the various examples herein use mapping of logical block addresses, and other examples use mapping of object tags or object identifiers, in the spirit of the teachings herein, many similar material tagging techniques can be used along with associated mapping techniques. .

As used herein, the term "mapping unit" refers to the size of one of the data objects being mapped by the flash transition layer. In some embodiments, the mapping unit is of a fixed size, while in other embodiments, the size of the data item is variable (and thus the size of the mapping unit is not fixed).

In some embodiments, mapping is performed on one or more logical segments or aligned units of the blocks. Each mapping unit is one or more logical segments or one of the blocks aligned with the unit. Each mapping unit has one of the data in which the mapping unit is stored, corresponding to the physical location (possibility of including a NULL entity location if the mapping unit has never been written or trimmed). For example, in the case of a 4 kilobyte (eg, KB) mapping unit, eight connected (and typically eight-segment aligned) serial technology attached (eg, SATA) 512 bits Group segments are mapped to a single unit. Typically, one of the mappings for a logical block address has an item per mapping unit to store a logical conversion from a logical block address associated with the mapping unit to one of the physical addresses of the non-volatile memory and / or other control information.

In various embodiments, the size of one of the data objects being mapped (the size of each mapping unit) and/or the size of one of the data objects stored in the non-volatile memory varies. In one example, each of the items in the map stores a size of one of the individual data items. Continuing with the example, in a key/value store, a tag for accessing one of the items of the mapping is stored according to the key, and the value is a separate data item, the value of which is different in the key. It is different. In another example, each of the items in the map stores an indication of one of the amounts of non-volatile memory used to read the retrieved data item. In a variation of another example, the amount of non-volatile memory specified by one of the mapping items includes The number of non-volatile memory items specified in the mapped item locates the header of each of the stored data items or portions of the stored data items or portions thereof. In another variation of another example, the amount of non-volatile memory used to read the respective data items specifies the exact size of each of the stored data items in one page of the non-volatile memory and Location, regardless of non-volatile memory error correction. The additional operations are used to determine a larger amount of non-volatile memory for reading the information stored in the respective data and other information sufficient to perform error correction on the data read from the non-volatile memory.

According to various embodiments, the non-volatile memory system has one or more of the following: NAND flash, which stores one bit per cell (eg, a single layer cell), two bits (eg, a multi-level cell), Three bits (eg, three-layer cells) or more than three bits and are planar (two-dimensional) or three-dimensional (eg, 3D); NOR flash; any other type of flash memory or electrically erasable In addition to memory; phase change memory (eg, PCM); magnetic random access memory (eg, MRAM); runway memory; resistive random access memory (eg, ReRAM); Access memory (eg, SRAM) or dynamic random access memory (eg, DRAM); any magnetic or optical storage medium; or any other non-volatile memory.

In some embodiments, non-volatile memory, such as by being physically isolated from different input/output devices (eg, in different solid state disks) or organized by having different physical locations or access mechanisms Or multiple groups (eg, one portion of the non-volatile memory is NAND flash, and a second portion is phase change memory). In some embodiments of the embodiments, the mapping is a global mapping, where each entry specifies an input/output device identification (e.g., ID) and one of the physical locations of the input/output devices. In other embodiments, the mapping is divided into portions, such as one portion per input/output device, and a higher level mapping and/or a function of the respective labels determines one of the input/output devices.

Some non-volatile memory (such as NAND flash) provides one of a non-volatile memory page (or, for example, a fast flash page when flashing NAND flash) is writable (or Stylized) unit. Non-volatile memory pages are typically the smallest writable unit of non-volatile memory. In some embodiments and/or usage scenarios, a non-volatile memory page includes a number of user (non-error correction code) data bytes and is used for post-data and error correction decoding (eg, ECC). One of the quantitative spare spaces. A typical NAND flash page size is 8KB or 16KB or 32KB of user data, while a typical mapping unit size for a logical block address is 4KB or 8KB. (Although the term "user" data is used for non-volatile memory pages, some non-volatile memory pages store "system" data such as mapping data and/or checkpoint data. User data is generally intended to refer to Non-error correction decoding part of non-volatile memory pages). NAND flash pages are organized into blocks, typically 128, 256 or 512 flash pages per block. A block is the smallest size unit that can be erased, and a NAND flash page can be (re)written after the page is erased.

Certain non-volatile memories, such as NAND flash, have multiple planes and/or banks and are permitted to be accessed (read or programmed or erased) in parallel from each of two or more planes. One-page and/or one-block "multi-plane" operation. Using a multi-plane stylization advantageously increases the write bandwidth and causes the basic write unit to be a multi-planar page rather than a single single-plan page. The term non-volatile memory page (or non-volatile memory block) as used herein refers to a single non-volatile memory page (or block) or one, depending on how one of the non-volatile memory is used. Multi-planar non-volatile memory pages (or blocks).

Although the term "flash" translation layer (eg, FTL) is used herein, one of the concepts of a translation layer between a logical address and a physical address applies to multiple types of non-volatile memory. In one example, a particular type of non-volatile memory, such as NAND flash, is erased in a large cell prior to rewriting. In another example, certain types of non-volatile memory are subject to wear, resulting in average wear (moving data from more worn portions of non-volatile memory to less worn portions). In yet another example, a new form of hard disk magnetic recording, such as a tiled magnetic recording, does not have the ability to overwrite one of the previously written data without erasing a much larger amount of other data. In various embodiments, the coarse material is Non-volatile memory types with granularity or limited persistence benefit from a (flash) conversion layer.

Referring to FIG. 1, an illustration of selected details of one embodiment of a mapping of a logical block address to a fixed size region within a non-volatile memory page is shown. Some conventional flash transition layers assume that the number of user data bytes in a non-volatile memory page (eg, non-volatile memory page 100) is a power of two (and/or one of the segment sizes) The multiples are divided into non-volatile memory pages into an integer number of mapping units (each shown in Figure 1 as data). For example, in the case of a user data of 16 KB per non-volatile memory page and a mapping unit of 4 KB, each non-volatile memory page contains four mapping units, and the flash transition layer will each mapping unit One of the addresses (eg, LBA[M:U] 110) is mapped to one of a plurality of non-volatile memory pages and four mapping units within each non-volatile memory page. That is, each mapping item contains a separate field, such as: nonvolatile_memory_page_address[n-1:0], mapping_unit_within_nonvolatile_memory__page[k-1:0] where nonvolatile_memory_page_address refers to one of the non-volatile memory in non-volatile memory. Page, and mapping_unit_within_nonvolatile_memory_page refers to one of the 2 ^k mapping unit size portions of each non-volatile memory page (k is fixed for the entire non-volatile memory system). A subpage address 104 is a combination of nonvolatile_memory_page_address and one of mapping__unit_within_nonvolatile_memory_page. For addressing based on a segment (eg, a finer granularity than the mapping unit), the lower bit of the logical block address (eg, LBA[U-1:0] 111) specifies a sub-portion, such as within the mapping unit. A number of segments (eg, segment 113 within a subpage).

Referring to Figure 2, there is shown one of the selected details of one embodiment of a logical block address to a mapping of one of the variable size regions of a non-volatile memory page as appropriate. A variable size flash translation layer (eg, VFTL) conceptually addresses one of the mapping elements (or Sign (eg, LBA[M:U]110) maps to one of the one or more non-volatile memory pages of a variable size region (for example, this is because the mapping unit data is stored in non-volatile memory) The volume is previously compressed and/or in another instance, because the mapping unit is written by the host as a variable size segment, such as for an object storage area). However, providing a complete byte address 204 and a one-bit data length 206 in each mapping item results in a larger mapping item when compared to a conventional flash transition layer.

Referring to Figure 3, an illustration of one of the embodiments of a non-volatile memory page comprising one of a plurality of read units is shown. In some embodiments, the variable size flash translation layer performs the self mapping unit by mapping to an Epage (eg, error correction decoded page) address (also referred to as a "read unit" address). The mapping of addresses (or tags) to physical addresses. An Epage (or read unit) is the minimum amount of data that can be read from non-volatile memory and corrected by an error correction code for protecting the contents of the non-volatile memory. That is, each reading unit contains a certain amount of data and a corresponding error correction decoding check byte that protects the data. In some embodiments, a non-volatile memory page (such as non-volatile memory page 100) or in other embodiments will be considered as a unit of non-volatile memory page group for writing purposes. The group is divided into an integer number of reading units, as illustrated in FIG.

In the case of certain types of non-volatile memory (such as NAND flash), the data stored in the non-volatile memory is the user data byte and the error correction code byte (error correction information). A hybrid, and accessing one of the non-volatile memory higher level controllers determines which bytes and non-volatiles of non-volatile memory are used for user data and which bytes of non-volatile memory And how many bytes are used for error correction decoding. In various embodiments, the number of read units per non-volatile memory page is allowed to vary. For example, some parts of non-volatile memory use a stronger error correction code than other parts (using more bytes in a non-volatile memory page for error correction coding information), and Less reading units and/or less available data per reading unit. In another example, the number of read units per non-volatile memory page when using non-volatile memory This is because the stylized/erase cycle tends to weaken the non-volatile memory, resulting in a stronger error correction code when more (wearing) non-volatile memory is used.

According to various embodiments, the error correction code used is one or more of the following: a Reed-Solomon (eg, RS) code; a Boss-Chad Huri-ho Bose Chaudhuri Hocguenghem (eg, BCH) code; a turbo code; a hard decision and/or soft decision low density parity check (eg, LDPC) code; a polar code; a non-binary code; Redundant array of independent disks (eg, RAID) code; erase code; any other error correction code; any combination of the foregoing, including synthesis, concatenation, and interleaving. Typical codeword sizes range from 512 bytes (plus error correction decoding bytes) to 2176 bytes (plus error correction decoding bytes). The typical number of error correction decoding bytes is in the range of only a few bytes to hundreds of bytes. In some multi-level cell NAND flash devices, the error correction criterion is 40 bits per 1 KB of user data. In some multi-level cell NAND flash devices, the code rate (the ratio of the user byte to one of the total bytes in a read cell) is typically less than 94%. For example, an MLC NAND flash device has a flash page of 17664 bytes, and 16384 bytes of the flash pages are nominally used to store the mapped data, and 1280 bytes are labeled It is used to store the data and the "alternate" byte of the error correction decoding byte. The recommended error correction decoding strength for the MLC NAND flash device is 40 correction bits per 1 kilobyte, which uses 70 of the spare bytes per 1 kilobyte of the mapped data byte. One byte.

Referring to Figure 4, there is shown an illustration of one of the selected details of mapping one logical block address to one of the variable size regions across one or more of the read cells. In some embodiments, the VFTL mapping maps an address (or tag) of a variable size (eg, compressed) mapping unit (eg, LBA[M:U] 110) to each item in the mapping. It is a read unit address 404 and a span (a number of read units) 406 of several read units. One or more (logically and/or physically) read units referenced by one of the mapping items In the non-volatile memory page, for example, the plurality of read cells optionally and/or selectively straddle a non-volatile memory page boundary. In various embodiments in which the data is compacted within the reading unit, mapping one of the items is typically insufficient to locate the associated material alone (this is because the item only references the reading unit and does not reference one of the locations within the reading unit) And further information (such as a header) within the reference reading unit is used to accurately locate the associated material.

In some embodiments, the data is written into the non-volatile memory page in one of a plurality of grain stripings across the non-volatile memory. Writing data across a plurality of grain strips advantageously achieves a larger write bandwidth by writing only one non-volatile memory page to each of the predetermined dies. A strip across one of a plurality of dies is referred to as a redundant block, as in other embodiments and/or usage scenarios, for example, a redundant dies are used in a redundant block. Add class RAID redundancy based on it. In various embodiments, certain blocks of non-volatile memory are defective and are skipped during writing such that striping occasionally has one of the dies being skipped (rather than The "hole" written to the non-volatile memory page of a bad block. In these embodiments, the "sequential" non-volatile memory page is sequentially ordered in a logical order determined by one of the pages written to the non-volatile memory page.

Referring to Figure 5, there is shown an illustration of selected details of one embodiment of a reading unit including a header and data. In various embodiments, the mapping illustrated in Figure 4 results in a criterion for locating variable size data within the reading unit. As illustrated in Figure 5, each read unit (e.g., read units 500 and 510) has a set of zero or more headers 501, and is typically written by hardware, This is because variable size data is "collaged" (eg, densely packed without wasted space) into one or more reading units. When reading non-volatile memory, the header is usually interpreted by other hardware to extract variable size data. Positioning variable size data by one of each of the headers having a matching logical block address (or label), and the data is optionally and/or selective Across a number of reading units (such as variable size data as illustrated by "Data, Start" and "Data, Continue").

In various embodiments, the headers are also used as part of recycling (eg, collection of obsolete items and/or average wear) - including logical block addresses in the header (or equivalently, mapping unit addresses or Label) both to find a variable size data within a read unit and to provide a means for determining when to read a particular one of the read units, whether the variable size data within it is still valid or has been overwritten (by way of looking up the logical block address in the map and determining if the mapping still references one of the specific read unit physical addresses or has been updated to the other of the reference read units). Therefore, the header is said to form an "inverse mapping" because the header combined with the physical location of one of the read units has information similar to that in the mapping but is associated with the logical location (or label) from the physical location. ) information.

In some embodiments, dedicated hardware to extract data from the read unit based on logical block addresses (or tags) is implemented to operate with high efficiency for random reads. A dedicated hardware parses a header within one or more read units to find one of the headers having a given logical block address (or label) and then uses the respective length and displacement to extract the correlation Variable size data. However, a hardware-based solution is expensive (in terms of area and power). For low-end and/or mobile environments where sequential performance is more important than random performance, changes are made to the variable-size flash conversion layer to reduce germanium area, save power, and achieve high sequential throughput rates.

In some embodiments, a sequentially-optimized variable size flash conversion layer (eg, SRO-VFTL) splicing (densely compacted) data onto non-volatile memory pages (or at some In some embodiments, it is considered as a unit of non-volatile memory page group for writing purposes, and there is no gap for the header in the data - all headers are grouped in non-volatile memory In one part of the body page. In other embodiments, the header is not used dynamically to access data (as in some variable size flash conversion layers), but only for recovery and repair of, for example, unexpected power loss. Instead, the mapped items include Complete information on variable size (eg, compressed) data within a volatile memory page. Separating the header and data into different portions of the non-volatile memory page results in a reading unit comprising only the header, a reading unit including a combination of the header and the data (but as in Figure 6, each non-volatile A memory page has only one such read unit) and a read unit that only includes data.

Although configured for low-cost configuration for sequential read throughput, a variable-size flash translation layer that is optimized for sequential reads can be based on other metrics (such as random read input/output operations per second (eg, IOP) ), random write input/output operations per second, and sequential write throughput) perform quite well. However, the removal of hardware assistance, such as the functionality of the VFTL-style data collage by means of a header in each read unit, places a significant burden on a control processor. Alternatively, in some embodiments, the sequentially optimised variable size flash conversion layer uses hardware to assist with data tiling, data extraction, or other operations.

Referring to Figure 6, an illustration of one of the embodiments of a SRO-VFTL non-volatile memory page is shown. Referring to Figure 7, an illustration of another embodiment of a SRO-VFTL non-volatile memory page is shown. A difference between the embodiments of Figures 6 and 7 is that the continuation data 640 from a previous non-volatile memory page is before or after the header. The present invention contemplates various embodiments and configurations of data within a non-volatile memory page.

According to various embodiments, a non-volatile memory page includes one or more of the following:

a header comprising a main header 610, optionally and/or optionally a redundant block header 620 (eg, added to the first page of each block of a redundant block) A header) and zero or more additional punctured headers 630. Each flash page has at least one count of the number of consecutive headers and one of the indicators to the beginning of the data (associated with the headers) in the non-volatile memory page. In some embodiments, the headers may be byte aligned, but each is only 6 bytes (eg, B). Such headers may include, but are not limited to, data headers, epoch headers, and padding. Data header uses a mapping unit address and a length degree. The displacement is implied because all the data is concatenated.

- Continuation data from a previous non-volatile memory page (a portion of variable size data of a mapping unit) 640, as appropriate and/or selectively.

- a compacted (eg, optionally and/or selectively compressed) material 650 for filling one or more mapping units of the non-volatile memory page, the last condition and/or of the non-volatile memory page Optionally continue in a subsequent non-volatile memory page.

- Fill in the end of the non-volatile memory page (included in 650). In various embodiments, the data is constricted (eg, non-porous), but if highly compressed (eg, excessive headers), it may be filled at the end of the non-volatile memory page. For example, padding is used when: (i) the last variable size data segment added to the non-volatile memory page has fewer unused bytes than one of the headers (so, cannot be added) a new header to start another variable size data segment), and (ii) optionally a specified number of headers per non-volatile memory page, as appropriate and/or selectively (thus, stored in a non-volatile The number of mapping units in a memory page is limited by the specified number of headers and not by the data size of one of the mapping units.

In some embodiments, repair and/or recycling (eg, collection of discarded items) with respect to a sequentially read optimized variable size flash conversion layer is advantageously enabled for reading and/or error correction and/or Or verifying only one header portion of each of the non-volatile memory pages, rather than reading and/or miscorrecting in a variable size flash conversion layer that is not sequentially read optimized / or check each reading unit. If the recovery decision can be rewritten into the data of a non-volatile memory page, the data can also be read and error corrected. In some embodiments, an entire non-volatile memory page is read for recycling, but only the header portion is erroneously corrected until one of the data recovery in the non-volatile memory page is determined. until.

In various embodiments, the number of one of the headers per non-volatile memory page is limited to limit the number of readable units per non-volatile memory page to ensure All headers have been read from non-volatile memory. In the embodiment of Figure 6, only a certain number of read units sufficient to accommodate a maximum number of headers are read. In the embodiment of FIG. 7, an additional number of read units are read to account for the maximum size of one of the data from the end of a previous non-volatile memory page (eg, continuation data 640). However, the embodiment of FIG. 7 enables the number of read units used to access the end of the data from a previous non-volatile memory page (eg, continuation data 640) from the associated mapping entry, which is the data. The number of bytes in the end can be determined based on the respective displacements and lengths of the associated mapping items and the number of bytes of user (non-error correction code) data in the previous non-volatile memory page. In addition, the only header before the end of the data is the selection of redundant block headers (only in the specified non-volatile memory pages, such as the first page in each block) and the main header (always Present in every non-volatile memory page). In the embodiment of Figure 6, in order to read the end of the data without having to access the non-volatile memory twice, it is assumed that there is a maximum number of headers (or the entire non-volatile memory page is read).

In some embodiments, the sequentially read optimized variable size flash translation layer uses a single level mapping with one of a plurality of mapping items. In other embodiments, the sequentially read optimized variable size flash translation layer uses a multi-level mapping, such as a two-level mapping, with one of pointing to a second hierarchical mapping (eg, SLM) page first. A hierarchical mapping (eg, FLM), wherein each of the second hierarchical mapping pages includes a plurality of hierarchical mapping entries. In other embodiments, the multi-level mapping has more than two levels, such as three levels. In some embodiments and/or usage scenarios, the use of a multi-level mapping enables only one of the mappings to be correlated (eg, in use) partially stored (eg, cached) in local memory (eg, a solid state) In the SRAM of a disk drive controller or a local DRAM of a host, thereby reducing the cost of maintaining a map. For example, if a typical usage pattern has a logical block address space of 1 billion bytes (eg, GB) acting at any point in time, then only enough local storage of the map for fast access is sufficient for access. The logical block address space acts as part of the 1GB portion rather than storing it in non-volatile memory. A reference other than the active portion of the logical block address space takes the requested portion of one or more levels of the multi-level map from the non-volatile memory, thereby optionally replacing other partial stores of the map as appropriate and/or selectively Part of it.

Each of the leaf-level mapping items is associated (corresponding) with one of the addresses (or tags) of one of the plurality of mapping units. In one example, a logical block address is converted to a mapped unit address, such as by removing zero or more least significant bits (eg, LSBs) and/or out of the logical block address. A constant is added to the logical block address for alignment purposes, and the mapping unit address is looked up in the mapping to determine one of the mappings corresponding to the item. In another example, a tag is looked up in a hash table (or other associated data structure) to determine a unique identifier that is used as one of the mapping unit addresses.

Referring to Figure 8, an illustration of one of the details of one of the various types of headers is shown. In the example of Figure 8, the headers have been formatted to fit into six bytes each. According to various embodiments, the various types of headers are one or more of: all having the same size; depending on the situation and/or selectively having different sizes; each of which includes one of the specified headers a separate field; different sizes in different non-volatile memory pages; and any combination of the foregoing.

According to various embodiments, the header in the non-volatile memory page includes one or more of the following:

- a data header (810) indicating information associated with a variable size data portion. In some embodiments, the data associated with a data header begins in a non-volatile memory page that is identical to the non-volatile memory page in which the data header appears. In other embodiments and/or usage scenarios, if a non-volatile memory page has only remaining space for a data header, all associated data begins in a subsequent non-volatile memory page.

A mapping header, such as a second level mapping (eg, SLM) header (820). The second level mapping header includes a first level mapping index (eg, FLMI) to indicate (eg, for the second level map to retrieve and/or repair) which second level mapping page is being stored.

- Log/Checkpoint header (820). The log/checkpoint header indicates information for recycling, repair, error handling, debugging, or other special conditions.

The epoch header (830) is used as part of the repair to associate the data with the corresponding map/checkpoint information. Typically, there is at least one epoch header per non-volatile memory page.

- The main header (870) is used once per non-volatile memory page to provide information on the number of headers in the non-volatile memory page and where the non-header data begins in the non-volatile memory page Information. Various techniques determine the beginning of one of the non-header data, such as illustrated in the embodiments of Figures 6 and 7.

- Redundant block headers (880) are used in certain non-volatile memory pages, such as the first non-volatile memory page in each block of a redundant block.

- Other types of headers (840), such as padding headers, checkpoint headers that support larger lengths, etc.

In some embodiments, certain headers include a TYPE field to provide one of a plurality of subtypes of the header. In various embodiments, certain headers include a LEN (length) field containing one of the lengths of the data associated with the header. In various embodiments, not a LEN field or a LEN field, some headers also include a displacement (in a non-volatile memory page) that includes the end of the data associated with the header. An OFFSET field (not shown). (In some embodiments, if the last one of the variable size segments spans a non-volatile memory page, OFFSET is one of the subsequent non-volatile memory pages or subsequent non-volatile The number of bytes in the memory page). Usually only one of the LEN field or an OFFSET field is implemented, because of the variable size data segment in a non-volatile memory page in the case of tightening the variable size data segment without waste of space. The start and end positions of each of the non-volatile memory pages are from the beginning of the first variable size data segment (eg, immediately after the header, as in Figure 7) and LEN or OFFSET The list of fields is implied.

Referring to Figure 9, a diagram showing selected details of one embodiment of a mapping item 900 is shown. solution. According to various embodiments, the mapped item comprises one or more of: - a non-volatile memory page address, - a non-volatile memory page to one of a variable size data item ( For example, OFFSET), one of the variable size data items (eg, LEN_M128), and - other control information.

In some embodiments, the length is encoded (for example, by displacement) such that one of the values of zero corresponds to a specified minimum length. For example, if the minimum length is 128 bytes, then one of the 0 LEN_M128 values represents 128 bytes. In other embodiments, the data compressed to less than the specified minimum length is padded to at least a specified minimum length.

In various embodiments, the SRO-VFTL mapping item is larger than the VFTL mapping item, because the SRO-VFTL mapping item stores one of the corresponding displacements and the length of the byte. Therefore, it may be advantageous to reduce the size of one of the mapping items when stored in non-volatile memory. In a typical use, the data is typically read and written sequentially, at least with a certain data granularity and/or an average number of sequential mapping units greater than one. Mapping the project compression format using one of the sequential nature of writing is also relatively inexpensive to implement and produces a high mapping compression ratio. The compression of the mapping item is further aided by having the sequentially written data enter the same non-volatile memory page until it crosses a non-volatile memory page boundary.

Referring to Figure 10, an illustration of one of the selected details of one of the various compressed mapping items is shown. The various mapping items contain uncompressed (1010), one non-volatile memory page address (1020) identical to a previously mapped item, one of the same non-volatile memory page address as the previous mapped item, and previously At the end of the data, one of the displacement starts (1030), and has one of the same non-volatile memory page address as the previous mapped item, starts at one of the displacements of the previous data, and has the same length as the previous mapped item (1040) ).

In some embodiments with a multi-level mapping, maintaining a lower level (such as lobes) Level) One of the map pages caches memory. The cache map page is in an uncompressed form to provide fast access by a processor, such as a host or a solid state drive controller controlling the processor. When mapping pages are moved (such as from non-volatile memory or dynamic random access memory (eg, DRAM)) to the cache, the mapped pages are uncompressed. When the self-cache memory flushes the map page (such as due to being modified), the map page is compressed for storage (such as in non-volatile memory). According to various embodiments in which DRAM is used to reduce latency by storing some or all of the mapped pages in the DRAM, the dynamic random access memory is stored in one or more of the following forms. Mapping page in volume: compressed form; uncompressed form; optionally, compressed or uncompressed form; and (variable size) compressed version for accessing mapped pages in dynamic random access memory One of the indirect tables.

In some embodiments, when a host write command to a host write command arrives at a solid state drive controller, the host writes the data as appropriate and/or selectively, and uses a class of advanced The output (eg, FIFO) is stored in a local (such as a wafer) memory. For example, in some embodiments, the host writes the data along with the firmware data structure, flash statistics, portions of the mapping (such as saving one or more of the pages of the cache memory), from the non- The read data of the volatile memory (including the recovered read data), the header of the data to be written to the non-volatile memory, the software code, the firmware code, and other uses are stored together in a unified buffer (for example, In UBUF) in Fig. 11A. In various embodiments, one or more dedicated memories are used for various local storage criteria for solid state drives.

In some embodiments, the host write data is compressed at a host as appropriate and/or selectively before a host write command to a solid state drive controller is sent to a solid state drive controller. For example, the database records are compressed by a host repository before the database records are written to an input/output device.

In various embodiments, with respect to each mapping unit of data arriving from the host, One of the solid state drives control processor (eg, the central processing unit CPU in FIG. 11A) notifies one or more of the following: a respective mapping unit address in which the storage is associated with the respective mapping unit address One of the associated data addresses and/or variable size (eg, compressed) one of each mapping unit of each of the mapping units. The control processor is enabled to determine a total number of non-erroneously corrected decoded byte groups available in one of the non-volatile memory page write order and each of the non-volatile memory pages. The control processor is enabled to determine the amount of headers placed in the predetermined non-volatile memory page based on the total number of non-erroneously corrected decoded byte groups available in one of the non-volatile memory pages And a quantity of information. For example, the control processor accumulates the header of the predetermined non-volatile memory page (and tracks the number of bytes of the header used so far) and maps the variable size data and the label of the unit one at a time. The header is added to a predetermined non-volatile memory page until the predetermined non-volatile memory page is full. When the predetermined non-volatile memory page is full, one of the data of one of the finalizers added to the mapping unit of the predetermined non-volatile memory page is not loaded in the predetermined non-volatile memory page and is used as The end of the data of one of the non-volatile memory pages (eg, continuation data 640), thereby reducing the total number of non-erroneously corrected decoding bytes available in subsequent non-volatile memory pages for use New headers and information.

In some embodiments, at a particular point in time, zero or more non-volatile memory pages are enabled to be filled with host write data and zero or more non-volatile memory pages are enabled It is filled with recycled data. For example, at least two bands (eg, redundant blocks of the FIFO-like series) can be filled separately, one with "hot" data (eg, just from the host) and the other with "cold" data ( For example, it is reclaimed) and the useful space of zero or more non-volatile memory pages is allocated from one buffer to each band. Continuing with the example, in various embodiments, the host writes data as appropriate and/or selectively enabled to be directed into the tropics or cold strips, and the recovered data is optionally enabled and/or selectively enabled to be Guide to a tropical or cold zone.

In some embodiments, the control processor is enabled to convert a series of respective mapping unit addresses, local memory addresses, and respective lengths into one or more of the following: to be written to a non- Volatile memory page as a series of headers in one of the header parts of a non-volatile memory page; part of the user data portion to be written to a non-volatile memory page as a non-volatile memory page a first start address and a first length of one of the sequential portions of the memory, the user data portion of the non-volatile memory page including at least a portion of the data of the at least one mapping unit; to be written to a subsequent non-volatile The memory page is a second start address and a second length of one of the partial memories of the local memory at the end of the user data of the subsequent non-volatile memory page, and the end portion of the user data includes a mapping unit One of the pieces of data is either empty; the number of zero or more padding bytes to be written to the non-volatile memory page, for example, at the end of the user data Use to fill and empty bytes in the case of non-volatile memory page discontent. Advantageously, the control processor is enabled to simply convert the respective mapping unit address, the respective local memory address and the respective length of the series into a header of the series by reformatting and generate a non-form The fraction of the volatile memory page (the header of the series, the end of a previous non-volatile memory page, the user data portion, and any padding bytes) is transferred to a small number of non-volatile memory directly Memory access (eg, DMA) commands.

In various embodiments, compression of host write data is optionally enabled and/or selectively enabled. In an example, the information of the host write command selectively enables compression. In another example, compression is selectively enabled in accordance with one of the host write commands, a logical block address (or tag). In yet another example, if the compression of the host write data has not reduced the size of one of the host write data, the compression is selectively disabled. If compression is not enabled, the host writes the data uncompressed. According to various embodiments, the mapped item indicates whether the corresponding data is compressed or uncompressed by one or more of: mapping each of the individual bits; and/or storing each mapping One of the lengths in the project. For example, if The mapping unit is 4 KB, and a length of 4 KB in the mapping item indicates that the associated data of a mapping item is uncompressed, and a length of less than 4 KB indicates that the associated data is compressed. In some embodiments and/or usage scenarios, a header associated with the stored condition of the host write data and/or optionally the compressed version specifies whether the stored host write data is compressed. .

In some embodiments, the data is recovered by selecting one of the redundant blocks to be recovered, reading the non-volatile memory pages in the order of the redundant blocks, and reading the non-volatile Memory page, only the read unit that contains the header of the non-volatile memory page, and one of the logical block addresses of each header in the map as a data header (or equivalently, one Map the unit address or label to see if the data is still valid, and if the data is still valid, construct an appropriate new header and DMA command to combine the data to be recovered into a new non-volatile memory page. The new non-volatile memory page is then written to the non-volatile memory.

Referring to Figure 11A, an illustration of one of the selected details of one embodiment of a solid state disk drive controller 1100 is shown. In some embodiments, the solid state disk drive controller 1100 is enabled to implement one or more flash transition layers or portions thereof, such as by implementing a flash transition layer in cooperation with a host. In various embodiments, controller 1100 can be implemented as one or more integrated circuits.

As illustrated in FIG. 11A, one of the input/output receivers of the solid state drive controller 1100, such as a SerDes (eg, a serializer/deserializer), is coupled to a host via an external interface 1111. A host interface (eg, HIF) receives commands (such as read and write commands) via SerDes, receives write data, and sends read data. The commands are sent to a central processing unit via a shared memory (eg, OpRAM). The central processing unit interprets the commands and controls other portions of the solid state drive controller via the shared memory. For example, the central processing unit communicates DMA commands to various data path transmission and reception units via shared memory (such as host data path receive segments (eg, HDRx) or flash data path transport segments (eg, FDTx)) And transmitting and receiving orders from such data paths The yuan receives the response.

A segment (eg, HDRx) is received via the host data path to transfer write data from the host interface to a unified buffer (eg, UBUF). In various embodiments, the host data path receive segment includes logic to conditionally and/or selectively compress and/or encrypt host write data. Then, via a flash data path transmission segment and a general flash interface (eg, GAFI), the optionally and/or optionally compressed and/or encrypted host write data is sent from the unified buffer to the non-volatile buffer. Volatile memory. In various embodiments, the flash data path transmission segment includes logic to perform encryption and/or scrambling and/or error correction coding. In response to the host read command, the data is read from the non-volatile memory via the general flash interface and the segment is received via a flash data path (eg, FDRx) to the unified buffer. In various embodiments, the flash data path receive segment incorporates error correction decoding and/or decryption and/or descrambling. In other embodiments, a separate error correction decoder (eg, LDPC-D for implementing the LDPC code) is enabled to receive "original" data stored in the unified buffer by the flash data path. operating. The decoded read data in the unified buffer is then sent to the host interface via a host data path transport segment (eg, HDTx). In various embodiments, the host data path transport segment includes logic to decrypt and/or decompress the decoded read data as appropriate and/or selectively. In some embodiments, a type of RAID and soft decision processing unit (eg, RASP) is enabled to generate RAID-like redundancy to additionally protect host write data and/or system data stored in non-volatile memory and/or Or perform soft decision processing operations for use with LDPC-D.

According to various embodiments, the solid state disk drive controller is enabled to not implement one or more flash transition layers, implement some of the one or more flash transition layers, all flash transition layers, or implement Part of one or more flash transition layers. In one example, one of the higher level mapping portions of the flash transition layer is executed on the host and one of the lower level mapping portions of the flash transition layer is executed in the solid state drive controller. In another example, the solid state disk drive The controller sends abstract physical unit addresses (such as read unit addresses and spans) to the host and receives abstract physical unit addresses (such as read unit addresses and spans) from the host, and the host will logical block addresses ( Or label) maps to an abstract physical unit address. The solid state drive controller is enabled to locate the particular data via one of the specific data identifiers (such as a logical block address (or tag)) associated with the abstract physical unit address stored in a header . In yet another example, mapping of a logical block address (or a tag) at the host generates a non-volatile memory page address, a displacement within a non-volatile memory page, and a one-tuple length. The solid state drive controller is enabled to determine a number of read units to be accessed in the non-volatile memory to retrieve specified data in one or more non-volatile memory pages. Advantageously, in one or more of the examples, the details of the error correction decoding are maintained by the solid state drive controller (eg, the number of user data bytes per non-volatile memory page or read) One size of the unit), thereby reducing the extra burden on the host.

Referring to Figure 11B, an illustration of one of the selected details of one embodiment of a data path segment is shown. A data path segmentation 1190 can illustrate the host data path receive segment or flash data path transport segment of FIG. 11A. Data path segment 1190 includes a read sequencer 1130, a write sequencer 1140, and zero or more data path units (e.g., DPUs). FIG. 11B illustrates an example with one of two data path units 1150-1 and 1150-2.

The read sequencer 1130 is coupled to the OpRAM (see FIG. 11A) to receive control information specifying the data to be read/accessed. For example, the information can be one of the addresses in the unified buffer and/or one length or one of the host interface or the general flash interface command and can specify commands to be mixed with the data. Read sequencer 1130 is also coupled to a reader 1110 to read/access data, such as from a UBUF, a host interface, or a general flash interface. The read sequencer 1130 is enabled to interleave one of the read data and the command to zero or more data path units 1150-1 and 1150-2 and a write set according to the request received from the OpRAM. Sequencer 1140.

Write sequencer 1140 is enabled to receive an interleaved stream of data and commands transmitted by read sequencer 1130. Write sequencer 1140 is coupled to a writer 1120 to write data, such as to a UBUF, a host interface, or a general flash interface. The data is written in accordance with commands in the data stream received by the write sequencer 1140, such as by specifying a single address and/or a length command. Write sequencer 1140 is also coupled to the OpRAM (see FIG. 11A) to transmit status information regarding the data that has been written in accordance with the received command. For example, state information is written to the OpRAM to indicate the end of a specified portion of a write data stream (eg, a 4 KB mapping unit).

Data path units 1150-1 and 1150-2 are enabled to transform data as it travels between read sequencer 1130 and write sequencer 1140. The commands generated by the read sequencer 1130 in the data stream are optionally and/or optionally intended to be received by one or more of the data path units 1150-1 and 1150-2 or the write sequencer 1140. . Examples of data path units 1150-1 and 1150-2 include:

An encryption unit that receives a command including a salt (initialization vector) to be used for encryption and encrypts the connected data according to the salt. In other embodiments, the command also includes a specification of an encryption key.

a decryption unit that receives a command including a salt (initialization vector) to be used for decryption and decrypts the succeeding data according to the salt. In other embodiments, the command also includes a specification of a decryption key.

a compression unit that receives a command indicating one of the boundaries of a compression unit (e.g., mapping unit) and compresses the contiguous material. In various embodiments, the command also includes one or more of compressing into one of a unit of data amount, a compression type, one of compression for maximum runtime, and other compression controls.

a decompression unit that receives a command indicating one of the boundaries of a compression unit and decompresses the contiguous data. In various embodiments, the command also includes decompressing one of a unit of data, an expected size of the decompressed data, decompressing one type, and using Decompress one or more of one of the maximum runtimes and other decompression controls.

a cyclic redundancy check (e.g., CRC) unit that receives a command including one of a salt (initialization vector) to be used for computing a cyclic redundancy check value and calculates a cyclical redundancy within the data according to the salt Check the value. In other embodiments, the command optionally and/or selectively enables the cyclic redundancy checking unit to append a previously computed cyclic redundancy check value to previously received data covered by the cyclic redundancy check value.

An error correction coding and/or decoding unit that receives a command including one of the code rates and encodes and/or decodes the contiguous data based on one of the bit rate error correction codes. In other embodiments, the commands include additional controls, such as soft decision processing information, maximum number of times to be used, and other encoder and/or decoder control information, as appropriate and/or selectively.

In an example operation, in response to receiving a write command from a host, a command list for reading one of the host data path receiving segments is constructed by the central processing unit, and according to the command list, the host data The path receive segment is enabled to transfer the write data of the write command from the host to the unified buffer via the host interface. One of the data path receiving segments of the host data path is enabled to compress the write data before the (compressed) write data is written to the unified buffer. Multiple (compressed) mapping units are enabled to tightly shrink into the unified buffer without wasted space. The central processing unit is notified by (compressed) the status information of the location and size of each of the mapping units to the OpRAM (which receives the segment write sequencer via the host data path). The central processing unit is enabled to construct a header based on the status information and to determine the amount of the header and (compressed) mapping unit that fills a non-volatile memory page. The central processing unit is further enabled to construct a command list for one of the flash sequencer segments to read the sequencer to transfer the non-volatile memory pages of the header and data to the non-volatile memory. One of the data path segments in the flash data path transmission segment is enabled to encode the header and data being sent to the non-volatile memory, thereby adding additional bytes for error correction decoding protection to the plurality of reads Take each of the units. Immediately retrievable (reusable) from the (compressed) mapping unit in the unified buffer after the write sequencer receives the status of completing the NVM page write from one of the flash data path transfer segments space.

In another example operation, in response to receiving a read command from a host, a command list for reading one of the flash data path receiving segments is constructed by the central processing unit, and according to the command list, The flash data path receive segment is enabled to receive one or more read units from the non-volatile memory read to the unified buffer via the universal flash interface. In some embodiments, one of the flash data path receiving segments is enabled to use an additional byte for error correction coding protection for each read unit and the decoding is being sent to the non-volatile Information on sexual memory. In other embodiments, error correction occurs via a separate data path segment (eg, LDPC-D in Figure 11A). One of the LDPC-D data path segments is written into the sequencer by one of the fast flash data path receive segments, or (in other embodiments) one of the LDPC-D data path segments is written into the sequencer. The central processing unit is notified of the receipt of the corrected data. The central processing unit is further enabled to construct a command list for the host material path transport segment to transmit at least a portion of the corrected data from the unified buffer to the host via the host interface. One of the host data path transmission segments is enabled to decompress the corrected data before the corrected data is transmitted to the host. The space used by the corrected data in the unified buffer can be reclaimed (reusable) upon receipt of the state in which the corrected sequence data has been successfully transmitted from one of the host data path transmission segments.

Referring to Figure 11C, an illustration of selected details of various embodiments of the system is shown in accordance with an embodiment of the present invention. These embodiments typically include one or more instances of the solid state disk drive controller 1100 of Figure 11A. The plurality of solid state drives 1101a through 1101n typically include solid state disk drive controllers 1100a through 1100n coupled to non-volatile memory 1199a through 1199n via device interfaces 1190a through 1190n, respectively. The figure illustrates various types of embodiments: directly coupled to a single solid state drive of a host 1102; each separately via a respective external medium Faces 1111a through 1111n are directly coupled to a plurality of solid state drives of host 1102; and indirectly coupled to one or more solid state drives of host 1102 via various interconnecting elements.

As an exemplary embodiment of a single solid state disk drive directly coupled to a host, an example of solid state disk drive 1101a is directly coupled to host 1102 via an external interface 1111a (eg, omitted, bypassed, or passed through a Switch / Mesh Architecture / Intermediate Controller 1103). As an exemplary embodiment of a plurality of solid state drives each directly coupled to a host via a respective external interface, each of the plurality of instances of solid state drives 1101a through 1101n is via external interfaces 1111a through 1111n, respectively. A separate instance is directly coupled to host 1102 (e.g., omitted, bypassed, or passed through switch/mesh architecture/intermediate controller 1103). As an example embodiment of one or more solid state drives indirectly coupled to a host via various interconnecting elements, each of one or more instances of solid state disk drive 1101 is indirectly coupled to host 1102, respectively. Each indirect coupling is via a respective instance coupled to an external interface 1111a through 1111n of a switch/mesh/intermediate controller 1103 and to an intermediate interface 1104 of one of the hosts 1102.

Some of the embodiments including the switch/mesh architecture/intermediate controller 1103 also include a card coupled via a memory interface 1180 and accessible by the solid state drives 1101a through 1101n and/or by the host 1102. Memory 1112C. In various embodiments, one or more solid state drives 1101a through 1101n, switch/mesh/intermediate controller 1103, and/or card memory 1112C are included in a physically identifiable module, card, or pluggable component (for example, input/output card 1116). In some embodiments, a solid state disk drive 1101a through 1101n (or variations thereof) corresponds to a serial attached SCSI (eg, SAS) disk drive or one coupled to one of the initiators operating as one of the hosts 1102. Serial advanced technology attached (eg, SATA) drives.

The host 1102 is enabled to execute various components of the host software 1115, such as a combination of an operating system (eg, OS) 1105, a driver 1107, an application 1109, and a multi-device management software 1114. A dashed arrow 1107D indicates host software and input / Two-way communication between the output devices (eg, via the driver 1107 and the application 1109 (via the driver 1107 or directly as a (eg, PCIe) virtual function (eg, VF)) to feed data from any of the operating systems 1105 Or one or more of the instances sent to the solid state drives 1101a through 1101n and one or more of the data received from one or more of the instances of the solid state drives 1101a through 1101n to any one or more of the operating systems 1105 By).

In certain embodiments and/or usage scenarios, host software 1115 includes some of the flash transition layers, all of the flash transition layers, or portions of one of the flash transition layers used with solid state drives 1101a through 1101n. In one example, in various embodiments, the driver 1107 implements at least a portion of the flash transition layer for use with the solid state drives 1101a through 1101n. In another example, in various embodiments, the multi-device management software 1114 implements at least a portion of the flash transition layer for use with the solid state drives 1101a through 1101n.

The operating system 1105 includes drivers for interfacing with the solid state drives 1101a through 1101n (illustrated conceptually by the driver 1107) and/or enabled to operate with the drivers. Various versions of Windows (eg, 95, 98, ME, NT, XP, 2000, Server, Vista, 7 and 8), various versions of Linux (for example, Red Hat, Debian, and Ubuntu) and various versions of MacOS (for example, 8, 9 and X) are examples of operating system 1105. In various embodiments, the driver can be paired with a standard interface and/or protocol (such as SATA), advanced host controller interface (eg, AHCI) or NVM Express operating standard and/or general purpose drivers (sometimes called Customized and/or vendor-specific for "shrink-wrapped" or "pre-installed" to enable use of commands and/or flash transitions specific to solid state drives 1101a through 1101n Floor. Some drives and/or drivers have a pass-through mode to enable application-level programs (such as an application) via optimal NAND access (sometimes referred to as ONA) or direct NAND access (sometimes referred to as DNA) technology. 1109) to pass commands directly to the solid state drives 1101a through 1101n, thereby enabling a custom application to use commands and/or flash transition layers specific to the solid state drives 1101a through 1101n even with a general purpose driver. ONA technology Contains one or more of the following: use of non-standard modifiers (prompts); use of vendor-unique commands; delivery of non-standard statistics, such as actual non-volatile memory usage based on compression capabilities; flash Use of transition layer specific protocols, such as passing read unit address and span or such as passing non-volatile memory page address, displacement, and byte length; and other techniques. DNA technology includes one or more of the following: providing non-standard commands for non-mapping read, write, and/or erase access to non-volatile memory or the use of vendor-specific commands; The use of non-standard or vendor-specific commands that provide more direct access to non-volatile memory by formatting the data that would otherwise be performed by the input/output device; and other techniques. The driver example does not support one of ONA or DNA drivers, an ONA enabled driver, a DNA enabled driver, and an ONA/DNA enabled driver. Other examples of drivers are vendor-provided, vendor-developed and/or vendor-enhanced drivers and a client-side, client-side development and/or client-side driver.

An example of an application hierarchy program is one that does not support ONA or DNA applications, an ONA enabled application, a DNA enabled application, and an ONA/DNA enabled application. A dashed arrow 1109D indicates an application and one of the applications (for example, an ONA-enabled application and one of the communication systems using the operating system as a middleware and a solid-state drive without an application) Two-way communication between one of the input/output devices (such as bypassing via a driver or bypassing via a virtual function) is enabled for the ONA driver. A dashed arrow 1109V indicates an application to communicate with an application (eg, a DNA-enabled application and, for example, using an operating system or driver as a middleware to communicate with a solid-state drive without an application) Two-way communication between one of the input/output devices (eg, via a bypass of a virtual function) of a DNA-enabled driver.

In some embodiments, one or more portions of non-volatile memory 1199a through 1199n are used for firmware storage devices (eg, firmware 1106a through 1106n). The firmware storage device includes a Or multiple firmware images (or parts thereof). For example, a firmware image has one or more images of firmware (eg, by a central processing unit of the solid state disk drive controllers 1100a through 1100n). For another example, a firmware image has, for example, one or more images of constants, parameter values, and non-volatile memory device information that are referenced by the central processing unit during firmware execution. For example, the image of the firmware corresponds to a current firmware image and zero or more previous (relative to firmware update) firmware images. In various embodiments, the firmware provides a general purpose, standard, ONA, and/or DNA mode of operation and operates with one or more flash transition layers. In some embodiments, one or more of the firmware operating modes are enabled (eg, "unlocking" one or more applications via a key or various software technologies that are optionally transmitted and/or provided by a driver. Interface (for example, API)). In other embodiments, different ones of the firmware images are used for different ones of the operational modes and/or different ones of the flash transition layers.

In some embodiments, host 1102 includes one mapping 1108 of one of the different hardware resources as one of the implementation maps. In other embodiments, a mapping is implemented partially or completely via mapping 1108 and/or a host memory 1112H and/or via one of solid state disk drive controllers 1100 and/or via card memory 1112C. . Mapping 1108, host memory 1112H, mapping 1141 in solid state drive controller 1100, and instances of card memory 1112C are implemented, for example, via DRAM, SRAM, and/or flash or other non-volatile memory devices. One or more volatile and/or non-volatile memory components. Other examples of host memory are system memory, host main memory, host cache memory, host accessible memory, and input/output devices that can access memory. In certain embodiments and/or usage scenarios, such as some embodiments having an input/output card 1116 and using the card memory 1112C of FIG. 11C as a storage device (for at least a portion of the mapping), one or more The input/output devices and/or host 1102 access the mapping in card memory 1112C.

In various embodiments, one or more of the instances of host 1102 and/or solid state disk drive 1101 are enabled to access mapping 1108, host memory 1112H, card memory 1112C And/or mapping 1141 to save and retrieve can be used to convert a logical block address (or other specifier, such as a tag) into one or more portions of a non-volatile memory of an input/output device (such as non-volatile All of the elements of one or more of the instances of the memory 1199a through 1199n) are all mapping information for the target non-volatile memory location (such as block and/or page address and/or read unit address) Or any part. Conceptually, there may be a single mapping, and according to various embodiments, the control and/or storage and/or use of mapping is provided by one or more of the hosts 1102 and/or by the solid state disk drive controllers 1100a through 1100n. .

In some embodiments lacking the switch/mesh architecture/intermediate controller 1103, the solid state drives 1101a through 1101n are directly coupled to the host 1102 via external interfaces 1111a through 1111n. In various embodiments, solid state disk drive controllers 1100a through 1100n are coupled to host 1102 via one or more intermediate levels of other controllers, such as a RAID controller or an input/output controller. In some embodiments, the solid state drives 1101a through 1101n (or variations thereof) correspond to a SAS disk drive or a SATA disk drive, and the switch/mesh architecture/intermediate controller 1103 corresponds to an expansion The expander is in turn coupled to an initiator, or alternatively, the switch/mesh/intermediate controller 1103 corresponds to a bridge that is indirectly coupled to an initiator via an expander. In some embodiments, the switch/mesh architecture/intermediate controller 1103 includes one or more PCIe switches and/or mesh architectures.

In various embodiments, such as where the host 1102 acts as a computing host (eg, a computer, a workstation computer, a server computer, a storage server, a personal computer, a laptop, a notebook, a mini In some embodiments of the notebook computer and/or a tablet computer, the computing host is optionally enabled to communicate with one or more local and/or remote servers (eg, server 1118) (For example, via the selection of input/output and storage/resources 1117 and the selection of a local area network/wide area network (eg, LAN/WAN) 1119). For example, the communication achieves local and/or remote access, management, and/or use of any one or more of the solid state disk drive components. In some embodiments, the communication is via Ethernet completely or partially. In some embodiments, the communication is completely Ground or partially via a Fibre Channel. In various embodiments, the local area network/wide area network 1119 represents one or more regional networks and/or wide area networks, such as one of a network of servers, one of a network of coupled server arrays, and a metropolitan area. Any one or more of the Internet and the Internet.

In various embodiments, a solid state disk drive controller and/or a computing host non-volatile memory controller is implemented as a non-volatile storage component, such as a universal string, in conjunction with one or more non-volatile memory. A column bus (eg, USB) storage component, a universal flash storage device (eg, UFS) storage component, a compact flash (eg, CF) storage component, a multimedia card (eg, , MMC) storage component, a secure digital (eg, SD) storage component, a memory stick storage component, and an xD picture card storage component.

In various embodiments, all or any portion of a solid state disk drive controller (or a computing host non-volatile memory controller) or a function thereof is implemented in a host to which the controller will be coupled (eg, Figure 11C) Host 1102). In various embodiments, all or any portion of a solid state disk drive controller (or a computing host non-volatile memory controller) or its functionality is via hardware (eg, logic circuitry), software, and/or toughness. Implemented by a body (eg, a driver software or a solid state drive control firmware) or any combination thereof.

Referring to Figure 12, there is shown a flow diagram 1200 of writing data to a non-volatile memory. In step 1202, the program begins, and in step 1206, a data write is made regarding associating a particular one of a plurality of tags (or other unique identifiers, such as an object identification or a logical block address). (storage) to one of the non-volatile memory decisions. For example, the determination is made by one or more of an application, an operating system, a management program, or any other software or firmware module. In some embodiments, the write data is variable in size (eg, may vary with each write operation). In other embodiments, the write data is a number of fixed size units, such as a number of SATA segments.

In step 1210, a write command and associated (possibly variable size) writes are received. data. In one example, an application uses a system call to send a write command and write data (such as via a pointer to one of the data) to a driver. In another example, a host sends a write command along with the information to a solid state drive controller to enable the solid state drive controller to retrieve the associated write data. For example, the write command includes a SATA native command queue (eg, NCQ) tag, and the native command queue tag is used to retrieve the associated write data.

In step 1214, the size of the write data (and possibly variable size) is optionally compressed or otherwise reduced or otherwise reduced. Even if the associated write data is already variable size, compression may be able to further reduce the size of one of the associated writes. In some embodiments, the (possibly variable size, possibly compressed) write data is optionally and/or optionally encrypted.

In step 1218, an unwritten physical location (in a physical address space) below the non-volatile memory for writing data is determined. In one example, the next unwritten physical location is determined to be immediately adjacent to the previously written variable size data (the space in the non-volatile memory is not wasted). In another example, the determined next unwritten physical location begins in one of the read units that are the same as the previously written variable size data. In some embodiments, the next unwritten physical location determined is based on one of the bands specified in the write command.

In step 1222, the (possibly variable size, possibly compressed) write data is stored in non-volatile memory at the determined next unwritten physical location. In some embodiments, a hardware unit writes (possibly variable size, possibly compressed) a data tile to an image of a non-volatile memory page (eg, writes to non-volatile memory) One of the pages in one of the buffers).

In step 1226, a header including one of the identifiers of the written data is stored in a non-volatile memory page that is identical to at least a portion of the (possibly variable size, possibly compressed) write data. For example, the header is stored in one of the same non-volatile memory as at least a portion of the (possibly variable size, possibly compressed) write data as in FIG. The page, and/or the header is stored in one of the same reading units as at least a portion of the (possibly variable size, possibly compressed) write data as in FIG. According to various embodiments, the identifier is one or more of the following: the same as the particular tag that writes the data; a function that writes a particular tag of the material; and the identification associated with the particular tag that writes the data via a table The unique identifier of all the data stored in the non-volatile memory; and any combination of the foregoing.

According to various embodiments, the storage of the data and/or headers (possibly variable size, possibly compressed) occurs in steps 1222 and/or 1226 and/or is postponed until the header and data are accumulated (such as from multiple Until the non-volatile memory page of the write operation). In some embodiments, error correction coding is performed as part of storage to non-volatile memory. In other embodiments, the error correction coding appends a number of error correction decoding bits to the user portion of each reading unit to form a reading unit as stored in the non-volatile memory. In still other embodiments, the scrambling code is performed prior to error correction coding.

In step 1230, an indication is returned that the next unwritten physical location is determined. In an example, the indication of the next unwritten physical location is determined to include a read unit address, such as the first one in the read unit for storing (possibly variable size, possibly compressed) write data. site. Continuing with the example, in some embodiments, the indication of the next unwritten entity location determined further includes a number of read units spanned by (possibly variable size, possibly compressed) write data, for example, Must be read to retrieve all of the read units that do not exceed (possibly variable size, possibly compressed) write data. One or more of the plurality of reading units optionally and/or optionally contain data associated with other materials in the tag, but each of the plurality of reading units contains (possibly variable size) At least some of the data written to the data may be compressed. In another example, the indication of the next unwritten physical location is determined to include the address of the non-volatile memory page and/or to store (possibly variable size, possibly compressed) at least a portion of the written data. Displacement in non-volatile memory pages. Continuing with this other example, in some embodiments, the next decision is made The indication that the entity location is not written further includes (possibly variable size, possibly compressed) the length of the byte in which the data is written. Continuing with this further example, in still other embodiments, (possibly variable size, possibly compressed) writes data across more than one non-volatile memory page (eg, in a first non-volatile memory page) Start and continue to one or more subsequent non-volatile memory pages). For example, when the displacement in the first non-volatile memory page and the amount of remaining user data in the subsequent one are less than (possibly variable size, possibly compressed) in the byte of the data to be written, It may be variable size, possibly compressed) to write data across more than one non-volatile memory page.

In step 1234, a mapping is maintained that associates the particular tag with the indication of the determined next unwritten entity location. For example, maintaining the mapping enables data associated with a particular tag to be retrieved by a subsequent read operation.

In step 1238, the statistics are maintained in accordance with the write command. For example, writing data associated with a particular tag uses one of a plurality of redundant blocks in which the data is written and optionally and/or selectively releasing one of the materials associated with the particular tag A specific amount of space in one of the redundant blocks of the older version. The statistics track the amount of space used by one of each redundant block (or equivalently, in some embodiments, a free space amount). At step 1290, the program ends.

In some embodiments, a lock, such as a semaphore, is used to prevent access to at least a portion of the map during at least a portion of the program 1200. For example, in some embodiments, one of the mappings associated with a particular tag is locked from steps 1210 through 1234 to prevent other access to the item while the item is being updated.

Referring to Figure 13, a flow diagram 1300 of reading data from a non-volatile memory is shown. At step 1302, the process begins, and at step 1306, a read (take) and a plurality of tags (or other unique identifiers, such as object identifiers or logical block bits) from a non-volatile memory are made. One of the data associated with one of the specific ones is determined. For example, the decision is made by an application, an operating system, a management program, or any other soft One or more of the body or firmware modules are made. In some embodiments, the data is variable in size (eg, may vary with each read operation). In other embodiments, the data is a number of fixed size units, such as several SATA sections.

In step 1310, a particular tag is looked up in a map to determine that one of the stored versions of one of the tags associated with a tag is in one of the physical locations in the non-volatile memory. According to various embodiments, the mapping lookup is performed by initiating a software module of a read operation or by another software module invoked by a software module that initiates a read operation. For example, an application initiates a read operation and a mapping layer is performed by one of the driver layers or a firmware layer on a solid state disk controller.

In step 1314, a read command is received that has an indication of one of the non-volatile memory locations. In one example, after a driver layer has performed a mapping lookup on the host, the driver layer sends a read command and an indication of one of the non-volatile memory locations to a solid state drive controller. In another example, after one of the first processor in a solid state disk drive controller has performed a mapping lookup, the first processor sends a read command and an indication of an entity location in the non-volatile memory. A second processor in a solid state disk drive controller that controls access to non-volatile memory.

In step 1318, an indication of one of the non-volatile memory locations is used to determine a location and a number of read units in the non-volatile memory that contain the stored version of the data associated with the particular tag. In an example, the indication of the physical location includes a read unit address, such as one of a stored version for storing data associated with the particular label or one of the first one of the plurality of read units . Continuing with the example, in some embodiments, the indication of the physical location further includes a number of one or more read units, for example, must be read to retrieve all of the data associated with the particular label and not The number of reading units that exceed the stored version. (One or more of the one or more reading units optionally and/or selectively containing material associated with other materials in the tag, but each of the one or more reading units contains and Stored version of the information associated with the label At least some of the versions). In another example, the indication of the physical location includes a location of a non-volatile memory page and/or a non-volatile memory page for storing at least a portion of the stored version of the data associated with the particular tag. One of the displacements. Continuing with the other example, in some embodiments, the indication of the physical location further includes one of a set of bytes of the stored version of the material associated with the particular tag. Continuing with the further example, in still other embodiments, the stored version of the material associated with the particular tag spans more than one non-volatile memory page (eg, begins in a first non-volatile memory page) And continue to one or more subsequent non-volatile memory pages). For example, when the displacement in the first non-volatile memory page and the subsequent remaining user data amount are less than the length in the byte group of the stored version of the data associated with the specific label, The stored version of the associated data spans more than one non-volatile memory page. Further continuing the other example, based on the number and/or size of one of the read units in the first non-volatile memory page and based on the displacement in the byte of the stored version of the data associated with the particular label and The length determines a number of one of the one or more of the read units in the first non-volatile memory page and one of the read units of the first non-volatile memory page. If the stored version of the data associated with a particular tag spans more than one non-volatile memory page, a similar procedure is used for one or more subsequent non-volatile memory pages in the non-volatile memory page to determine subsequent The non-volatile memory page contains additional read units that are at least a portion of the stored version of the data associated with the particular tag.

In step 1322, the determined read unit is read from the non-volatile memory. In some embodiments, error correction decoding is performed on the reading unit to correct any errors that occur during transmission in non-volatile memory and/or to non-volatile memory or from non-volatile memory. . In other embodiments, the descrambling code is performed after error correction decoding. Due to the error correction code of the determined reading unit, it is determined that the plurality of bytes read from the non-volatile memory include error correction in each of the user data and the reading unit in the reading unit Both bit bytes are decoded. In some embodiments, the reading list The number of one of the error correction decoding bytes in each of the elements, such as is dynamically changed by the wear of the non-volatile memory under the control of the solid state drive controller. In various embodiments and/or usage scenarios, such as when at least one of the determined reading units contains at least a portion of the data associated with the other of the tags, the user data in the determined reading unit The total number of one of the bytes exceeds the length in the byte of the stored version of the data associated with the particular tag.

In step 1326, the stored version of the material associated with the particular tag is extracted from the determined reading unit. In some embodiments, the extraction is based on having one of the read commands identifiers. According to various embodiments, the identifier is one or more of the following: the same as the particular label of the material; a function of a particular label of the data; an identifier associated with a particular label of the data via a table; stored in One of the unique identifiers of all materials in non-volatile memory; and any combination of the foregoing. In an example, the reading unit includes one or more headers, as illustrated in FIG. 5, and uses an identifier to determine one of the headers, and then uses the matching header to locate the determined reading. The stored version of the material associated with a particular tag in the unit. In another example, the indication of the physical location includes information specifying a location of a stored version of the data associated with the particular tag within the determined reading unit. According to various embodiments, the stored version of the material associated with a particular tag is variable in size. For example, the material associated with a particular tag is compressed prior to storage, and/or the material associated with a particular tag is itself variable in size.

In step 1330, the stored version of the material associated with the particular tag is optionally decrypted and/or optionally and/or selectively decompressed to generate material associated with the particular tag.

In step 1334, the material associated with the particular tag is returned in response to the read operation.

In step 1338, the statistics are maintained in accordance with the read command. In one example, the read command accesses a particular number of non-volatile memory blocks to retrieve the determined read order A statistic that maintains a count of the number of read disturb events per non-volatile memory block. In another example, the read command accesses a particular number of non-volatile memory blocks to retrieve the determined read unit, and the determined read unit error correction correction is determined in each of the read units A number of individual errors and maintaining statistics of the maximum number of errors corrected in any of the read units in each of the non-volatile memory blocks. At step 1390, the program ends.

Generally, for reading data of a single mapping unit that does not span multiple non-volatile memory pages, the number of reading units to be accessed in the non-volatile memory page to obtain the stored version of the mapping unit data Less than all read cells in a non-volatile memory page. In addition, since the stored version of the data of the mapping unit is variable in size, reference to a first logical block address (or tag) is to be accessed in a non-volatile memory page for a first read command. The number of one of the read units is different from the number of read units of a second logical block address (or tag) that are to be accessed in the non-volatile memory page for a second read command, The two logical block addresses are different from the first logical block address. In some embodiments, only a number of read cells to be accessed in a non-volatile memory page are read from a non-volatile memory page. That is, only the read unit of the stored version of the data containing the mapping unit in the read unit is read from the non-volatile memory to access and retrieve the stored version of the data of the mapping unit.

Referring to Figure 14, there is shown a flow diagram for recycling data in a non-volatile memory. At step 1402, the process begins, and in step 1406, a determination is made as to one of the regions of non-volatile memory to be recovered. According to various embodiments and/or usage scenarios, the region is one or more of: a redundant block; one or more non-volatile memory blocks; maintaining free space therein and/or Part of the non-volatile memory of the spatial statistics used; part of the non-volatile memory in which the average wear statistics are maintained; and any combination of the foregoing. Recycling is performed on one or more of the following in accordance with various embodiments and/or usage scenarios: obsolescence in non-volatile memory Project collection (total free space); average wear of non-volatile memory (to keep blocks of non-volatile memory relatively equal in a separate stylized/erased count); and related to non-volatile memory Program errors and/or exceptions such as program failures, excessive read disturbs, and/or excessive error rates. In other embodiments, the recycling is performed by a host globally, such as across a plurality of solid state drives.

In step 1410, one or more non-volatile memory pages are read from the area of the non-volatile memory. In some embodiments, error correction is performed on the non-volatile memory page as a whole. Error correction is performed on all read units in the non-volatile memory page. In other embodiments, only one portion of the non-volatile memory page that is determined to contain a header (such as illustrated in FIG. 6) is first error corrected, and if determined (eg, step 1426) non-volatile memory If the page contains information that needs to be recycled, the other parts of the non-volatile memory page are erroneously corrected (if needed).

In step 1414, the header is extracted from the non-volatile memory page. In one example, in one embodiment, such as illustrated in FIG. 5, a header is extracted from each of the non-volatile memory pages. In another example, in one embodiment, such as illustrated in Figure 6, one of each of the non-volatile memory pages (such as each of the non-volatile memory pages) One or more reading units) extract headers.

In step 1418, the header extracted from the non-volatile memory page is parsed to determine the identifier of the non-volatile memory page that is associated with, for example, the beginning of the data.

In step 1422, an identifier is looked up in a map to determine a respective indication of the physical location of the data associated with the identifier in the non-volatile memory. In some embodiments, the identifier is the same as the individual tags of the material used in writing the non-volatile memory. In other embodiments, the identifier is combined with other information, such as a solid state drive identifier, to form a tag that is looked up in the map. In still other embodiments, maintaining the identifier associated with the tag and/or causing the identifier to be associated with the identifier is non-volatile An indication of the location of the entity in the memory is associated with one of the mappings.

In step 1426, any data associated with the identifier (currently in the non-volatile memory page being recovered) is written to one of the new entity locations in the non-volatile memory. For example, the respective indications of the physical location of the data associated with the identifier in the non-volatile memory are converted into individual read unit addresses, and if the respective read unit addresses are in the non-recycling In the volatile memory page, the non-volatile memory page being recycled contains the latest version of the data associated with the identifier. In various embodiments, similar to the steps 1218 through 1230 of the routine 1200, the still existing data associated with the identifier is written to one of the new entity locations in the non-volatile memory. In various embodiments, if the current data is still compressed and/or encrypted, the current data is rewritten "as is" in compressed and/or encrypted form. In some embodiments, the non-volatile memory page that is still being recovered from the current data is moved to a new non-volatile memory page in the solid state drive controller (and will not be current data) Sent to a host to reclaim the current data). In other embodiments, recycling includes sending the current data to the host and rewriting the data that is still current, similar to the program 1200. In other embodiments, the recycling is performed globally across a plurality of solid state drives, and for recycling purposes, the current data previously stored on one of the solid state drives is rewritten to the solid state disk. The other one in the machine.

In step 1430, the mapping is updated to reflect an indication of one of the new entity locations for any of the materials that have been recycled.

In step 1434, a determination is made as to whether one of the more non-volatile memory pages will still be processed in the region. If so, the program proceeds to step 1410 to continue recovering other non-volatile memory pages.

In step 1438, the statistics are maintained during the recovery process based on the reading and writing of the non-volatile memory. In one example, the non-volatile memory is read to access a specific number of non-volatile memory blocks to retrieve non-volatile memory pages, and the count is maintained for each non-volatile memory. Statistics on the number of read disturb events for volatile memory blocks. In another example, the non-volatile memory is read to access a specific number of non-volatile memory blocks to capture non-volatile memory pages, and the non-volatile memory pages are erroneously corrected to correct non-volatile memory. The page is erroneously corrected for a number of individual errors in each of the decoded read units, and maintaining the maximum number of corrections in any of the read units in each of the non-volatile memory blocks Statistics of errors. In yet another example, data is recovered by writing non-volatile memory using a particular amount of space in one of the redundant blocks of the recovered data, and optionally released positively and/or selectively A specific amount of space in a redundant block that is recycled. The statistics track the amount of space used by one of each redundant block (or equivalently, in some embodiments, a free space amount). In some embodiments, when the amount of space used in the region being recycled tends to zero, the current (not overwritten) data in the region is no longer reclaimed, and the program 1400 can read All non-volatile memory pages in the area being recycled are completed before. At step 1490, the program ends.

In some embodiments, a lock, such as a semaphore, is used to prevent access to at least a portion of the map during at least a portion of the program 1400. For example, in some embodiments, one of the mappings associated with one of the identifiers of the current data is locked from steps 1422 through 1430 to prevent other access to the item while the item is being updated.

According to various embodiments, the host selects the area of the non-volatile memory to be recovered; the solid state drive controller selects the area of the non-volatile memory to be recovered; the host selects the non-volatile memory for a first reason The area to be recovered, and the solid state disk drive controller selects the area of the non-volatile memory to be recovered for a second different reason; and any combination of the foregoing. In one example, all selections of non-volatile memory regions to be recovered are performed on the host. In another example, the host selects the area of the non-volatile memory to be recycled for the purpose of collecting the waste items, and the solid state disk controller selects the area to be recycled of the non-volatile memory for the average wear. . In yet another example, the host selects non-volatile memory for the purpose of waste collection and average wear. The area to be recycled, and the solid state drive controller selects the non-volatile memory area to be recycled due to abnormal conditions and/or errors such as program failure, excessive error correction decoding error, or read interference event. . In other embodiments, the solid state drive controller is enabled to pass one or more statistics of non-volatile memory, such as stylized/erased counts and/or used spatial statistics, to the host. For example, the statistics are retained as part of a logical block address space of one of the solid state drive controllers or as a log (such as a SMART log) by a special command to read and/or write statistics. transfer. In some embodiments and/or usage scenarios, passing statistics to the host enables the host to select areas of non-volatile memory to be reclaimed, while the solid state drive controller is enabled to maintain statistics from the host. .

In some embodiments, the solid state drive controller is enabled to reclaim at least a portion of the non-volatile memory and to communicate the updated entity location to the host independent of the host. For example, in response to an abnormal condition and/or error, such as a program failure, an excessive error correction decoding error, or a read interference event, the solid state drive controller determines that one of the areas of non-volatile memory must be recovered. The solid state drive controller reads the header in the area of the non-volatile memory and relocates any still current data in the non-volatile memory area to a different portion of the non-volatile memory Individual new entity locations. According to various embodiments, in one or more embodiments: the solid state drive maintains a mapping and is capable of updating the mapping to reflect respective new physical locations that are still current data; the solid state disk drive controller is maintained by the solid state disk drive One of the data of the controller relocation is mapped separately, the individual partial mapping correlates the indication of the physical location of the current data in the non-volatile memory region with the respective new entity location; solid state drive control The respective new entity locations are passed along with information from the headers (such as individual identifiers that are still current data) to the host, and the host updates the mapping; and any combination of the foregoing. Advantageously, the data that is still current can be accessed in both the area of the non-volatile memory and the respective new physical location until the area of the volatile memory is erased. In other embodiments, no volatiles are recorded unless volatile Recall the area of the body until after the mapping is updated with the location of each new entity. For example, the host informs the solid state drive controller that the mapping has been updated, and then only the solid state drive controller is enabled to wipe out areas of the volatile memory.

In various embodiments, the host controls non-volatile memory pages from non-volatile for recycling, such as by requesting a number of non-volatile memory pages to be read or a number of extracted headers to be sent to the host. Reading of the memory (step 1410). According to various embodiments, the host performs at least some of the steps in the header parsing (step 1418) and/or the solid state drive controller (such as by preprocessing and/or reformatting and/or filtering the extracted headers) Perform at least some of the steps in the header parsing. In other embodiments, the host performs a mapping lookup (step 1422) and determines if any material in the material needs to be rewritten. Rewriting (step 1426) is performed by the solid state drive controller under the control of the host (such as by the host sending a "rewrite" command for any data that is still current). The rewrite command is similar to a write command, but does not have a write data. The rewrite command, like a read command, includes one of the physical locations in the non-volatile memory (where the data is being recovered from it). Instructions. Similar to a write command, the rewrite command returns an indication of one of the new entity locations of the rewritten data, and the host performs step 1430 to update the map. In a related embodiment in which the host executes a larger portion of the program 1400, the rewrite command includes a buffer location that is still current data in the solid state drive controller.

In some embodiments, the non-standard and/or vendor unique commands are used as part of a communication protocol between the host and the solid state drive controller. According to various embodiments, the communication protocol is one or more of the following: SATA, small computer system interface (eg, SCSI), SAS, high speed peripheral component interconnect (eg, PCIe), NVM Express (non-volatile memory) SCSI (eg SOP), Mobile Express, USB, UFS, embedded multimedia card (eg eMMC), Ethernet, Fibre Channel or any other suitable for communication between two electronic devices agreement. In one example, one of the physical locations indicates that the transfer between the host and the solid state drive controller uses a vendor specific command, such as a standard A unique version of the vendor of quasi-read and write commands. In another example, the extracted header for recycling is passed from the solid state drive controller to the host in the form of a log page, such as a SMART log page. In yet another example, the extracted header is processed similar to reading the data, but is read by means of a vendor unique "read extracted header" command.

According to various embodiments, any of the steps of program 1200 and/or program 1300 and/or program 1400 are performed by one or more of: coupling to a host of a solid state disk drive controller; coupling A solid state disk drive controller to one of the mainframes; and any combination of the foregoing. In an example, mapping lookup and mapping maintenance are performed on the host. In another example, the determination of the number of read units is performed on either or both of the host and the solid state drive controller. In yet another example, the writing of the write data to the non-volatile memory page is performed on the solid state drive controller (eg, step 1222). In one example, the write data is tiled into a non-volatile memory page image in a buffer of a solid state drive controller under the control of the host. In another example, self-reading unit extraction of data is performed on a solid state drive controller (e.g., step 1326). In yet another example, compression (eg, step 1214) and decompression (eg, step 1330) are performed on the solid state drive controller. In one example, statistics are maintained on the solid state drive controller (eg, step 1238 or step 1338). In another example, an area of the non-volatile memory to be recovered is determined on the host (eg, step 1406). In yet another example, the still-current data to be recovered is moved from an old location to a new location on the solid-state drive controller (eg, step 1426).

In some embodiments, the host and/or solid state drive controller maintains a table that associates each of a plurality of regions of non-volatile memory with specified properties and/or features. In one example, the table associates each of the regions of the non-volatile memory with a particular one of a plurality of code rates (error correction code strengths) such that it is stored in each of the regions One of the data volumes can vary depending on which one of the regions is "healthy". Use a higher (weaker) code rate for healthier areas and enable to store more user resources The weaker area uses a lower (stronger) code rate and is enabled to store less user data (but enabled to correct more errors). In another example, the table indicates an area in the area that is defective or has failed and should not be used. For example, in the case of NAND flash, some of the plurality of blocks of NAND flash are defective even when the NAND flash is new, and other areas in the blocks The block may fail during one of the NAND flash lifetimes. The table indicates the blocks that must be skipped when data is written sequentially across a plurality of NAND flash devices (eg, striped).

In some embodiments, one of the higher level portions of the map is maintained on the host and one of the lower level portions of the map is maintained on the solid state drive controller. The higher level portion of the mapping associates the tag (or logical block address) with a separate indication of the physical location in the non-volatile memory. The indication of the physical location in the non-volatile memory is then further converted by the solid state drive controller using the lower level portion of the mapping to determine the physical portion of the non-volatile memory to be read and/or written. From the perspective of the host, the indication of the physical location acts as an opaque handle, as the solid state drive controller assigns one of the indications of the physical location to one of the particular data objects being written, and the solid state disk The machine controller is enabled to return a particular data item upon returning a corresponding indication of the physical location. In other words, the knowledge of the specified details of the user profile organization in the non-volatile memory is hidden from the host system. Advantageously, the solid state drive controller is enabled to perform at least some management of non-volatile memory, such as selecting a code rate or determining other portions of the bad or non-volatile memory that are not used by the host.

In one example, when one of a plurality of blocks of non-volatile memory is first used, the solid state drive controller divides each of the plurality of pages of the particular block into a plurality (eg, , eight) each of the read units and using one of a plurality of code rates for error correction of a particular block. Later, when the particular block is reused after the particular block is worn more, the solid state drive controller divides each of the plurality of pages of the particular block into multiples (eg, seven) Each reading unit and for that particular block Error correction uses one of the stronger code rates. In both cases, when a host writes data stored in a particular block, one of the physical locations in that particular block indicates a number of read units that are divided into pages independent of that particular block.

In another example, when the variable size data spans the plurality of blocks of the non-volatile memory, the indication of the physical location used by the host is independent of any particular block of the non-volatile memory. In use, it has been marked as bad and not used. Continuing with this other example, it is assumed that block 7 of a particular one of the plurality of grains of the non-volatile memory is bad and unused. The solid state disk drive controller uses block 6 of a particular die when the data in one of the former tiles 6 spans to a subsequent block. When the data in block 7 of the previous die spans to a subsequent block, the solid state drive controller skips block 7 of the particular die and continues in block 7 of the lower one of the die. data. The host does not have knowledge about which of the blocks spans the data.

According to various embodiments, background operations such as read washing and recycling are performed by one or more of a host, a solid state drive controller, and any combination thereof.

According to various embodiments, any operation of one of the host and/or solid state drive controllers is performed by any one or more of the central processing units, by one or more hardware units, and/or by the foregoing Any combination of items is executed.

According to various embodiments, a host and/or a solid state disk drive controller is enabled to use one or more of: a conventional flash transition layer; a variable size flash transition layer; a sequential read Optimized variable size flash transition layer; any other type of flash conversion layer; direct access to non-volatile memory; any combination of the foregoing in different physical portions of non-volatile memory; Any combination of the foregoing of the logical portions of one of the logical address spaces of the solid state drive controller; access to the original entity of the non-volatile memory; and any combination of the foregoing.

According to various embodiments, the host write data is optionally encrypted and optionally before being written to the non-volatile memory and/or optionally from the non-volatile memory before being written to the non-volatile memory. The memory is decrypted after reading. In other embodiments, the encryption occurs after the host writes the data as appropriate and/or selectively, and the decryption occurs before the data being read is optionally and/or selectively decompressed for transmission back to the host. .

Although several exemplary embodiments herein have used solid state drives and solid state drive controllers, the techniques described are generally applicable to other input/output devices and/or data storage devices, such as hard disk drives. In various embodiments, non-volatile memory systems used in such input/output devices are non-volatile memory other than "solid" non-volatile memory, such as hard disk drives (eg, using shingled tiles) The magnetic disk of the magnetic recording hard disk drive).

In some embodiments, a solid state disk or a portion of an input/output device that is interoperable with a multi-node storage device or portion thereof (eg, a hard disk drive or enabled to communicate with a processor (such as a CPU) Non-volatile memory controller, an input/output controller (such as a RAID die on a wafer) and a portion of a processor, a microprocessor, a single-chip system, a special application integrated circuit, a hardware accelerator or the like Various combinations of all or part of the operations performed in whole or in part of the operation are specified by one specification compatible with the processing performed by a computer system. The specification is based on various descriptions such as hardware description language, circuit description, network connection table description, mask description or layout description. Example descriptions include, but are not limited to, Verilog, VHDL (Very High Speed Integrated Circuit Hardware Description Language), SPICE (Integrated Analog Program for Integrated Circuits), SPICE variants (such as PSpice), IBIS (Input/Output Buffer Information Specification) , LEF (Library Exchange Format), DEF (Design Exchange Format), GDS-II (Graphics Database System II), OASIS (Open Art System Exchange Standard) or other descriptions. In various embodiments, the processing includes any combination of interpretation, compilation, simulation, and synthesis to generate, verify, or specify logic and/or circuitry suitable for inclusion on one or more integrated circuits. According to various embodiments, each integrated circuit can be designed and/or fabricated in accordance with a variety of techniques. These technologies include a programmable technique (such as a field or mask programmable gate array integrated circuit), half of the custom technology (such as a fully or partially unit-based integrated circuit) and a full custom Technology (such as essentially specialized one integrated circuit), any group thereof Any other technique that is compatible with or compatible with the design and/or manufacture of the integrated circuit.

The functions performed by the diagrams of Figures 1 through 14 can be implemented using one or more of the following: a conventional general purpose processor, a digital computer, a microprocessor, a microcontroller, a RISC (Reduced Instruction Set Computer) Processor, CISC (complex instruction set computer) processor, SIMD (single instruction multiple data) processor, signal processor, central processing unit (CPU), arithmetic logic unit (ALU), video digital signal processor (VDSP) and / or a similar computing machine that is stylized according to the teachings of this specification, as will be apparent to those skilled in the art. Skilled programmers can readily prepare suitable software, firmware, decoding, routines, instructions, opcodes, microcode, and/or programming modules based on the teachings of the present invention, as will be apparent to those skilled in the art. The software is typically executed by one or more of the processors of the machine implementation from a medium or media.

The invention can also be implemented by the following preparations: ASIC (Special Application Integrated Circuit), Platform ASIC, FPGA (Field Programmable Gate Array), PLD (Programmable Logic Device), CPLD (Complex Programmable) Logic device), sea-of-gate, RFIC (RF integrated circuit), ASSP (Special Application Standard Product), one or more monolithic integrated circuits, configured as flip chip modules and/or One or more of the multi-chip modules or dies, or a suitable network by interconnecting one of the conventional component circuits, as will be apparent to those skilled in the art, will be readily apparent to those skilled in the art.

Accordingly, the present invention may also comprise a computer product, which may comprise one or several storage media and/or one or several transmission media that can be used to program a machine to perform one or more of the programs or methods in accordance with the present invention. . The execution of the instructions contained in the computer product, together with the operation of the surrounding circuitry, may transform the input data into one or more files on the storage medium and/or represent a physical object or asset (such as an audio and/or visual depiction). One or more output signals. The storage medium may include, but is not limited to, any type of disc, including floppy disks, hard drives, disks, compact discs, CD-ROMs, DVDs, and magneto-optical discs and circuits, such as ROM (read only memory), RAM (random Access memory), EPROM (can be erased) ROM), EEPROM (Electrically Erasable Programmable ROM), UVPROM (UV erasable programmable ROM), flash memory, magnetic card, optical card and/or any type suitable for storing electronic instructions media.

Elements of the invention may form part or all of one or more devices, units, components, systems, machines, and/or devices. Such devices may include, but are not limited to, servers, workstations, storage array controllers, storage systems, personal computers, laptops, notebooks, palmtop computers, personal digital assistants, portable electronic devices, battery powered devices Device, set-top box, encoder, decoder, transcoder, compressor, decompressor, pre-processor, post-processor, transmitter, receiver, transceiver, crypto circuit, cellular phone, digital camera, Positioning and/or navigation system, medical equipment, heads-up display, wireless device, audio recording, audio storage and/or audio playback device, video recording, video storage and/or video playback device, gaming platform, peripherals and/or multi-chip Module. Those skilled in the art will appreciate that the elements of the present invention can be implemented in other types of devices to meet the criteria for a particular application.

The use of the terms "may" and "generally" in this context is intended to convey the description as exemplary and is believed to be broad enough to encompass the specific examples presented in the disclosure and may be derived based on the disclosure. The intent of the alternative examples. The terms "may" and "generally" as used herein are not to be construed as necessarily implying that the o

While the invention has been shown and described with reference to the embodiments of the present invention, it will be understood

Claims (20)

A method for storing data by dividing a partitioned flash translation layer, comprising the steps of: receiving a first data to be written from a host; and storing a second data generated from the first data a memory in which the first data is compressed to generate the second data, the second data having a variable size to store the second data in a plurality of physical locations of the memory, and storing the second data One of the plurality of physical locations initial physical location is one of the next unwritten locations in the memory, and the size of the second data is stored in a first partition of one of the flash transition layers local to the memory And the initial physical location of the second data in the memory is stored in a second partition of the flash transition layer of the host. The method of claim 1, further comprising the steps of: receiving, from the host, a read command of the initial physical location having the second data; reading the second data from the first partition of the flash transition layer The size is obtained; and the second data is retrieved by reading a portion of the memory based on the initial physical location and the size of the second data. The method of claim 2, further comprising the steps of: reforming the first data by decompressing the second data retrieved from the memory; and transmitting the first data as reformed Go back to the host. The method of claim 1, further comprising the step of storing an identifier associated with the first material in the memory as at least a portion of a header associated with the second material. The method of claim 4, further comprising the step of maintaining a mapping in the host, wherein the mapping associates the identifier with the initial physical location of the second material in the memory. The method of claim 4, wherein the identifier is a logical block address, and the initial physical location is an address of one of a plurality of read units of the second data stored in the memory, and Each of the plurality of reading units includes a respective one of the second data and a respective one of the respective portions of the second data to correct error correction information. The method of claim 6, wherein the memory has a plurality of pages, the address is in a first page of the plurality of pages storing the second data, the first page includes a first number of The plurality of reading units of the second data, the second page of the plurality of pages comprising a second number of the plurality of reading units for storing the second data, and the first number is different from the second number. The method of claim 1, wherein the next unwritten location is adjacent to previously written data in a physical address space of one of the memories. The method of claim 1, wherein the steps are performed in a solid state drive controller. A method for storing data by dividing a flash transition layer, comprising the steps of: receiving data to be written from a host, wherein the data has a variable size; and storing the data in a memory The data is stored in a plurality of physical locations of the memory, and one of the plurality of physical locations storing the data is an initial physical location of the memory, and the size of the data is stored. The first physical partition of the flash transition layer that is local to the memory, and the initial physical location of the data in the memory is stored in the host The flash transition layer is in a second division. The method of claim 10, further comprising the step of: receiving, from the host, a read command having the initial physical location in the memory that holds the data; reading the first partition from the flash transition layer The size of the data; and based on the initial physical location and the size of the data, the data is retrieved by reading a portion of the memory. The method of claim 11, further comprising the step of transmitting the data back to the host. The method of claim 10, further comprising the step of storing an identifier associated with the material in the memory as at least a portion of a header associated with the material. The method of claim 13, further comprising the step of maintaining a mapping in the host, wherein the mapping associates the identifier with the indication of the initial physical location of the material in the memory. The method of claim 13, wherein the identifier is a logical block address, and the initial physical location is an address of one of a plurality of read units in the memory that holds the data, and the complex number Each of the reading units includes a respective one of the data and a respective error correction information that protects one of the respective portions of the data. The method of claim 15, wherein the memory has a plurality of pages, the address being in a first page of the plurality of pages storing the data, the first page comprising a first number of data to be saved The plurality of reading units, the second page of the plurality of pages includes a second number of the plurality of reading units for storing the data, and the first number is different from the second number. The method of claim 10, wherein the next unwritten location is adjacent to previously written data in a physical address space of one of the memories. The method of claim 10, wherein the steps are performed in a solid state drive controller. A storage device comprising: an interface configured to process a plurality of read and write operations from a memory and to the memory; and a control circuit configured to receive the first from a host And storing the second data generated from the first data in the memory, wherein compressing the first data to generate the second data, the second data having a variable size, storing the second data One of the plurality of physical locations of the memory, the initial physical location of the second physical location is one of the next unwritten locations in the memory, and the size of the second data is stored in the The first partition of the flash transition layer in which the memory is local, and the initial physical location of the second data in the memory is stored in a second partition of the flash transition layer of the host . The device of claim 19, wherein the interface and the control circuit are part of a solid state drive controller.