DE102014111670A1 - A transition layer partitioned between a host and a controller - Google Patents

Abstract

Disclosed is a method of using a partitioned flash transition layer. A step (A) receives at a device from or from a host a write command with first write data. A step (B) generates second write data by compressing the first write data in the device. The second write data is generally a variable size. A step (C) stores the second write data at a physical location in a non-volatile memory. The physical location is a next non-described location. Step (D) returns an indication of the physical location from the device to the host in response to the read command.

Description

This application is related to U.S. Provisional Application No. 61 / 893,383 filed on Oct. 21, 2013, US Provisional Application No. 61 / 888,681 filed on Oct. 9, 2013 and US Provisional Application No. 61 filed on Sep. 3, 2013 US Provisional Application No. 61 / 866,672 filed August 16, 2013, and US Provisional Application No. 61 / 755,169 filed January 22, 2013, each of which is hereby incorporated by reference in its entirety.

This application is related to US Patent Application Serial No. 21 filed on Mar. 21, 2011. No. 13 / 053,175, which relates to U.S. Provisional Application No. 61 / 316,373 filed March 22, 2010, each of which is hereby incorporated by reference in its entirety.

This application also relates to the international application PCT / US2012 / 058583 which has an international filing date of 4 October 2012 and which claims the benefits of US Provisional Application No. 61 / 543,707 filed on October 5, 2011, each of which is hereby incorporated by reference in its entirety.

This application is related to United States Patent Application Serial No. 2007 filed July 10, 2013. 13 / 936,010, referring to the international application PCT / US2012 / 049905 which has an international filing date of 8 August 2012 and which claims the benefits of US Provisional Application No. 61 / 531,551 filed on September 6, 2011 and US Provisional Application No. 61 / 521,739 filed on August 9, 2011, of each of which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD OF THE INVENTION

The invention relates generally to rake hosts and to input / output device technology, and more particularly to a method and / or apparatus that provides a transition layer partitioned between a host and a controller.

BACKGROUND

Conventional solid state drives store a fixed, whole number of logical blocks of a host in each page frame of a non-volatile memory. Memory efficiency issues occur when either a size of user data or a usable size of each page frame is not specified in the non-volatile memory. Architectures for variable-sized flash transistion layers in the solid-state drives are hardware-intensive. Page header headers are used to identify where the user data is stored in multiple read units within the page frames of the solid state drive, and extracting the data requires first reading and parsing the page frame -Nachrichtenkopfes.

SUMMARY

The invention relates to a method of using a split flash-layer. A step (A) receives at a device from or from a host a write command with first write data. A step (B) generates second write data by compressing the first write data in the device. The second write data is generally a variable size. A step (C) stores the second write data at a physical location in a non-volatile memory. The physical location is a next non-described location. A step (D) returns an indication of the physical location from the device to the host in response to the write command.

BRIEF DESCRIPTION OF THE FIGURES

Embodiments of the invention will become apparent from the following detailed description and the appended claims and the drawings, in which:

1 12 is an illustration of selected details of one embodiment of mapping a logical block address into fixed sized areas within a non-volatile memory page frame;

2 13 is an illustration of selected details of one embodiment of mapping a logical block address to a variable size area that optionally spans non-volatile memory page frames;

3 Figure 4 is an illustration of one embodiment of a non-volatile memory page frame comprising an integer number of read units;

4 Figure 4 is an illustration of selected details of one embodiment of mapping a logical block address to a variable sized area spanning one or more read units;

5 Fig. 3 is an illustration of selected details of an embodiment of a reading unit comprising message headers and data;

6 Figure 4 is an illustration of selected details of an embodiment of a non-volatile memory page frame that includes message headers and data;

7 Fig. 4 is an illustration of selected details of another embodiment of a non-volatile memory page frame including message headers and data;

8th Fig. 3 is an illustration of selected details of one embodiment of various types of message headers;

9 FIG. 4 is an illustration of selected details of an embodiment of a mapping entry; FIG.

10 Fig. 4 is an illustration of selected details of one embodiment of various compressed map entries in the image;

11A FIG. 4 is an illustration of selected details of one embodiment of a solid state drive controller; FIG.

11B Fig. 3 is an illustration of selected details of one embodiment of a data path segment;

11C Figure 3 is an illustration of selected details of various embodiments of the system according to one embodiment of the invention;

12 Fig. 10 is a flowchart of writing data to a non-volatile memory;

13 FIG. 11 is a flowchart of reading data from a non-volatile memory, and FIG

14 Fig. 10 is a flowchart of recycling data to non-volatile memory.

DETAILED DESCRIPTION OF EMBODIMENTS

Embodiments of the invention include providing a transition layer partitioned between a host and a controller that (i) supports a wide range of data sizes, (ii) operates on non-block based data (iii) returns a handle to a host in response to the writing of the data; (iv) the handle may be used to read the data; and / or (v) may be implemented as one or more integrated circuits and / or associated firmware.

A host is coupled to an input / output device (such as a solid state drive (eg, SSD) controller, and the input / output device is coupled to and / or includes nonvolatile memory (eg, NVM) Examples of a host include a computer host, a server, a personal computer, a laptop computer, a notebook computer, a workstation computer, a personal digital assistant, a smartphone, a mobile radio Telephone device, a media player or recorder, an input / output controller, a controller of a redundant array of inexpensive / independent disks (eg RAID, redundant array of independent disks) on-chip (eg ROC, RAID). on-chip), and any other devices that include a processor or computer, the host makes requests to access (eg, read or write) the non-volatile memory about the input / output device, and the requests are from a combination of the host (e.g. at least partially by software running on the host) and by the input / output device (e.g., at least in part by firmware running on the input / output device).

In some embodiments, from (or translates to) flash transition layers (eg, FTLs), logical block addresses (LBAs) in a logical block address space (as used by a host) form input / output operations in an input / output device) to physical locations (eg, physical memory addresses in a physical address space) in a nonvolatile memory, such as a non-volatile NAND flash memory. According to various embodiments, the mapping of a logical block address into a logical block address space occurs via one or more of the following: a one-level map; a two-level map; a multi-level map; a direct picture; an associative figure; a hash table; a B-tree; a prefix tree (trie); a cache of part of the image; and any other means for associating the logical block addresses with the physical locations in the non-volatile memory. In further embodiments, the mapping includes a plurality of entries, such as an entry for each logical block address in the logical block address space.

In other embodiments, flash transitions form labels or other unique identifiers of corresponding data to physical locations in nonvolatile memory. For example, the name could be a hash (such as a SHA-256 or SHA-512 hash) of the corresponding data, or an object identifier of a corresponding object stored as or in the corresponding data, or an identifier of a file system (such as an imode) of the corresponding data (where the corresponding data is a file system object). According to various embodiments, the mapping of names or other unique identifiers of the corresponding data is via one or more of the following: a one-level map; a two-level image; a multi-level image; a direct picture; an associative figure; a hash table; a B-tree; a prefix tree (trie); a cache of a portion of the map and any other means of associating the names or other unique identifiers within the physical locations of the non-volatile memory. In other embodiments, the mapping includes a plurality of entries, such as an entry for each existing name or other unique identifier. In still further embodiments, the map is dynamic in size and grows or shrinks as the number of existing names or other unique identifiers increases or decreases. In one example, the size of the map grows or shrinks linearly as the number of existing names or other unique identifiers increases or decreases. In another example, the size of the map grows or shrinks incrementally (in discrete pieces) as the number of existing names or other unique identifiers increases or decreases by more than a corresponding threshold.

In various embodiments, a multi-level map is used to provide unique identifiers and / or to delimit a range of unique identifiers. For example, a name is looked up in a first associative map to produce a unique identifier that is shorter in length than the name. The unique identifier is then looked up in a second map to create a physical location in the non-volatile memory. In further embodiments, the second mapping is a plurality of mappings, such as an image for each of a plurality of physically separated regions (eg, present in different solid state disks) and / or functionally distinct regions (eg, different types) of the non- volatile memory.

Each of a plurality of names (or handles or logical block addresses or identifiers or other similar expressions) generally corresponds to a corresponding data object (or sector or block or element or other similar expressions), and the flash transition layer places a physical location in each of the names to the non-volatile memory of the corresponding data object. It is said that the mapping of the name and the physical location in the non-volatile memory of the corresponding data object is represented by a map regardless of how the mapping is performed. Because various examples herein use mapping of logical block addresses and other examples use mapping of object names or object identifiers, many similar data labeling techniques, along with associated mapping techniques, are useful herein in accordance with the spirit of the teachings.

The term "imaging unit" as used herein refers to a size of the data objects imaged by the flash transition layer. In some embodiments, the mapping unit has a fixed size, while in other embodiments the data objects are variable in size (and thus the mapping units are not fixed in size).

In some embodiments, the mapping to aligned units operates from one or more logical sectors or blocks. Each mapping unit is an aligned unit of one or more logical sectors or blocks. Each mapping unit has a corresponding physical location where data of the mapping unit is stored (including the possibility of a ZERO physical location if the mapping unit has never been written or trimmed.) For example, with 4 kilobytes (eg KB) mapping units become eight contiguous Generally, a logical block address map has one entry per mapping unit to have a corresponding translation from that of the mapping unit (typically, eight sector aligned) 512 byte sectors in the form of a Serial Advanced Technology Attachment (eg, SATA) associated logical block address in a physical address in the non-volatile memory and / or other control information store.

In various embodiments, a size of the data objects that are mapped (the size of each mapping unit) and / or a size of the data objects as stored in the non-volatile memory varies. In one example, each of the entries in the map stores a size of the corresponding data objects. Continuing the example, in a key / value memory, a label used to access an entry in the map is stored according to the key, and the value is a corresponding data object, the value being in size varies over different individual of the key. In another example, each of the entries in the map stores an indication of a size of the non-volatile memory to be read to retrieve the stored data object. In a variation of the other example, the size of the non-volatile memory, as specified by the entry in the map, includes headers that size the corresponding stored data among one or more stored data objects or portions thereof non-volatile memory specified by the entry of the picture locates. In another variation of the other example, the size of the non-volatile memory to be read specifies the corresponding data objects, the exact size, and the location of the corresponding stored data objects in a page frame of the non-volatile memory. however, regardless of the error corrector of the non-volatile memory. Additional calculations are used to determine a larger size of the non-volatile memory to be read to recover both the corresponding stored data object and other sufficient information to perform error correction on the data read from the non-volatile memory.

According to various embodiments, the non-volatile memory is one or more of the following: a NAND flash containing one (eg, single-level cell, single-level cell), two (eg, multi-level cell, multi-level cell) stores three (eg triple-level cell, tripple-level cell) or more bits per cell and which is planar (2-dimensional) or three-dimensional (eg, 3D); a NOR flash or any other type of flash memory or electrically erasable memory; a phase change memory (e.g., PCM, phase change memory); a magnetic random access memory (e.g., MRAM); a racetrack store; a resistive random access memory (e.g., ReRAM, resistive random access memory); a battery-buffered static random access memory (e.g., SRAM) or a dynamic random access memory (e.g., DRAM), a magnetic or optical storage medium, or any other non-volatile memory.

In some embodiments, the nonvolatile memory is organized into one or more groups, such as being physically separated into different input / output devices (eg, in different solid state disks), or having different physical locations or access mechanisms (eg one portion of the non-volatile memory is a NAND flash and a second portion is a phase change memory). In some of the embodiments, the mapping is a global map where each entry specifies an identifier (e.g., ID) of an input / output device and a physical location in that input / output device. In other embodiments, the map is divided into several lines, such as one part per input / output device, and a higher level map and / or a function of the corresponding name determines a selected one of the input / output devices ,

Some nonvolatile memories, such as a NAND flash, provide a writable (or programmable) unit called a non-volatile memory page frame (or a flash page frame, for example, when referring to a NAND flash ). A non-volatile memory page frame is generally the smallest writable unit of non-volatile memory. In some embodiments and / or user scenarios, a nonvolatile memory page frame includes a number of user (non-error correcting code) data bytes and a size of metadata space reservation and error correction coding (e.g., ECC). Typical sizes of NAND flash page frames are 8 KB or 16 KB or 32 KB of user data, whereas typical sizes of logical block address mapping units are 4 KB or 8 KB. (While the term "user" data is used with respect to the non-volatile memory page frames, some non-volatile memory page frames store "system" data such as image data and / or checkpoint data. It is intended that user data generally refers to non-error correcting encoding portions of a non-volatile memory page frame The NAND flash page frames are organized in blocks, typically 128, 256, or 512 flash page frames per block the minimum size unit that can be deleted, and a NAND flash page frame is cleared before the page frame is able to be (re) written.

Some nonvolatile memories, such as NAND flash, have multiple planes and / or banks, and allow for "multi-plane" operations on a page frame and / or a block from each of access two or more levels in parallel (read or program or delete). The use of multi-level programming advantageously increases the write bandwidth, and causes the base unit of the writing to be a multi-level page frame rather than a single one-level page frame. The term non-volatile memory page frame (or non-volatile memory block), as used herein, represents either a single, non-volatile memory page frame (or block) or a multi-level, non-volatile Memory page frame (or block), depending on a way in which the non-volatile memory is used.

While the term "flash" transition layer (e.g., FTL, flash transition layer) is used herein, a concept of a transition layer between logical and physical addresses is applicable to multiple types of non-volatile memory. In one example, certain types of nonvolatile memory, such as a NAND flash, are erased in large units before being rewritten. In another example, some types of non-volatile memory are subject to wear, resulting in wear leveling (shifting data from more worn areas of the non-volatile memory to less worn areas). In yet another example, new forms of magnetic recordings in hard disk drives, such as shingled magnetic recording, have an inability to overwrite previously described data without deleting a much larger amount of other data. In various embodiments, nonvolatile memory types that are coarse-grained or that have a finite life benefit from a (flash) transition layer.

With reference to 1 For example, an illustration of selected details of one embodiment of mapping a logical block address to fixed size areas within a nonvolatile memory is shown. Some conventional flash transitions assume that a number of user data bytes are stored in a non-volatile memory page frame (eg non-volatile memory page frame) 100 is a power of two (and / or a multiple of the sector size) and divide the non-volatile memory page frame into an integer number of mapping units (each of which is in 1 shown as DATA). For example, with 16 KB of user data per nonvolatile memory page frame and 4 KB of imaging units, each nonvolatile memory page frame contains four mapping units, and the flash transition layer forms one address of each mapping unit (eg, LBA [M: U]. 110 ) to a corresponding nonvolatile memory page frame and one of the four mapping units within the respective nonvolatile memory page frames. That is, each map entry contains corresponding fields, such as:
nonvolatile_memory_page_address [n-1 ... 0], or
mapping_unit_within_nonvolatile_memory_page [k-1: 0],
where the element "nonvolatile_memory_page_address" designates a unique non-volatile page frame in the non-volatile memory and the element "mapping_unit_within_nonvolatile_memory_page" one of 2 sections with areas of mapping unit sizes of each non-volatile memory page frame (where k is the entire non-volatile memory Memory is fixed). A sub-page sub-page address 104 is a combination of "nonvolatile_memory_page_address" and "mapping_unit_within_nonvolatile_memory_page". For sector-based addressing (eg, with finer granularity than the mapping unit), low-order bits specify the logical block address (eg, LBA [U-1: 0] 111 ) a subsection, such as a number of sectors (eg, sector (s) within a sub-page frame) 113 ) within the imaging unit.

With reference to 2 For example, an illustration of selected details of one embodiment of mapping a logical block address to a variable size area that optionally spans nonvolatile memory page frames is shown. Flash transition layers of variable size (eg VTLEs, variable-size flash transition layers) conceptually form an address (or name or identifier) of a mapping unit (eg LBA [M: U] 110 ) to a variable size area of one or more non-volatile memory page frames because, for example, data of the mapping unit is compressed before being stored in the non-volatile memory and / or because, in another example, the mapping units are written by the host as sections of variable size, such as for an object store. However, make a full byte address 204 and a byte data length 206 In each map entry, the map entries are large compared to conventional flash transitions.

With reference to 3 For example, one illustration shows one embodiment of a non-volatile memory page frame that includes an integer number of read units. In some embodiments, variable size flash transition layers perform mapping of addresses (or names) of mapping units to physical addresses by using an epage (eg, error correction encoding pages) address, also referred to as a "read device" address. maps. An epage (or reading unit) is the minimum Size of data read from the nonvolatile memory and corrected by the error correction code used to protect the content of the nonvolatile memory. That is, each read unit contains a set of data and corresponding error correction code check bytes protecting that data. In some embodiments, a non-volatile memory page frame (such as the non-volatile memory page frame 100 ) or, in other embodiments, a group of non-volatile memory page frames, which are treated as a unit for purposes of writing, are divided into an integer number of read units, such as that in FIG 3 is illustrated.

In some types of non-volatile memory, such as a NAND flash, the data stored in the nonvolatile memory is a mixture of user data bytes and error correction code bytes (error correction information), and a higher level controller which accesses the nonvolatile memory determines which bytes and how many of the bytes of the nonvolatile memory are used for user data, and which bytes and how many of the bytes of the nonvolatile memory are used for the error correction code. In various embodiments, it is possible for the number of read units per non-volatile memory page frame to vary. For example, some portions of the nonvolatile memory use stronger error correction codes than others (by using more bytes in the nonvolatile memory page frame for the error correction encoding information) and have fewer read units and / or less usable data per reading unit. In another example, the number of read units per non-volatile memory page frame varies when the non-volatile memory is used because the program / erase cycles tend to weaken the non-volatile memory, resulting in more error correction. Codes result when the non-volatile memory becomes more used (more worn).

According to various embodiments, the error correction code used is one or more of the following: a Reed-Solomon (e.g., RS) code; a Bose Chaudhuri Hocquenghem (e.g., BCH) code; a turbo code; a hard decision parity check and / or a soft decision low density parity check parity check (e.g., LDPC); a polar code; a non-binary code; a code with a redundant array of inexpensive / independent hard disks (e.g., RAID, redundant array of / independent disks); an erasure code; any other error correction code; any combination of the foregoing, including compositions, concatenations and interleaving. Typical codeword sizes range from 512 bytes (plus error correction coding bytes) to 2176 bytes (plus error correction coding bytes). Typical numbers of error correction coding bytes range from only a few bytes to several hundred bytes. In some NAND flash devices with multi-level cells, error correction criteria are 40 bits per 1 KB of user data. In some multi-level cell NAND flash devices, code rates (a ratio of user bytes to total bytes in a read unit) are typically less than 94%. For example, an MLC NAND flash device has 17,664 byte Flash page frames, of which 16,384 bytes are nominally used to store mapped data and 1,280 bytes are "space" bytes that are normally used to store metadata and error correction coding Bytes are used. A recommended error correction coding strength for the MLC NAND flash device is 40 correction bits per 1 KB using 70 bytes of space bytes per 1K of the mapped data bytes.

With reference to 4 For example, an illustration of selected details of one embodiment of mapping a logical block address to a variable size area spanning one or more read units is shown. In some embodiments, a VFTL map forms the address (or name or identifier) of a variable-sized mapping unit (eg, compressed) (eg, LBA [M: U]. 110 ) to a number of read units included in each entry of the map as an address 404 a reading unit and a span (a number of reading units) 406 are shown. For example, the read units referred to by one of the mapping entries are in one or more (logically and / or physically) consecutive nonvolatile memory page frames, the number of read units being optional and / or optionally a non-volatile Exceed memory page frame. In various embodiments, which pack data within read units, an entry of the map alone is generally not sufficient to locate the associated data, because the entry designates only the readers and not a location of the data within the readers, and there will be more Imformation (such as headers within the referenced readers used to accurately locate the associated data.

In some embodiments, data is written to the nonvolatile memory page frames in a manner that is shared across multiple Chips of non-volatile memory is striped. Striping of write data across multiple chips advantageously allows for greater write bandwidth by writing only one nonvolatile memory page frame once per stripe in a given chip. A strip of blocks over multiple chips is called a redundancy block because in further embodiments and / or user scenarios RAID-like redundancy is added to a redundancy block basis using, for example, a redundant chip. In various embodiments, some blocks of the non-volatile memory are defective and are skipped during writing so that splitting into stripes occasionally has "holes" where one of the chips is skipped (rather than being written into the non-volatile memory page frames of a bad block (bad block) is written). In some embodiments, "sequential" non-volatile memory page frames are sequentially determined in a logical order determined by an order in which the nonvolatile memory page frames are written.

With reference to 5 For example, an illustration of selected details of an embodiment of a reader that includes message headers and data is shown. In various embodiments, the in 4 Figure 1 illustrates a criterion for locating the variable size data within the readers. As in 5 has each reading unit (eg 500 and 510 ) a set of zero or more headers 501 and the message headers are written into one or more read units, typically by hardware, when the variable size data is "tiled" (eg, packed tightly without wasted space). The message headers are interpreted, typically by other hardware, to extract the variable size data when the non-volatile memory is read. Variable size data is provided via a corresponding offset and a length in one of the message headers, a matching logical block address (or name), and optionally data and / or selective spanning reading units (such as the variable size data generated by "Data", "Start" and "Data, Continuation" are included, localized.

In various embodiments, the message headers are also used as part of recycling (eg, garbage collection and / or wear leveling) - including the logical block addresses (or equivalently the address of the mapping unit or names) in the headers allows for both finding the data variable size within a read unit and also provides a way to determine when a particular one of the read units is read, if the variable size data therein is still valid or has been overwritten (by looking up the logical block address or name in mapping and determining whether the map has still been referenced or updated to a physical address of the particular reader so that it references another of the readers). Consequently, it can be said that the message headers form a "reverse map" in that the message headers have imformation in combination with a physical location of the readers that is similar to that in the figure, but starting from the physical location of the logical Block address (or name) are assigned.

In some embodiments, special hardware for extracting data from the read units based on the logical block addresses (or names) is implemented to operate with high efficiency for statistical reads. The specialized hardware parses message headers within one or more read units to find the one of the headers with a given logical block address (or name) and then uses the appropriate length and offset to make the associated data variable To extract size. However, a hardware-based solution is costly (in terms of silicon area and power). For a low-end and / or mobile environment where sequential performance is more important than statistical performance, changes to the variable-size flash transition layer are implemented to reduce silicon area, conserve power, and achieve high sequential flow rates ,

In some embodiments, a variable-sized sequential-read optimized flash transition layer (eg, SRO-VTL) densely packs (densely packed) data into the non-volatile memory page frame (or, in some embodiments, a group of non-volatile memory page frames treated as a unit for purposes of writing) without any gaps for message headers within the data - all message headers being in a non-volatile memory area - Page frames are grouped together. In further embodiments, the message headers are not dynamically used to access data (as in some flash transition layers), but are only used for recycling and restoring, such as unexpected performance losses. Instead, the entries include the figure full imformation, which is used to find the variable size data (eg compressed) within the non-volatile memory page frames. The separation of headers and data into various areas of the non-volatile memory page frame results in readers that include only headers, readers that include a mix of headers and data (but as in FIG 6 , only one such read unit per nonvolatile memory page frame), and read units comprising only data.

While designed for low cost sequential read throughput, a variable size sequential read-optimized flash transition layer is capable of other metrics, such as statistical read I / O operations per second (eg, IOPs). random write input / output operations per second) and sequential write throughput to cut comparatively well. However, removing hardware help for functions such as VFTL-like packing data with message headers in each reader imposes a greater burden on a control processor. Alternatively, in some embodiments, a variable size sequential read-optimized flash transition layer uses hardware help for data tiling, data extraction, or other operations.

With reference to 6 A diagram of one embodiment of an SRO-VFTL nonvolatile memory page frame is shown. With reference to 7 FIG. 3 is an illustration of another embodiment of an SRO VFTL non-volatile memory page frame. A difference between the embodiments of the 6 and the 7 is whether the continuation data from a previous, non-volatile memory page frame 640 is before or after the message headers. Various embodiments and arrangements of the data within the non-volatile memory page frame are conceivable.

• – Nachrichtenköpfe, einschließlich eines Master-Nachrichtenkopfs 610, optional und/oder selektiv einen Redundanzblock-Nachrichtenkopf 620 (z.B. ein Nachrichtenkopf, der in dem ersten Seitenrahmen von jedem Block in einem Redundanzblock hinzugefügt ist), und null oder mehrere zusätzliche gepackte Nachrichtenköpfe 630. Jeder nicht-flüchtige Speicher-Seitenrahmen hat zumindest einen Zähler der Anzahl der nachfolgenden Nachrichtenköpfe und einen Zeiger (Pointer) dahin, wo Daten (die Nachrichtenköpfen zugeordnet sind) in dem nicht-flüchtigen Speicher-Seitenrahmen beginnen. In einigen Ausführungsformen können die Nachrichtenköpfe bitweise ausgerichtet sein, jedoch jeweils nur sechs Bytes (z.B. B) sein. Die Nachrichtenköpfe können umfassen, sind jedoch nicht beschränkt auf: Daten-Nachrichtenköpfe, Epoch-Nachrichtenköpfe und Auffüllungen (padding). Daten-Nachrichtenköpfe verwenden eine Adresse einer Abbildungseinheit und eine Länge. Der Versatz ist impliziert, weil alle Daten aufeinanderfolgend bzw. konsekutiv gepackt sind.
• – Optional und/oder selektiv Fortsetzungsdaten aus einem vorhergehenden, nicht-flüchtigen Speicher-Seitenrahmen (einem Bereich von Daten mit variabler Größe einer Abbildungseinheit) 640.
• – Gepackte (z.B. optional und/oder selektiv komprimierte) Daten von einer oder mehreren Abbildungseinheiten 650, um den nicht-flüchtigen Speicher-Seitenrahmen, von denen der letzte sich optional und/oder selektiv in einem nachfolgenden, nicht-flüchtigen Speicher-Seitenrahmen fortsetzt.
• – Optionale Blindgruppen (padding) am Ende des nicht-flüchtigen Speicher-Seitenrahmens (enthalten in 650). Im verschiedenen Ausführungsformen werden die Daten byteweise gepackt (z.B. keine Löcher), jedoch am Ende des nicht-flüchtigen Speicher-Seitenrahmens möglicherweise aufgefüllt, wenn er hoch komprimiert ist (z.B. zu viele Nachrichtenköpfe). Auffüllen (padding) wird beispielsweise verwendet falls: (i) der letzte Abschnitt von Daten mit variabler Größe, der dem nicht-flüchtigen Speicher-Seitenrahmen hinzugefügt worden ist, weniger unbenutzte Bytes als eine Größe eines Nachrichtenkopfes hinterließ (so dass ein neuer Nachrichtenkopf nicht eingefügt werden konnte, um einen anderen Abschnitt von Daten mit variabler Größe zu beginnen), (ii) optional und/oder selektiv, eine vorbestimmte Anzahl von Nachrichtenköpfen pro nicht-flüchtigem Speicher-Seitenrahmen überschritten wird (so dass die Anzahl der Abbildungseinheiten, die in dem nicht-flüchtigen Speicher-Seitenrahmen gespeichert sind, durch die vorbestimmte Anzahl der Nachrichtenköpfe begrenzt sind und nicht durch eine Größe der Daten in den Abbildungseinheiten).

According to various embodiments, a non-volatile memory page frame includes one or more of the following:

• - Message headers, including a master message header 610 , optionally and / or selectively, a redundancy block header 620 (eg, a message header added in the first page frame of each block in a redundancy block), and zero or more additional packed message headers 630 , Each non-volatile memory page frame has at least a count of the number of subsequent message headers and a pointer to where data (associated with message headers) begin in the non-volatile memory page frame. In some embodiments, the message headers may be bit-aligned, but each only six bytes (eg, B). The message headers may include, but are not limited to: data headers, epoch headers, and padding. Data message headers use an address of an imaging unit and a length. The offset is implied because all the data is packed consecutively or consecutively.
• Optional and / or selective continuation data from a previous non-volatile memory page frame (a range of variable size data of an imaging unit) 640 ,
• - Packed (eg optionally and / or selectively compressed) data from one or more imaging units 650 to the non-volatile memory page frame, the latter of which optionally and / or selectively continues in a subsequent non-volatile memory page frame.
• Optional padding at the end of the non-volatile memory page frame (included in 650 ). In various embodiments, the data is packed in bytes (eg, no holes) but may be padded at the end of the non-volatile memory page frame if it is highly compressed (eg, too many headers). Padding is used, for example, if: (i) the last section of variable size data added to the non-volatile memory page frame left fewer unused bytes than a message header size (so a new message header is not inserted (ii) optionally and / or selectively, a predetermined number of message headers per non-volatile memory page frame is exceeded (such that the number of mapping units included in the non-volatile memory page frames are limited by the predetermined number of message headers and not by a size of the data in the mapping units).

In some embodiments, retrieval and / or recycling (eg, garbage collection) with a sequentially read-optimized variable-size flash transition layer is advantageously capable of only one header section of each of the non-volatile memory page frames read and / or error correcting and / or checking, and not every reading unit, as in a non-sequential read-optimized variable-size flash transition layer. If the recycling determines that data of a non-volatile page storage frame can be rewritten, then that data may also be read and may also be error-corrected become. In some embodiments, an entire non-volatile memory page frame is read for recycling, however, only the header section is error-corrected until a determination is made that some data in the non-volatile memory page frame should be recycled.

In various embodiments, a number of message headers per non-volatile memory page frame are limited to limit a number of read units per nonvolatile memory page frame that can be read to ensure that all message headers are read from the non-volatile memory have been. In the embodiment of the 6 Only a number of read units sufficient to hold the maximum number of headers is read. In the embodiment of the 7 An additional number of read units are read to account for a largest amount of data completed by a previous non-volatile memory page frame (eg, continuation data 640 ). The embodiment of the 7 allows a number of read units to complete the data from a previous non-volatile memory page frame (eg, continuation data 640 ), which are to be determined from the associated map entry, because the number of bytes in the completion of the data is based on the corresponding offset and the length of the associated map entry, and the number of bytes of user data (not error correction code) in the preceding non-volatile memory page frame is determinable.

Furthermore, the only message headers prior to completing the data are the optional redundancy message header (which exists only in specified non-volatile memory page frames, such as the first page frame in each block) and the master message header (which is not in each -volatile memory page frame is always present). In the embodiment of the 6 In order to read the completion of the data without having to access the non-volatile memory twice, the maximum number of headers is assumed to be present (or the entire non-volatile memory page frame is read).

In some embodiments, the variable size sequential read-optimized flash transition layer uses a single-level map having a plurality of map entries. In other embodiments, the variable size sequential-read optimized flash transition layer uses a multi-level map, such as a 2-level map, including a first level map (eg FLM, first-level map) refers to a two-level map (eg, SLM, second-level map) page frame, where each of the two-level map page frames includes a plurality of leaf-level map entries. In further embodiments, the multi-level map has more than two levels, such as three levels. In some implementations and / or user scenarios, the use of a multi-level map allows only a relevant (eg, in use) portion of the map to be stored in local memory (eg, on-chip SRAM of a solid-state drive controller or local DRAM a host) can be stored (eg, cached), which reduces overhead for maintaining or maintaining the map. For example, if typical usage patterns have 1 gigabyte (eg, GB) of logical block address space that is active at any one time, then only a portion of the map sufficient to access the active 1 GB portion of the logical block address space becomes one quick access stored locally, versus being stored in the non-volatile memory. References to outside the active portion of the logical block address space fetch requested portions of one or more levels of the multi-level map from the non-volatile memory, optionally and / or selectively replacing other locally stored portions of the map.

Each of the leaf-level map entries is associated with or corresponds to an address (or name) of one or a plurality of mapping units. In one example, a logical block address is converted to an address of an imaging unit, such as by removing zero or more least significant bits (eg LSBs) of the logical block address and / or adding a constant to the logical block address for alignment purposes, and the address of the mapping unit is looked up in the figure to determine a corresponding entry in the map. In another example, a name in a hash table (or other associative data structure) is looked up to determine a unique identifier used as the address of the mapping unit.

With reference to 8th An illustration of details of one embodiment of various types of message headers is shown. In the example of the 8th the message headers have been formatted so that everyone fits in six bytes. According to various embodiments, the different types of message headers are one or more of the following: all of an equal size; optional and / or selective of different sizes; each includes a corresponding field that specifies a size of the message header; varying in size in various non-volatile memory page frames; and any combination of the foregoing.

• – Daten-Nachrichtenköpfe (810), die Imformation angeben, die einem Datenabschnitt von variabler Größe zugeordnet sind. In einigen Ausführungsformen beginnen Daten, die einem Daten-Nachrichtenkopf zugeordnet sind, in einem selben nicht-flüchtigen Speicher-Seitenrahmen wie dem, wo der Daten-Nachrichtenkopf auftritt. In weiteren Ausführungsformen und/oder Nutzungsszenarien beginnen alle zugeordneten Daten in einem nachfolgenden, nicht-flüchtigen Speicher-Seitenrahmen, falls ein nicht-flüchtiger Speicher-Seitenrahmen nur für einen Daten-Nachrichtenkopf verbleibenden Raum aufweist.
• – Abbildungs-Nachrichtenköpfe, wie etwa Zwei-Niveau-Abbildung (z.B. SLM)-Nachrichtenköpfe (820). Die Zwei-Niveau-Abbildungs-Nachrichtenköpfe umfassen einen Erst-Niveau-Abbildungs-Imdex (z.B. FLMI, first-level map index) um anzuzeigen (wie etwa für ein Recycling und/oder ein Wiedererlangen einer Zwei-Niveau-Abbildung), welcher der die Zwei-Niveau-Abbildungs-Seitenrahmen gespeichert wird.
• – Log/Überprüfungspunkt (log/checkpoint)-Nachrichtenköpfe (820). Log/Überprüfungspunkt-Nachrichtenköpfe geben Daten an, die zum Recycling, zum Wiedererlangen, zur Fehlerbehandlung, zum Debugging oder für andere spezielle Bedingungen verwendet werden.
• – Epoch-Nachrichtenköpfe (830) werden als Teil der Wiedererlangung, zum Zuordnen bzw. Assoziieren von Daten mit entsprechender Abbildungs-Checkpoint-Imformation verwendet. Typischerweise gibt es mindestens einen Epoch-Nachrichtenkopf pro nicht-flüchtigem Speicher-Seitenrahmen.
• – Master-Nachrichtenköpfe (870) werden einmal pro nicht-flüchtigem Speicher-Seitenrahmen verwendet, um Imformation hinsichtlich einer Anzahl von Nachrichtenköpfen in dem nicht-flüchtigen Speicher-Seitenrahmen bereitzustellen, und darüber, wo Nicht-Nachrichtenkopf-Daten innerhalb des nicht-flüchtigen Speicher-Seitenrahmens beginnen. Verschiedene Techniken bestimmen einen Beginn von Nicht-Nachrichtenkopf-Daten, wie in den Ausführungsformen der 6 und 7 dargestellt.
• – Redundanzblock-Nachrichtenköpfe (880) werden in bestimmten nicht-flüchtigen Speicher-Seitenrahmen verwendet, wie etwa im ersten nicht-flüchtigen Speicher-Seitenrahmen in jedem Block in einem Redundanzblock.
• – Andere Arten von Nachrichtenköpfen (840), wie etwa Padding-Nachrichtenköpfe, Überprüfungspunkt-Nachrichtenköpfe, die größere Längen unterstützen, usw.

According to various embodiments, the headers in the non-volatile memory page frame include one or more of the following:

• - Data message headers ( 810 ) indicating information associated with a data section of variable size. In some embodiments, data associated with a data message header begins in a same non-volatile memory page frame as where the data message header occurs. In further embodiments and / or usage scenarios, all associated data begins in a subsequent non-volatile memory page frame if a non-volatile memory page frame has only space remaining for a data message header.
• Image message headers, such as two-level image (eg, SLM) message headers ( 820 ). The two-level map headers include a first-level map index (eg, FLMI, first-level map index) to indicate (such as for recycling and / or retrieving a two-level map) that the the two-level picture page frame is stored.
• - log / checkpoint (log / checkpoint) message headers ( 820 ). Log / Checkpoint message headers indicate data used for recycling, retrieval, error handling, debugging, or other specific conditions.
• - Epoch message headers ( 830 ) are used as part of retrieval, associating or associating data with corresponding map checkpoint information. Typically, there is at least one epoch header per non-volatile memory page frame.
• - Master message headers ( 870 ) are used once per non-volatile memory page frame to provide information regarding a number of headers in the non-volatile memory page frame and where non-header data begins within the non-volatile memory page frame. Various techniques determine the beginning of non-message header data, as in the embodiments of FIGS 6 and 7 shown.
• - redundancy block message headers ( 880 ) are used in certain non-volatile memory page frames, such as in the first non-volatile memory page frame in each block in a redundancy block.
• - Other types of message headers ( 840 ), such as padding headers, checkpoint headers that support longer lengths, etc.

In some embodiments, some message headers include a TYPE field to provide multiple subtypes of message headers. In various embodiments, some message headers include a LEN (length) field that includes a length of the data associated with the message header. In various embodiments, instead of or in addition to a LEN field, some message headers include an OFFSET field (not shown) that includes an offset (within the non-volatile memory page frame) to the end of data associated with the message header , (In some embodiments, when the last of the variable size data sections spans a non-volatile memory page frame, the OFFSET is an offset within a subsequent non-volatile memory page frame or a number of bytes within the subsequent non-volatile one Memory page frame.) In general, only either a LEN field or an OFFSET field is implemented because the data sections of variable size packed together with no wasted space, the start position and end position of each of the data Variable size sections in a non-volatile memory page frame are implied by the start position of the first variable size data piece in the non-volatile memory page frame (eg, immediately after the headers as in FIG 7 ) and the last of the LEN or OFFSET fields.

• – eine physikalische Adresse eines nicht-flüchtigen Speicher-Seitenrahmens,
• – ein Versatz innerhalb des nicht-flüchtigen Speicher-Seitenrahmens (z.B. OFFSET) auf ein Datenobjekt mit variabler Größe,
• – eine Länge des Datenobjekts mit variabler Größe (z.B. LEN_M128), und
• – andere Steuerungsinformation.

With reference to 9 Figure 12 is an illustration of selected details of one embodiment of a map entry 900 shown. According to various embodiments, the entries of the figure include one or more of the following:

• A physical address of a non-volatile memory page frame,
• An offset within the non-volatile memory page frame (eg OFFSET) to a variable size data object,
• A length of the variable size data object (eg LEN_M128), and
• - other control information.

For example, in some embodiments, the length is encoded by being offset so that a value of zero corresponds to a specified, minimum length. For example, if the minimum length is 128 bytes, then a LEN_M128 value of zero represents 128 bytes. In further embodiments, data compressed to less than the specified minimum length becomes padded so that they have at least the specified minimum length in size.

In various embodiments, the SRO-VFTL mapping entries are larger than VFTL map entries because the SRO-VFTL map entries store a full offset and byte lengths of corresponding data. Accordingly, reducing a size of the map entries when stored in the non-volatile memory may be advantageous. In a typical usage, data is often read and written sequentially, at least with some granularity and / or an average number of sequential mapping units that is greater than one. An image entry compression format that takes advantage of the sequential nature of writing is also relatively inexpensive to implement and produces a high image compression rate. Compression of mapping entries is further favored by sequential-written data going into the same non-volatile memory page frames until a limit of non-volatile memory page frame is exceeded.

With reference to 10 an illustration of selected details of one embodiment of various compressed mapping entries is shown. The various mapping entries include uncompressed ( 1010 ) having a same non-volatile memory page frame address as a previous mapping entry ( 1020 ); those that have the same nonvolatile memory page frame address as the previous mapping entry and that starts at an offset where the previous data ended ( 1030 ); those having a same nonvolatile memory page frame address as the previous mapping entry starting at an offset where the previous data ended; and those that have the same length as the previous mapping entry ( 1040 ).

In some implementations having a multi-level map, a cache of map page frames is maintained at a low level (such as leaf level). The cached map page frames are in an uncompressed form, providing fast access by the processor (such as a host or control processor of a solid state drive controller). When map page frames are moved (such as from a nonvolatile memory or dynamic random access memory (e.g., DRAM)) into the cache, then the map page frames are decompressed. If the memory page frames are flushed from the cache (such as due to being changed), then the map page frames are compressed for storage (such as in the non-volatile memory). According to various embodiments in which a DRAM is used to reduce latency for storing some or all of the map page frames in the dynamic random access memory, the map page frames in the dynamic random access memory become one or more of the following forms stored: compressed form; non-compressed form; a selectively compressed or uncompressed form; and an immediate table used to access the compressed versions of the variable size map page frames in the dynamic random access memory.

In some embodiments, host write data of a host write command is optionally and / or selectively compressed when host write data arrives at a controller of a solid state drive, and is first-in-first-out (eg, FIFO) -like manner stored in a local memory (such as an on-chip memory). For example, in some embodiments, the host memory data is placed in a unified buffer (eg, UBUF, unified buffer, see FIG 11A ), along with firmware data structures, flash statistics, portions of the map (such as a cache containing one or more page frames of the map), read data from the non-volatile memory, the recycle read data, headers from Data written to the non-volatile memory, software code, firmware code and other uses written. In various embodiments, one or more dedicated memories are used for different local storage criteria in the solid state drive.

In some embodiments, host write data of a host write command is optionally and / or selectively compressed in a host before being sent to a controller of a solid state drive. For example, database entries are compressed by a host database before being written to an input / output device.

In various embodiments, with each mapping unit of data arriving from the host, a control processor of the solid-state drive (eg, the central processing unit, CPU) is integrated into 11A ) notifies, via one or more of the following: a corresponding address of an imaging unit, a corresponding local memory address, wherein data associated with the corresponding address of the imaging unit is stored, and / or a corresponding length of each mapping unit of host data of variable size (eg compressed). The control processor is capable of determining an order of writing non-volatile memory page frames and a total number of non-error correction encoding bytes available in each of the non-volatile memory page frames.

According to the total number of non-error correction coding bytes available in a given non-volatile memory page frame, the control processor is capable of generating a number of message headers and a data set that is in the given non-volatile Memory page frame is placed to determine. For example, the control processor accumulates headers for the given non-volatile memory page frames (and keeps track of a number of headers of headers that have been used until then) and sequentially adds data from variable size headers and headers to the given non-volatile memory. Add page frames until the given non-volatile memory page frame is full. If the given non-volatile memory page frame is full, then it is possible that a last portion of data of a last of the mapping units added to the given non-volatile memory page frame will not fit into the given non-volatile memory Memory page frame fits and as a data completion section of a subsequent, non-volatile memory page frame (eg, continuation data 640 ), thereby reducing the total number of non-error correction coding bytes available in the subsequent non-volatile memory page frame for new message headers and data.

In some embodiments, it is possible for zero or more non-volatile memory page frames to be filled with host write data at a particular time, and it is possible for zero or more non-volatile memory page frames to be filled with recycled data , For example, at least two bands (eg, FIFO-like series of redundancy blocks) may be filled, one band with "hot" data (eg, fresh from the host) and the other band with "cold" (eg, recycled) data, and zero or more Nonvolatile memory page frames that are worth the space are directed from a buffer in each band. Continuing the example, in various embodiments, the host write data is optionally and / or selectively enabled to be addressed directly to either the hot band or the cold band, and the recycled data becomes optional and / or selective being able to be directed into either the hot band or the cold band.

In some embodiments, the control processor is capable of converting the series of corresponding mapping unit addresses, local memory addresses, and corresponding lengths into one or more of the following: a series of message headers stored in a non-volatile memory page frame as a message header Section of the non-volatile memory page frame is to be described; a first start address and a first length of a sequential portion of the local memory to be written in the non-volatile memory page frame as a user data portion of the non-volatile memory page frames, the user data portion of the non-volatile memory Memory page frame includes at least a portion of at least one imaging unit, a second start address and a second length of a sequential portion of the local memory to be written in a subsequent non-volatile memory page frame, the user data completion section a Data section of an imaging unit comprises or is empty; a number of zero or more padding bytes to be written in the non-volatile memory page frames, the padding bytes being used, for example, when the user data completion section is empty and the non-volatile memory page frame is not is full. Advantageously, the control processor is able to simply convert the series of corresponding addresses of the mapping units, the corresponding local memory addresses and the corresponding lengths into the series of message headers by reformatting and a small number of random access memories (eg direct memory access). To generate the sections (the series of message headers, a completion section of a previous nonvolatile memory page frame, the user data section, and any padding bytes) into the non-volatile memory.

In various embodiments, the compression of the host write data is optionally and / or selectively enabled. In one example, the imformation of the host write command optionally enables compression. In another example, compression is selectively enabled as a function of a logical block address (or identifier) of the host write command. In yet another example, compression is selectively disabled when compression of the host write data does not decrease a size of the host write data. If compression is not enabled, the host write data is stored uncompressed. According to various embodiments, entries of the map indicate whether the corresponding data is compressed or uncompressed, by one or more of more of the following: a corresponding bit in each entry of the figure; and / or a value of the length stored in each map entry. For example, if the mapping units are 4 KB, then a 4 KB length in a mapping entry indicates that associated data of the map entry is uncompressed, whereas a length of less than 4 KB indicates that the associated data is compressed. In some embodiments and / or user scenarios, a message header associated with the optionally and / or selectively compressed stored version of host write data specifies whether the stored host write data is compressed or not.

In some embodiments, data is recycled by selecting a redundancy block to be recycled; nonvolatile memory page frames of the redundancy block are read in an order in which the nonvolatile memory page frames have been written; only read units containing headers of the non-volatile memory page frames are processed; a logical block address (or, equivalently, an address of an imaging unit or name) of each message header that is a message header in the map is looked up to determine if the data is still valid; and if the data is still valid, appropriate new message headers and DMA commands are constructed to assemble the data to be recycled as part of a new non-volatile memory page frame. The new non-volatile memory page frame is then written to the non-volatile memory.

With reference to 11A Fig. 12 is an illustration of selected details of an embodiment of a controller 1100 shown a solid-state drive. In some embodiments, the controller is 1100 The solid state drive is capable of implementing one or more flash transition layers or portions thereof, such as by implementing the flash transition layer in cooperation with a host. In various embodiments, the controller 1100 be implemented as one or more integrated circuits.

As in 11A is an input / output receiver, such as a SERDES (eg, serializer-deserializer) controller 1100 of the solid-state drive via an external interface 1111 connected to a host. A host interface (eg, HIF, host interface) receives commands through the SERDES, such as read and write commands, receives write data, and sends that data. The commands are sent to a central processing unit via a shared memory (eg OpRAM). The central processing unit interprets the instructions and controls other portions of the solid-state drive controller over the shared memory. For example, the central processing unit communicates DMA commands and receives responses from various data path transmitting and receiving devices, such as the host data path receive segment (eg, HDRx, host data path receive segment) or a flash data path transfer Segment (eg FDTx, flash data path transmit segment) over the shared memory.

Write data from the host interface is transferred via a host data path receive segment (eg, HDRx) to a unified buffer (eg, UBUF). In various embodiments, the host data path segment includes logic for optionally and / or selectively compressing and / or encrypting the host write data. The optionally and / or selectively compressed and / or encrypted host write data is then extracted from the unified buffer to the non-volatile memory via a flash data path transfer segment and a generic flash interface (eg, GAFI, generic flash interface). In various embodiments, the flash data path transfer segment includes logic to perform encryption and / or scrambling and / or error correction coding. In response to host read commands, data is read from the nonvolatile memory via the generic flash interface and sent to the unified buffer via a flash data path receive segment (eg, FDRx). In various embodiments, the flash data path receive segment includes error correction decoding and / or encryption and / or de-scrambling. In other embodiments, a separate error correction decoder (eg, LDPC-D for implementing LDPC codes) is capable of operating on "raw" data stored in the unified buffer by the flash data path receive segment , Decoded read data in the unified buffer is then sent to the host interface via a host data path transfer segment (eg HDTx). In various embodiments, the host data path transfer segment includes logic to optionally and / or selectively decrypt and / or decompress the decoded read data. In some embodiments, a RAID-type and a soft-decision processing unit (eg, RASP) processing unit are configured to generate RAID-like redundancy to host write data and / or system data stored in the non-volatile memory are stored, in addition to protect and / or soft- To execute decision processing operations for use with the LDPC-D.

According to various embodiments, the solid state drive controller is configured to implement none, some, all, or portions of one or more flash transition layers. In one example, a higher level imaging section of the flash transfer layer is executed on the host, and a lower level imaging section of the flash transition layer is executed in the controller of the solid state drive. In another example, the controller of a solid state drive sends and receives abstracted physical address of a device, such as read device addresses and spans, to and from the host, and the host forms logical block addresses (or names) on the abstracted physical addresses of the units. The controller of the solid state drive is configured to locate specific data associated with the abstracted physical device addresses via an identifier of the specific data, such as a logical block address (or name), stored in a message header. In yet another example, mapping from a logical block address (or name) in the host generates a nonvolatile memory page frame address, an offset within the non-volatile page frame, and a byte length. The controller of the solid state drive is configured to determine a number of read units to be accessed in the nonvolatile memory to retrieve the specified data within one or more nonvolatile memory page frames. Advantageously, in one or more of the examples, details of error correction coding (eg, a number of user data bytes per non-volatile memory page frame or a size of read units) are maintained by the controller of the solid state drive, which increases the overhead in the Host reduced.

With reference to 11B An illustration of selected details of an embodiment of a data path segment is shown. A data path segment 1190 For example, the host data path receive segment or the flash data path transfer segment of the 11A represent. The data path segment 1190 includes a read sequencer 1130 , a write-sequencer 1140 and zero or more data path units (eg, DPUs, data path units). 11B shows an example with two data path units 1150-1 and 1150-2 ,

The read-expiry control 1130 is with the OpRAM (see 11A ) to receive control information specifying the data to be read / accessed. For example, the information may be an address and / or length in the unified buffer or a command or host interface or generic flash interface, and may specify commands to be merged with the data. The read-expiry control 1130 is also with a reading device 1110 connected to read / access the data, such as from the UBUF, the host interface or the generic flash interface. The read-expiry control 1130 is adapted to provide a nested stream of read data and instructions, according to the requests received from the OpRAM, to zero or more data path units 1150-1 and 1150-2 and a write-flow control 1140 to send.

The write sequence control 1140 is designed to handle a nested stream of data and commands from the read flow control 1130 has been sent to receive. The write sequence control 1140 is with a writing device 1120 for writing the data, such as to the UBUF, the host interface or the generic flash interface. The data is processed according to the instructions in the of the write sequence control 1140 received data stream (such as the instructions specifying an address and / or length). The write sequence control 1140 is also with the OpRAM (see 11A ) to send status information about data that has been written in accordance with the received commands. For example, status information is written to the OpRAM to indicate the completion of writing a particular portion of the data stream (eg, a 4 KB mapping unit).

• – eine Codierungseinheit, die einen Befehl empfängt, der den Codierungsschlüssel (Imitialisierungs-Vektor), das zur Verschlüsselung zu verwenden ist, und die nachfolgenden Daten gemäß dem Codierungsschlüssel (salt) verschlüsselt. In weiteren Ausführungsformen umfasst der Befehl eine Spezifizierung eines Codierungsschlüssels;
• – eine Entschlüsselungseinheit, die einen Befehl empfängt, der den Decodierungsschlüssel (Imitialisierungs-Vektor) enthält, das für die Entschlüsselung zu verwenden ist, und die folgenden Daten gemäß dem Decodierungsschlüssel (salt) entschlüsselt. In weiteren Ausführungsformen umfasst der Befehl auch eine Spezifizierung eines Dekodierungsschlüssels;
• – eine Komprimierungseinheit, die einen Befehl empfängt, der einen Beginn einer Kompressions-Einheit (z.B. Abbildungseinheit)-Grenze anzeigt, und die folgenden Daten komprimiert. Im verschiedenen Ausführungsformen umfasst der Befehl auch eine oder mehrere einer Menge von Daten, die als eine Einheit zu komprimieren sind, eine Art der Kompression, eine maximale Laufzeit für die Kompression, und andere Kompressionssteuerungen;
• – eine Dekomprimierungseinheit, die einen Befehl empfängt, der einen Beginn einer Kompressions-Einheits-Grenze angibt, und die folgenden Daten dekomprimiert. Im verschiedenen Ausführungsformen umfasst der Befehl auch eine oder mehrere Mengen von Daten, die als eine Einheit zu dekomprimieren sind, eine erwartete Größe der dekomprimierten Daten, einen Typ der Dekompression, eine maximale Laufzeit für die Dekompression und andere Dekomprimierungssteuerungen;
• – eine Überprüfungseinheit für zyklische Redundanz (z.B. CRC, cyclic redundancy check), die einen Befehl empfängt, der den Überprüfungsschlüssel (Imitialisierungs-Vektor) umfasst, der zu verwenden ist, einen zyklischen Redundanz-Überprüfungs-Wert zu berechnen und einen zyklischen Redundanz-Überprüfungs-Wert über die folgenden Daten gemäß dem Überprüfungsschlüssel (salt) berechnet. In weiteren Ausführungsformen ist der Befehl dazu ausgelegt, optional und/oder selektiv die zyklische Redundanz-Überprüfungs-Einheit in die Lage zu versetzen, einen vorher berechneten zyklischen Redundanz-Überprüfungs-Wert an die vorher empfangenen Daten, die von dem zyklischen Redundanz-Überprüfungs-Wert abgedeckt sind, anzuhängen;
• – eine Fehlerkorrektur-Codierungs- und/oder Dekodierungs-Einheit, die einen Befehl empfängt, der eine Code-Rate umfasst und/oder die folgenden Daten gemäß einem Fehlerkorrektur-Code dieser Code-Rate zu decodieren. In weiteren Ausführungsformen umfasst der Befehl optional und/oder selektiv zusätzliche Steuerungen, wie etwa Soft-Decision-Verarbeitungs-Imformation, eine maximale Anzahl von zu verwendenden Iterationen und andere Codierer und/oder Decodierer-Steuerungsinformation.

The data path units 1150-1 and 1150-2 are designed to convert the data while between the read-out control 0 and the write-flow control 1140 to run. From the read-flow control 1130 Commands generated in the data stream are optionally and / or selectively directed to one or more of the data path units 1150-1 and 1150-2 or the write-sequence control 1140 to be received. Examples of data path units 1150-1 and 1150-2 include:

• An encoding unit which receives a command which encodes the encryption key (initialization vector) to be used for encryption and the subsequent data according to the encryption key (salt). In further embodiments, the command includes a specification of an encryption key;
• A decryption unit which receives a command containing the decryption key (de-initialization vector) to be used for the decryption and decrypts the following data according to the decryption key (salt). In further embodiments, the command also includes a specification of a decryption key;
• A compression unit which receives a command indicating a start of a compression unit (eg, imaging unit) boundary and compresses the following data. In various embodiments, the command also includes one or more of a set of data to be compressed as a unit, a type of compression, a maximum run time for compression, and other compression controls;
• A decompression unit which receives a command indicating a beginning of a compression unit boundary, and decompresses the following data. In various embodiments, the command also includes one or more sets of data to be decompressed as a unit, an expected size of the decompressed data, a type of decompression, a maximum runtime for decompression, and other decompression controls;
• A cyclic redundancy check unit (eg, CRC, cyclic redundancy check) which receives a command including the check key (initialization vector) to be used, a cyclic redundancy check value, and a cyclic redundancy check Value is calculated over the following data according to the verification key (salt). In further embodiments, the command is adapted to optionally and / or selectively enable the cyclic redundancy check unit to apply a previously calculated cyclic redundancy check value to the previously received data provided by the cyclic redundancy checker. Value are covered, attach;
• An error correction coding and / or decoding unit receiving a command comprising a code rate and / or decoding the following data according to an error correction code of that code rate. In further embodiments, the command optionally and / or selectively includes additional controls, such as soft-decision processing information, a maximum number of iterations to use, and other encoders and / or decoder control information.

In an exemplary operation, in response to receiving a write command from a host, a command list for read-flow control of the host data path receive segment is constructed by the central processing unit, and according to the command list, the host data path is Receive segment is enabled to transfer write data of the write command from the host to the unified buffer via the host interface. A data path unit in the host data path receive segment is configured to compress the write data before the (compressed) write data is written to the unified buffer. Several (compressed) imaging units are designed to be tightly packed in the unified buffer without tiled space. The central processing unit is notified of the location and size of each of the (compressed) mapping units by the status information written in the OpRAM (via a write-flow control of the host data path receive segment). The central processing unit is configured to construct headers according to the status information and to determine a set of the headers and the (compressed) mapping units that fill a non-volatile memory page frame. The central processing unit is further configured to build a command list for a read-flow control of the flash data path transfer segment to transfer the non-volatile memory page frame of headers and data to the non-volatile memory. A data path unit in the flash data path transfer segment is configured to encode the headers and data sent to the non-volatile memory, and additional bytes for error correction coding protection for each of a plurality of read units add. Upon receiving the status from a write-flow control of the flash data path transfer segment that the writing of the NVM page frame is complete, space used in the unified buffer by the (compressed) imaging units becomes reusable ( reusable).

In another exemplary operation, in response to receiving a read command from a host, a command list for a read-run control of the flash data path receive segment is constructed by the central processing unit, and according to the command list, the flash Datapath receive segment is enabled to receive one or more read units read from the non-volatile memory into the unified buffer via the generic flash interface. In some embodiments, a data path unit in the flash data path receive segment is configured to use the data sent to the non-volatile memory using the to decode additional bytes for error correction coding protection with each reading unit. In other embodiments, an error correction via a separate data path segment (eg LDPC-D in 11A ). The central processing unit is characterized by receiving (corrected) data in the unified buffer by receiving a status from a write-flow control of the flash data path receive segment or, in other embodiments, a write-trace control of the LDPC-D data path segment notified. The central processing unit is further configured to construct a command data path for the host data path transfer segment to transfer at least a portion of the corrected data from the unified buffer to the host via the host interface. A data path unit in the host data path transfer segment is configured to decompress the corrected data before transferring it to the host. Upon receiving a status from a write-flow control of the host data-path transmission segment that the corrected data has been successfully transmitted, space used in the unified buffer by the corrected data is re-requestable (reusable) ,

With reference to 11C an illustration of selected details of various embodiments of the system according to one embodiment of the invention is shown. The embodiments comprise one or more instances of the controller of a solid state drive 1100 of the 11A , Multiple solid-state drives 1101a - 1101n generally include control devices 1100a - 1100N for solid state drives using nonvolatile memories 1199a - 1199n via device interfaces 1190a - 1190n , respectively, are connected. The figure depicts various classes of embodiments: a single solid-state drive directly connected to a host 1102 connected to a variety of solid state drives, each with corresponding external interfaces 1111a - 1111n directly with the host 1102 and one or more solid-state drives that have various interconnect elements indirectly with the host 1102 are coupled.

As an exemplary embodiment of a single solid-state drive coupled directly to a host is an imprint of the solid-state drive 1101a directly with the host 1102 via an external interface 1111a (eg, a switch / structure / intermediary controller 1103 omitted, bypassed or traversed) is coupled. As an example embodiment of a plurality of solid state drives, each of which is directly coupled to a host via corresponding external interfaces, each of a plurality of solid state drive instances is 1101a to 1101n , respectively, via a corresponding imprint of an external interface 1111a - 1111n (eg, a switch / structure / intermediary controller 1103 omitted, bypassed or traversed) directly to the host 1102 is coupled. As an example embodiment of one or more solid state drives indirectly coupled to a host via various interconnect elements, each is one or more instances of the solid state drive 1101 , respectively, indirectly with the host 1102 coupled. Each indirect coupling is via a corresponding instance of the external interfaces 1111a - 1111n connected to a switch / structure / intermediate controller 1103 and an intermediate interface 1104 coupled with the host 1102 coupled.

Some of the embodiments that comprise the switch / structure / intermediary controller 1103 include, also include a card memory 1112c that has a memory interface 1180 is coupled and over the solid state drives 1101a - 1101n and / or over the host 1102 is accessible. In various embodiments, this is one or more solid state drives 1101a - 1101n , the switch / structure / intermediate controller 1103 and / or the card memory 1112c in a physically identifiable module, a card or a pluggable element (eg input / output card 1116 ). In some embodiments, a solid state drive is equivalent 1101a - 1101n (or variations thereof) to a serial attached SCSI (eg, SAS) drive or to a serial advanced technology port (eg SATA) drive with an imitator acting as the host 1102 works, is coupled.

The host 1102 is designed to use different elements of the host software (SW) 1115 such as different combination of operating system (eg OS, operating system) 1105 , a driver 1107 , an application 1109 and a multi-device management software 1114 , A dotted arrow 1107d is representative of bi-directional communication between the host software and the input / output device (eg, data sent to / received from one or more of the solids of the solid state drives 1101a - 1101n and from / to any one or more of the operating systems (OS) 1105 over the driver 1107 , and the application 1109 either via the driver 1107 or directly as a (eg PCI) virtual function (eg VF)).

In some embodiments and / or user scenarios, the host software includes 1115 some, all, or parts of a flash transition layer containing the solid state drives 1101a - 1101n is used. In one example and in various embodiments, the driver implements 1107 at least a portion of the flash transitional layers containing the solid state drives 1101a - 1101n be used. In another example and in various embodiments, the multi-device management software implements 1114 at least a portion of the flash transitional layers containing the solid state drives 1101a - 1101n be used.

The operating system 1105 includes and / or is designed to operate with, drivers (which are conceptualized by the driver 1107 shown) for interfacing with the solid state drives 1101a - 1101n , Different versions of Windows (eg 95, 98, ME, NT, XP, 200, Server, Vista, 7 and 8), different versions of Linux (eg Red Hat, Debian and Ubuntu) and different versions of MacOS (eg 8, 9 and X) are examples of the operating system 1105 , In various embodiments, the driver standards and / or the generic driver (sometimes called "shrink-wrapped" or "pre-installed") are those that come with a standard interface and or protocol, such as SATA, an advanced host controller interface (eg AHCI, advanced host controller interface) or NVM Express operable, or are optional customer-specific and / or merchant-specific [designed] to use commands and / or flash transition layers used for solid state drives 1101a - 1101n are specific to enable. Some drives and / or drivers have pass-through modes to provide application-level programs, such as an application 1109 , via an optimized NAND access (sometimes called ONA (optimized NAND access)) or direct NAND access (sometimes called DNA (direct NAND access) technique), enable commands directly to the solid state drives 1101a - 1101n Communicating what allows a custom application to use commands and / or flash transitions specific to the solid state drives 1101a - 1101n are, even with a generic driver.

The ONA techniques include one or more of the following:
Use of non-standardized modifiers (hints); Use of dealer-specific commands; Communication of non-standardized statistics, such as current use of non-volatile memory according to the compressibility; Use of layer-specific flash transition layer-specific protocols, such as communicating addresses of readers and spans, or communicating addresses, offsets, and byte lengths of non-volatile ones memory page frame; and other techniques. The DNA techniques include one or more of the following: use of non-standardized instructions or dealer-specific instructions that provide non-mapped read, write, and / or erase access to the non-volatile memory; Using non-standardized or merchant-specific instructions that provide direct access to the non-volatile memory, such as bypassing the formatting of data that would otherwise handle the input / output device; and other techniques. Examples of drivers are a driver without ONA or DNA support, a driver designed for ONA, a driver designed for DNA, and a driver designed for ONA / DNA. Other examples of drivers are a dealer-provided, dealer-developed, and / or dealer-enhanced driver, and client-supplied, client-developed, and / or client-improved driver.

Examples of application-level programs are an application without ONA or DNA support, an ONA-designed application, a DNA-designed application, and an ONA / DNA-designed application. A dotted arrow 1109D is representative of bi-directional communication between an application and an input / output device (eg, bypassing via a driver or bypassing via a virtual function) for an application (eg, an ONA-designed application and an ONA-designed driver using communicates with a solid state drive, such as without the application using the operating system as an imtermmediate). A dotted arrow 1109V is representative of bidirectional communication between an application and an input / output device (eg, bypassing via a virtual function) for an application (eg, an application designed for DNA and a DNA driver configured to communicate with a solid state drive, such as for example, without the application that uses the operating system or the driver as an imtermmediate).

One or more sections of non-volatile memory 1199a - 1199n are, in some embodiments, as a firmware memory (eg firmware 1106a - 1106n ) used. The firmware memory includes one or more firmware images (or portions thereof). A firmware image has, for example, one or more images of the firmware, the be executed (eg by the central control unit (CPU) of the controllers 1100a - 1100N the solid state drives). As another example, a firmware map has one or more mappings of constants, parameter values, and non-volatile memory device imformation that are referenced, for example, by the central processing unit during firmware execution. The images of the firmware correspond to, for example, a current firmware image and zero or more previous (in terms of firmware updates) firmware images. In various embodiments, the firmware provides generic, standardized, ONA and / or DNA modes of operation, as well as operating with one or more flash transition layers. In some embodiments, some or more of the firmware operating modes are enabled (eg, one or more application program interfaces (eg, APIs) are "unlocked" via keys or various software techniques optionally communicated and / or provided by a driver). In further embodiments, various of the firmware maps are used for various of the modes of operation and / or different ones of the flash transition layers.

In some embodiments, the host includes 1102 an illustration 1108 as a separate hardware resource that implements an image. In other embodiments, an image is partially or in its entirety about the image 1108 and / or a host memory 1112H and / or an illustration 1141 in the control device 1100 of the solid state drive and / or the card memory 1112c implemented. Examples of the picture 1108 , the host memory 1112H , the picture 1141 in the control device 1100 Solid State Drive and Card Memory 1112c are one or more volatile and / or non-volatile memory elements, such as implemented via DRAM, SRAM and / or Flash or other non-volatile memory devices. Other examples of host memory include system memory, host memory, host cache memory, host accessible memory, and device accessible input / output memory. In some embodiments and / or user scenarios (such as some embodiments including an input / output card 1116 have and the optional card memory 1112c of the 11C use as memory (at least for part of the figure)), access one or more of the input / output devices and / or the host 1102 to the picture in the card store 1112c , In different embodiments are the host 1102 and / or one or more of the solids of the solid state drive 1101 designed to look at the picture 1108 , the host memory 1112H , the card store 1112c and / or the picture 1141 to access all or any portions of the image information used to convert logical block addresses (or other identifiers, such as names) to non-volatile memory locations (such as block and / or page frame addresses and / or addresses of Reading units) directed to one or more portions of non-volatile memory of an input / output device, such as elements of one or more of the non-volatile memory instances 1199a - 1199n is usable. Conceptually, a single map may exist and, according to various embodiments, control and / or storage and / or use of the map by one or more of the hosts 1102 and / or by the control devices 1100a - 1100N the solid state drives provided.

In some embodiments, where the switch / structure / intermediate controller 1103 missing, are the solid state drives 1101a - 1101n via the external interfaces 1111a - 1111n directly with the host 1102 coupled. In various embodiments, the controllers are 1100a - 1100N the solid state drives have one or more intermediate levels from other controllers, such as a RAID controller or input / output controller, with the host 1102 coupled. In some embodiments, the solid state drives correspond 1101a - 1101n (or variations thereof) to a SAS drive or SATA drive and the switch / structure / intermediate controller 1103 corresponds to an expander, which in turn is coupled to an imitator, or alternatively, the switch / structure corresponds to the intermediate control device 1103 a bridge indirectly coupled to an imitator via an expander. In some embodiments, the switch / structure includes the intermediate controller 1103 one or more PCIe switches and / or structures.

In various embodiments, such as some of the embodiments, wherein the host 1102 a computing host (eg, a computer, a workstation computer, a server computer, a storage server, a personal computer, a laptop computer, a notebook computer, a netbook computer, and / or a tablet computer), the rake host is optionally adapted to one or more local and / or remote servers (eg, optional servers 1118 ) (eg via optional input / output and storage facilities / resources 1117 and optional local area networks / wide area networks (eg LAN / WAN) 1119 to communicate. The Communication allows, for example, local and / or remote access management and / or use of one or more of the solid state drive elements. In some embodiments, all or part of the communication is over Ethernet. In some embodiments, communication is wholly or partially via Fiber Channel. The local network wide area network 1119 is representative, in various embodiments, of one or more local area networks and / or wide area networks, such as one or more server farms coupled from a network in a server farm, networked over a network, a metropolitan area network (metro network), area network) and the Internet.

In various embodiments, a controller for a solid state drive and / or a controller for a computing host, nonvolatile memory in combination with one or more nonvolatile memories are implemented as a nonvolatile memory component, such as a memory Universal serial bus (eg USB) component, universal flash memory (eg UFS) memory component, compact flash (eg FC) memory component, multimedia card (eg MMC) memory Component, a secure digital (eg, SD) memory component, a memory stick memory component, and an xD picture card memory component.

In various embodiments, all or any portions of a controller of a solid state drive (or non-volatile memory controller of a computing host) or functions thereof are implemented in a host to which the controller is to be coupled (eg, the host 1102 out 11C ). In various embodiments, all or any portions of a solid state drive controller (or non-volatile memory controller of a computing host) or functions thereof are hardware (eg, logic circuits), software, and / or firmware (eg, driver software or solid state drive control firmware) or any combination thereof.

With reference to 12 becomes a flowchart 1200 of writing data to non-volatile memory. The process begins in step 1202 , and in the step 1206 a determination is made to write (store) data to a non-volatile memory with a particular one of a plurality of names (or other unique identifiers such as object identifiers or logical block addresses). For example, the determination is performed by one or more of the following: an application program, an operating system, a hypervisor, or any other software or firmware module. In some embodiments, the write data is of variable size (eg, possibly varying with each write operation). In some embodiments, the write data is a number of fixed size units, such as a number of SATA sectors.

In step 1210 a write command and the associated write data (possibly of variable size) are received. In one example, an application sends a write command and write data (such as via a pointer to the data) to a driver using a system call. In another example, a host sends a write command to a controller of a solid state drive, along with an information that allows the controller of the solid state drive to retrieve the associated write data. For example, a write command includes a tag of a SATA native command queue (eg, NCQ, native command queue), and the native command queue flag is used to fetch the associated write data.

In step 1214 For example, the write data (possibly of variable size) is optionally and / or selectively compressed or otherwise reduced in size only. Even if the associated write data were already of variable size, compression may be able to further reduce a size of the associated write data. In some embodiments, the write data (possibly of variable size and possibly compressed) is optionally and / or selectively encrypted.

In step 1218 a next non-written location (a physical memory address space) of the non-volatile memory is designated for writing data. In one example, the particular, next undescribed, physical location is adjacent to the previously described variable size data (which would waste no space in the non-volatile memory). In another example, the particular next undetected physical location in the same read unit begins as the variable size data previously described. In some embodiments, the determined next physical location not described is in accordance with a band specified in the write command.

In step 1222 The write data (possibly of variable size, possibly compressed) in the non-volatile memory on the certain, next, not described, physical location stored. In some embodiments, a hardware unit writes the write data (possibly of variable size, possibly compressed) directly to a non-volatile memory page frame image (eg, a portion of a buffer that is stored in the non-volatile memory). Side frame is described).

In step 1226 For example, a header comprising an identifier of the write data is stored in a same non-volatile memory page frame as at least a portion of the write data (possibly of variable size, possibly compressed). For example, the message header is stored in a same non-volatile memory page frame as at least part of the write data (possibly of variable size, possibly compressed) as in 6 , and / or the header is stored in the same reading unit as at least part of the write data (possibly of variable size, possibly compressed) in FIG 5 , According to various embodiments, the identifier is one or more of the following: same as the particular name of the write data; a function of the specific name of the write data; an identifier associated with the particular name of the write data through a table; a unique identifier among all the data stored in the non-volatile memory; and any combination of the foregoing.

According to various embodiments, storing the write data (possibly of variable size, possibly compressed) and / or the message header occurs in the steps 1222 and or 1226 and / or is postponed until a non-volatile memory page frame of message headers and data (such as multiple write operations) is accumulated. In some embodiments, error correction coding is performed as part of the storage in the non-volatile memory. In further embodiments, the error correction coding appends a number of error correction coding bytes to a user portion of each reading unit to form read units as stored in the non-volatile memory. In still further embodiments, scrambling is performed prior to error correction coding.

In step 1230 an indication of the particular next physical location not described is returned. In one example, the indication of the particular nearest physical location not described includes an address of a reading unit, such as an address of a first one of the reading units, used to store the writing data (possibly of variable size, possibly compressed) , Continuing with the example and in some embodiments, the indication of the particular next physical location not described further includes a number of read units spanned by the write data (possibly of variable size, possibly compressed), for example a number of read units , which must be read to retrieve all and not more than the write data (possibly with variable size, possibly compressed). One or more of the plurality of readers optionally and / or selectively contains data associated with others of the names, however, each of the number of readers includes at least some of the write data (possibly of variable size, possibly compressed). In another example, the indication of the determined next physical location not described includes an address of a nonvolatile memory page frame and / or an offset in a nonvolatile memory page frame used to write at least a portion of the write To save data (possibly with variable size, possibly compressed). Continuing with the other example, and in some embodiments, the indication of the particular next physical location not described further includes a length in bytes of the write data (possibly of variable size, possibly compressed). Continuing with the other example, and in yet other embodiments, the write data (possibly of variable size, possibly compressed) spans more than one non-volatile memory page frame (eg, begins in a first non-volatile memory page frame and sits down into one or more subsequent non-volatile memory page frames). For example, if a remaining amount of user data at and subsequent to the offset in the first non-volatile memory page frame is less than the length in bytes of the write data (possibly of variable size, possibly compressed), then the write data will span (possibly variable size, possibly compressed) more than one non-volatile memory page frame.

In step 1234 a mapping is maintained that assigns a specific name to the input of the particular next, not described, physical location. For example, maintaining the map allows the data associated with the particular name to be retrieved by a subsequent read operation.

In step 1238 a statistic is maintained according to the write command. For example, writing the data associated with the particular name uses a certain amount of space in one Redundancy block where the data was written, and optionally and / or selectively released a certain amount of space in a redundancy block where an older version of the data associated with the particular name was stored. The statistic tracks an amount of space used (or equivalently an amount of free space in some embodiments) in each redundancy block. The process ends in step 1290 ,

In some embodiments, locks (such as semaphores) are used to access at least a portion of the map during at least part of the process 1200 to prevent. For example, and in some embodiments, an entry of the map associated with the particular name is of the steps 1210 to 1234 locked to prevent further access to the entry while it is being updated.

With reference to 13 becomes a flow diagram 1300 of reading data from a non-volatile memory. The process begins in step 1203 and in the step 1306 a determination is made to read (retrieve) data associated with a particular one of a plurality of names (or other unique identifiers, such as object identifiers or logical block addresses) from a nonvolatile memory. For example, the determination is made by one or more of an application program, an operating system, a hypervisor, or any other software or firmware modules. In some embodiments, the data is of variable size (eg, possibly varying with each read operation). In other embodiments, the data is a number of fixed size units, such as a number of SATA sectors.

In step 1310 the particular name is looked up in an image to determine an indication of a physical location in the non-volatile memory of a stored version of the data associated with a name. According to various embodiments, the look-up in the image is performed by a software module that produced the read operation, or by another software module called by the software module that performed the read operation. For example, an application effects the read operation, and a driver layer in the host or a firmware layer in a controller of a solid-state drive performs the lookup in the map.

In step 1314 For example, a read command with the entry of a physical location is received in the non-volatile memory. In one example, after a driver layer in the host has made the look up in the map, the driver layer sends a read command and the indication of a physical location in the nonvolatile memory to a controller of a solid state drive. In another example, after a first processor in a controller of a solid state drive has performed the lookup in the map, the first processor sends a read command and the physical location in the nonvolatile memory to a second processor in the FIG Control device of the solid-state drive, which controls access to the non-volatile memory.

In step 1318 the indication of a physical location in the non-volatile memory is used to determine a location and a number of read units in the non-volatile memory containing the stored version of the data associated with the particular name. In one example, the physical location indication includes an address of a reading unit, such as an address of a first one or more reading units used to store the stored version of the data associated with the particular name. Continuing with the example and in some embodiments, the physical location indication further includes a number of the one or more read units, for example, a number of read units that must be read, all and not more than the memory card version of the particular name to retrieve associated data (one or more of the one or more read units optionally and / or selectively includes data associated with others from the names, however, each of the one or more read units includes at least some of the stored versions of the particular name associated therewith Dates). In another example, the physical location indication includes an address of a nonvolatile memory page frame and / or an offset in a nonvolatile memory page frame that is used to encode at least a portion of the stored data of the data associated with the particular name save. Continuing another example, and in some embodiments, the physical location indication further includes a length in bytes of the stored version of the data associated with the particular name, and in continuation of the other example, and in still other embodiments, the stored version encompasses the particular name associated with the particular name Data exceeds a non-volatile memory page frame (eg, starts in a first non-volatile memory page frame and continues in one or more subsequent non-volatile memory page frames). If For example, if a remaining amount of user data at and subsequent to the offset in the first non-volatile memory page frame is less than the length in bytes of the stored versions of the particular name associated data, then the stored version of the data associated with the particular name spans more as a non-volatile memory page frame. In a further continuation of the other example, according to a number and / or a size of the reading units in the first non-volatile memory page frame and according to the offset and the length in bytes of the stored version of the data associated with the particular name, a first one of a plurality of the read units in the first nonvolatile memory page frame and a number of the read units in the first nonvolatile memory page frame. If the stored version of the data associated with the particular name spans more than one non-volatile memory page frame, a similar procedure is used with one or more subsequent ones of the non-volatile memory page frames to add additional readers to the subsequent non-volatile memory Page frame that includes at least a portion of the stored version of the data associated with the particular name.

In step 1322 the particular readers are read from the non-volatile memory. In some embodiments, error correction coding is performed on the readers to correct for any errors that occur during storage in and / or transfer to or from the nonvolatile memory. In further embodiments, subsequent to the error correction coding, de-scrambling is performed. Due to the error correction coding of the particular reading units, a number of bytes determined to be read from the non-volatile memory include both the user data in the reading units and the error correcting coding bytes in each of the reading units. In some embodiments, a number of the error correction coding bytes in each of the reading units dynamically varies, such as under control of the solid state drive controller due to wear of the nonvolatile memory. In various embodiments and / or user scenarios, a total number of bytes of user data in the particular readers exceeds the length in bytes of the stored version of data associated with the particular name, such as at least one of the particular readers at least a portion of the data are assigned from the names.

In step 1326 the stored version of the data associated with the particular name is extracted from the particular readers. In some embodiments, the extraction is done according to an identifier provided with the read command. According to various embodiments, the identifier is one or more of the following: the same as a particular name of the data; a function of the particular name of the data; an identifier associated with the particular name of the data about a table; a unique identifier among all data stored in the non-volatile memory; and any combination of the foregoing. In one example, the readers include one or more message headers, as in FIG 5 and the identifier is used to determine a matching one of the message headers which is then used to store the stored version of the data associated with the particular name in the particular readers. In another example, the physical location indication includes information specifying a location of the stored version of the data associated with the particular name within the particular readers. According to various embodiments, the stored version of the data associated with the particular name is of variable size. For example, the data associated with the particular name was compressed before it was stored, and / or the data associated with the particular name itself was of variable size.

In step 1330 the stored version of the data associated with the particular name is optionally and / or selectively decrypted and / or optionally and / or selectively decompressed to generate the data associated with the particular name.

In step 1334 the data associated with the particular name is returned in response to the read command.

In step 1338 a statistic is maintained according to the read command. In one example, the read command accesses a certain number of non-volatile memory blocks to retrieve the particular read units, and the statistics are maintained by counting a number of occurrences of read errors per non-volatile memory block. In another example, the read command accesses a certain number of non-volatile memory blocks to retrieve the particular readers, error correction of the particular readers corrects a certain number of errors in each particular reader, and the statistic is given a maximum Number of corrected errors in each Maintained read unit in each of the non-volatile memory blocks. The process ends in step 1390 ,

Typically, to read data from a single imaging unit that does not include multiple non-volatile memory page frames, a number of the read units that are to be accessed in a non-volatile memory page frame to obtain the stored version of the imaging unit data; less than all of the read units in the non-volatile memory page frame. Further, because the stored version of the imaging unit data is of variable size, a number of the read units referenced in the non-volatile memory page frame for a first read instruction that references a first logical block address (or name), is to be accessed, other than a number of read units to be accessed in the non-volatile memory page frame for a second read command that references a second logical block address (or name), the second logical block address being different from the first one logical block address is. In some embodiments, only the number of read units to be accessed in the nonvolatile memory page frame is read from the nonvolatile memory page frame. That is, only those read units that include a portion of the stored version of the imaging unit data are read from the non-volatile memory to access and retrieve the stored version of the imaging unit data.

With reference to 14 A flowchart of recycling data in a non-volatile memory is shown. The process begins in step 1402 , and in the step 1406 a determination is made as to a region of the non-volatile memory to be recycled. According to various embodiments and / or user scenarios, the scope is one or more of the following: a redundancy block; one or more non-volatile memory blocks; a part of the non-volatile memory maintained for free and / or used memory statistics; a part of the non-volatile memory used to maintain wear-leveling statistics; and any combination of the foregoing. According to various embodiments and / or user scenarios, recycling is performed on one or more of the following: garbage collection (accumulated free space) in the non-volatile memory; Wear leveling of the non-volatile memory (to keep the blocks of the non-volatile memory relatively equal with respect to a corresponding programming erase counter); and process faults and / or exceptions related to the non-volatile memory, such as program errors, excessive read faults, and / or excessive error rates. In other embodiments, recycling from a host is performed globally, such as over a plurality of solid state drives.

In step 1410 One or more non-volatile memory page frames are read from the non-volatile memory area. In some embodiments, the nonvolatile memory page frames are error corrected in their entirety. All of the read units in the non-volatile memory page frame are error corrected. In other embodiments, only a portion of the non-volatile memory page frames determined to contain message headers (such as in FIG 6 illustrated) first error-corrected, and other parts of the non-volatile memory page frames are error-corrected as needed when it is determined (eg, step 1426 ) The non-volatile memory page frames contain data that needs to be recycled.

In step 1414 Message headers are extracted from the non-volatile memory page frame. In an example and in an embodiment as they are in 5 is shown, message headers are extracted from each reading unit in each of the non-volatile memory page frames. In another example and in one embodiment, as in 6 1, message headers are extracted from a part of each of the non-volatile memory page frames, such as a first or more read units in each of the non-volatile memory page frames.

In step 1418 For example, the message headers extracted from the non-volatile memory page frames are parsed (parsed) to determine the identifiers of associated data in the non-volatile memory page frame (eg, beginning therein).

In step 1422 the identifiers are looked up in an image to determine the corresponding indications of the physical locations in the non-volatile memory of the data associated with the identifiers. In some embodiments, the identifiers are corresponding names of data that was used when the nonvolatile memory was written. In other embodiments, the identifiers are combined with other information, such as an identifier of a solid state drive, to form names that are looked up in the figure. In still other embodiments, an image is maintained that associates the identifiers with the name and / or associates the identities of the physical location in the nonvolatile memory with the identifiers associated with the identifiers.

In step 1426 For example, any data associated with the identifiers that are still current (in the non-volatile memory page frames that are being recycled) is written to a new physical location in the nonvolatile memory. For example, the corresponding indications of the physical locations in the non-volatile memory of the data associated with the identifier are converted to corresponding addresses of reading units, and if the corresponding addresses of the reading units are in the non-volatile memory page frame being recycled, then non-volatile memory page frames that are recycled, the most recent version of the data associated with the identifiers. In various embodiments, writing the still-current data associated with the identifier to a new physical location in the non-volatile memory concurrently with the steps 1218 to 1230 of the process 1200 executed. In various embodiments, when the still-current data is compressed and / or encrypted, the still-current data is re-written "as-is" in the compressed and / or encrypted form. In some embodiments, the still-up-to-date data from the non-volatile memory page frame being recycled is moved to a new non-volatile memory page frame within the solid-state drive controller (and the still-current data does not become one Host to recycle the still current data). In other embodiments, recycling includes sending the still-current data to the host and rewriting them similarly as in the process 1200 , In further embodiments, recycling is performed globally across a plurality of solid state drives, and still up-to-date data previously stored on one of the solid state drives is rewritten to another of the solid state drives for recycling.

In step 1430 the map is updated to reflect the indication of the new physical location of any data that has been recycled.

In step 1434 a determination is made as to whether additional nonvolatile memory page frames are to be processed in the area. If so, the process goes to the step 1410 to continue recycling of other non-volatile memory page frames.

In step 1438 a statistic is maintained according to the reading and writing of the non-volatile memory during the recycling process. In one example, reading the non-volatile memory accesses a certain number of non-volatile memory blocks to retrieve the non-volatile memory page frames, and maintaining the statistics by evaluating a number of the read-miss events per non-volatile memory block is counted. In another example, reading the non-volatile memory accesses a certain number of non-volatile memory blocks to recover the non-volatile memory page frames, and error correction of the non-volatile memory page frames corrects a corresponding number of errors in each of the read units of the non-volatile memory page frames which have been decoded by error correction, and the statistics are maintained for a maximum number of errors corrected in each reading unit in each of the non-volatile memory blocks. In yet another example, recycling the data by writing non-volatile memory uses a certain amount of space in a redundancy block where the recycled data has been written, and optionally and / or selectively gives a certain amount of space in the redundancy block recycled, free. The statistic tracks an amount of used space (or, equivalently, an amount of free space in some embodiments) in each redundancy block. In some embodiments, as the amount of space used in the area being recycled approaches zero, no further, still current (not already overwritten) data is recycled in the area and the process 1400 is able to complete itself before reading all of the non-volatile memory page frames in the area being recycled. The process ends in step 1490 ,

In some embodiments, locks (such as semaphores) are used to access at least a portion of the map during at least part of the process 1400 to prevent. For example, in some embodiments, an entry of the map associated with one of the current data identifiers will be from the steps 1422 to 1430 locked to prevent another access to the entry while it is being updated.

According to various embodiments, the host selects areas of the non-volatile memory to be recycled; the controller of the solid-state drive selects areas of the non-volatile memory to be recycled; the host selects areas of the non-volatile memory to be recycled for a first reason, and the solid-state drive controller selects areas of the non-volatile memory to be recycled for a second, different reason; and any combination of the foregoing. In an example, all selections of areas of the non- volatile memory to be recycled running in the host. In another example, the host selects non-volatile memory areas to recycle for waste collection, and the solid-state drive controller selects non-volatile memory areas to recycle for wear-leveling. In yet another example, the host selects non-volatile memory areas to recycle for waste collection and for wear leveling, and the solid-state drive controller selects non-volatile memory areas that are unusable due to exceptional conditions and / or errors, such as program errors, excessive error correction coding errors, or read disturb incidents. In other embodiments, the solid state drive controller is configured to communicate one or more statistics of the non-volatile memory, such as program deleting counters and / or used space, to the host. For example, the statistics are communicated as logs, such as SMART logs, through a reserved area of a logical block address space of the controller of the solid state drive, or through special instructions for reading and / or writing statistics. In some embodiments and / or user scenarios, communicating the statistics to the host allows the host to select portions of the non-volatile memory to be recycled while allowing the solid-state drive controller to maintain the statistics of to repel the host.

In some embodiments, the solid state drive controller is configured to recycle at least a portion of the nonvolatile memory independently of the host and to communicate updated physical locations to the host. For example, the controller of the solid state drive determines a portion of the nonvolatile memory that needs to be recycled in response to exceptional conditions and / or errors, such as program errors, excessive error correction coding errors, or read interference events. The solid state drive controller reads message headers in the nonvolatile memory area and relocates any still current data in the nonvolatile memory area to corresponding new physical locations in another nonvolatile memory area. According to various embodiments and in one or more implementations, the solid state drive maintains the map and is capable of updating the map to reflect the corresponding new physical locations of the still-up-to-date data; the solid-state drive controller maintains a separate partial map of data migrated by the solid-state drive controller, the separate partial map representing the physical locations of the still-current data in the non-volatile memory area assigns to physical places; the solid-state drive controller communicates the corresponding new physical locations along with information from the message headers, such as corresponding identifiers of the still-current data, to the host and the host updates the map; and any combination of the preceding ones. Advantageously, the still-current data in both the non-volatile memory area and the corresponding new physical locations may be accessed until the non-volatile memory area is erased. In further embodiments, the area of the nonvolatile memory is not cleared before the map is updated with the corresponding new physical locations. For example, the controller of the solid state drive is informed by the host that the map has been updated, and only then is it possible for the controller of the solid state drive to erase the nonvolatile memory area.

In various embodiments, the host controls the reading of the non-volatile memory page frames from the non-volatile memory for recycling (step 1410 ), such as by requesting a number of nonvolatile memory page frames to be read or a number of the extracted headers to be sent to the host. According to various embodiments, the host performs at least part of the message header analysis (step 1418 ) and / or the controller of the solid state drive performs at least a portion of the header analysis, such as by preprocessing and / or reformatting and / or filtering the extracted headers. In other embodiments, the host performs the image lookup (step 1422 ) and determines if any of the data needs to be rewritten. The rewriting (step 1426 ) is performed by the controller of the solid state drive under the control of the host, such as by the host sending a "rewrite" command for any still current data. The rewrite command is similar to a write command, but instead of having write data, the rewrite command includes an indication of a physical location in the non-volatile memory (the location from which the data is recycled), as well as that would do a read command. Similar to a write command, the rewrite command returns an indication of the new physical location of the rewritten data, and the host performs the step 1430 to refresh the picture. Im with it related embodiments in which the host is a larger part of the process 1400 executes, the rewrite command includes a buffer location in the controller of the solid state drive of still current data.

In some embodiments, non-standardized and / or dealer specific commands are used as part of a communication protocol between the host and the solid state drive controller. According to various embodiments, the communication protocol is one or more of the following: SATA, small computer system interface (SAS), SAS, peripheral component interconnect (PCIe) peripheral connection, NVM Express (non-volatile memory), SCSI via PCIe (eg SOP, SCSI Over PCIe), mobile express, USB, UFS, embedded multimedia cards (eg eMMC, embedded multimedia card), Ethernet, Fiber Channel or any other protocol used to Communication between two electronic devices is suitable. In one example, communication indicates an indication of a physical location between the host and the controller of the solid-state drive for vendor-specific instructions, such as vendor-specific versions of standardized read and write instructions. In the other example, extracted headers are communicated from the solid state drive controller to the host in log page frames (such as SMART log page frames) for recycle. In yet another example, extracted headers are treated similarly to the read data, but are read with a trader-specific "read extracted headers" command.

According to various embodiments, any of the steps of the process 1200 and / or the process 1300 and / or the process 1400 by one or more of the following: a host coupled to a controller of a solid state drive; a controller of a solid state drive coupled to a host; and with a combination of the aforementioned. In one example, the lookup of the map and the maintenance of the map are performed on the host. In another example, determining a number of read units is performed either by the host or by the controller of the solid state drive or both. In yet another example, the subsequent, dense-writing (tiling) of write data into non-volatile memory page frames (eg, step 1222 ) in the controller of the solid-state drive. In one example, write data is written tiled into the map of nonvolatile memory page frames in a buffer in the controller of the solid state drive and the controller of the host. In another example, extracting data from the readers (eg, step 1326 ) in the controller of the solid-state drive. In yet another example, compression (eg, step 1214 ) and decompressing (eg step 1330 ) in the controller of the solid-state drive. In one example, the statistics (eg, step 1238 or step 1338 ) maintained in the controller of the solid-state drive. In another example, determining the areas of the non-volatile memory to be recycled (eg, step 1406 ) in which host is running. In yet another example, moving from recycled to still-current data from an old place to a new place (eg 1426 ) in the controller of the solid-state drive.

In some embodiments, the host and / or controller of the solid state drive maintain a table that associates each one of a plurality of nonvolatile memory areas with certain characteristics and / or characteristics. In one example, the table assigns each of the non-volatile memory areas a particular one of a plurality of coding rates (error correction code strengths), allowing a set of data stored in each of the areas to be stored in accordance with a "Health" varies from each of the areas. Healthier domains use a higher (weaker) code rate and are able to store more user data, and weaker domains use a lower (stronger) code rate and are able to store less user data (but are able to to correct more mistakes). In another example, the table shows those of the areas that are defective or that have failed and should not be used. For example, with a NAND flash, some of a plurality of blocks of the NAND flash are defective, even if the NAND flash is new and other of the blocks may fail during a lifetime of the NAND flash. The table indicates blocks that must be skipped over when data is sequentially written (e.g., striping) through a plurality of NAND flash devices.

In some embodiments, a portion of the higher level map is maintained in the host, and a portion of the lower level map is maintained in the controller of the solid state drive. The part of the higher-level map associates names (or logical block addresses) with corresponding physical specifications Places in the non-volatile memory too. The indications of the physical locations in the nonvolatile memory are then further translated by the controller of the solid state drive using the portion of the lower level map to read and / or describe the physical locations of the nonvolatile memory are to be determined. From a host point of view, physical location information behaves as opaque handles, in that the solid state drive controller assigns one of the physical location indications to a particular data object in writing and the solid state drive controller is capable of performing the return specific data object if the corresponding physical location information is returned. In other words, knowledge of details of the organization of user data within the non-volatile memory is hidden from the host. Advantageously, the solid state drive controller is capable of performing at least some of the non-volatile memory management, such as selecting code rates or determining bad blocks or other areas of the non-volatile memory. volatile memory that is not used by the host.

In one example, when one particular one of a plurality of blocks of non-volatile memory is used first, the solid-state drive controller divides each of a plurality of page frames in the particular block into a plurality (eg, eight) corresponding read units and uses a particular one of a plurality of code rates for error correction of the particular block. Later, when the particular block is reused after being more worn, the solid-state drive controller divides each of the plurality of page frames of the particular block into multiple (eg, seven) corresponding readers and uses a stronger one of the code rates for error correction for that particular block. In both cases, when the host writes data stored in the particular block, an indication of a physical location in the particular block is independent of a number of the reading units into which the page frames of the particular block are divided.

In another example, when variable sized data spans multiple ones of a plurality of blocks of nonvolatile memory, indications of the physical locations used by the host are independent of any knowledge as to whether any particular block of nonvolatile memory is in use or has been marked as bad and is not used. Continuing the other example, suppose that block 7 a particular one of a plurality of chips of the non-volatile memory is bad and is not used. When data in the block 6 of a previous one of the chips spans into the subsequent block, then the controller of the solid state drive uses the block 6 of the particular chip. When data in the block 7 spanning the previous chip into a subsequent block, the controller of the solid state drive skips the block 7 of the chip and puts the data in block 7 away from the next chip. The host has no knowledge of which blocks are spanning the data.

According to various embodiments, background operations such as reading, scrub, and recycling are performed by one or more of the host, the solid state drive controller, or any combination thereof. According to various embodiments, any operations of the host and / or processor of the solid state drive controller are performed by any one or more central processing units, by one or more hardware units, and / or by any combination of the foregoing.

According to various embodiments, a host and / or controller of a solid state drive are capable of using one or more of the following: a conventional flash transition layer; a variable-size flash transition layer; a sequentially read optimized variable-size flash transition layer; any other type of flash transition layer, direct access to the non-volatile memory, any combination of the foregoing in various physical areas of the non-volatile memory; any combination of the foregoing in different logical parts of a logical address space of the controller of the solid state drive; and processed raw physical access on the non-volatile memory; and any combination of the foregoing.

According to various embodiments, host write data is optionally and / or selectively encrypted before being written to the non-volatile memory, and optionally and / or selectively decrypted after being read from the non-volatile memory. In further embodiments, the encryption occurs subsequent to optional and / or selective compression of the host write data, and decryption occurs prior to optionally and / or selectively decompressing the data read to be returned to the host.

While several exemplary embodiments herein use the solid state drive and have used the controller of the solid state drive, the described techniques are generally applicable to other input / output devices and / or data storage devices, such as solid state drives. The nonvolatile memory used in such input / output devices is, in various embodiments, other than a "solid state" nonvolatile memory, such as the magnetic disks (platters) of a solid state drive (eg, hard drives Drives using shingled magnetic recording).

In some embodiments, various combinations of all or part of operations performed by a multi-node memory device or a portion or portions thereof are, for example, a solid state drive or hard disk or non-volatile memory controller An input / output device capable of interoperating with a processor (such as a CPU) is capable of an input / output control device (such as a RAID-on-chip chip) as well as parts of a Processors, microprocessors, system-on-a-chip, application-specific integrated circuits, hardware accelerators, or other circuits that provide all or part of the aforementioned operations, specified by a specification compatible with processing by a computer system is. This specification is in accordance with various descriptions such as hardware description languages, circuit descriptions, netlist descriptions, mask descriptions, or layout descriptions. Exemplary descriptions include, but are not limited to: Verilog, VHDL (very high speed integrated circuit hardware description language), SPICE (simulation program with integrated circuit emphasis), SPICE variants such as PSpice, IBIS (input / output buffer information specification), Library exchange format (LEF), design exchange format (DEF), graphical database system-II (GDS-II), open artwork system interchange standard (OASIS) or other descriptions. In various embodiments, the processing includes any combination of interpretation, compilation, simulation, and synthesis to produce, verify, or specify logic and / or circuits suitable for inclusion in one or more integrated circuits. According to various embodiments, each integrated circuit may be designed and / or fabricated according to a variety of techniques. The techniques include a programmable technique (such as a field array integrated circuit (gate array integrated circuit)), a semi-custom technique (such as a wholly or partially cell-based integrated) Circuit), and a fully custom-made technique (such as an integrated circuit that is essentially specialized), any combination thereof, or any other technique involved in designing and / or manufacturing integrated circuits is compatible.

The of the representations of the 1 to 14 The functions performed may be implemented using one or more of the following: a general purpose general purpose computer, a digital computer, a microprocessor, a microcontroller, a reduced instruction set computer (RISC) processor, a CISC (complex instruction set computer) processor, a SIMDI (single instruction multiple data) processor, a signal processor, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital video signal processor (VDSP) and or similar calculating machines programmed according to the teachings of the description, as will be apparent to those skilled in the relevant art / s. Appropriate software, firmware, encodings, routines, instructions, opcodes, microcodes, and / or program modules may be readily developed by skilled programmers based on the teachings of this disclosure, as will be apparent to those skilled in the relevant art , The software is generally executed by one or more media, by one or more of the processors of the machine implementation.

The invention may also be implemented by the manufacture of the following: application specific integrated circuits (ASICs), platform ASICs, field programmable gate arrays (FPGAs), programmable logic devices (PLDs), complex programmable logic devices (CPLDs), sea-of Gates, RFICs (Radio Frequency Integrated Circuits), ASSPs (Application Specific Standard Products), one or more monolithic integrated circuits, one or more chips or chips formed as flip-chip modules and / or multi-chip modules or by connecting a suitable network of conventional component circuits as described herein, and modifications of which will be readily apparent to those skilled in the art.

The invention may also include a computer product which may be a storage medium or media and / or a transfer medium or media comprising instructions that may be used to program a machine to process one or more processes or to carry out the method according to the invention. The execution of the instructions contained in the computer product by the Machine, along with operations from surrounding circuits, can input data into one or more files on the storage medium and / or one or more output signals representative of a physical object or substance, such as an audio and / or visual Representation, transform. The storage medium may include, but is not limited to, any type of disk including a floppy disk, hard disk, magnetic disk, optical disk, CD, ROM, DVD, and magneto-optical disks and circuits such as read-only memories ), RAMs (random access memories), EPROMs (erasable programmable ROMs), EEPROMs (electrically erasable programmable ROMs), ultraviolet erasable programmable ROMs (UVPROMs), flash memories, magnetic cards, optical cards and / or any type of Media suitable for storing electronic instructions.

The elements of the invention may form part or all of one or more devices, units, components, systems, machines, and / or devices. The devices may include, but are not limited to: servers, workstations, storage array controller, storage systems, personal computers, laptop computers, notebook computers, palm computers, mini- Personal digital assistants, portable electronic devices, battery-powered devices, set-top boxes, encoders, decoders, transcoders, compressors, decompressors, pre-processors, post-processors, transmitters, receivers, transceivers , Cipher circuits, mobile phones, digital cameras, position determination and / or navigation systems, medical equipment, heads-up displays, wireless devices, audio recording, audio storage and / or or audio playback devices, video recording, video storage and / or video playback devices, game platforms, peripherals, and / or multi-chip modules. Those skilled in the relevant art / s would understand that the elements of the invention can be implemented in other types of devices to meet the criteria of a particular application.

The terms "may" and "general" when used herein together with "verbs" and verbs are to be understood as communicating the intention that the description is exemplary and believed to be broad are enough to encompass both the specific examples presented in the disclosure and alternative examples that may be derived based on the disclosure. The terms "may" and "general" as used herein should not be construed as necessarily implying the desirability or possibility of omitting a corresponding element.

While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• US 2012/058583 [0003]
• US 2012/049905 [0004]

Claims (19)

A method of using a partitioned flash transitions layer, comprising the steps of: (A) at a device from or from a host, receiving a write command with first write data, (B) generating second write data by compressing, in the device, the first write data, the second write data having a variable size, (C) storing the second write data at a physical location in a nonvolatile memory, the physical location being a next unrecorded location, and (D) in response to the write command, returning an indication of the physical location from the device to the host. The method of claim 1, further comprising the step of: Partitioning a non-volatile memory associated flash transition layer between the device and the host by storing (i) the indication in the host; and (ii) information associated with the variable variable in the device. The method of claim 1 or 2, further comprising the steps of: at the facility of the host, receiving a read command indicating the physical location, and in response to the indication, retrieving the second write data by reading a portion of the non-volatile memory including the physical location. The method of claim 3, further comprising the steps of: Restoring the first write data by decompressing the second write data as retrieved from the non-volatile memory; and Return the first write data as it was restored to the host. The method of one of claims 1 to 4, wherein the write command further comprises an identifier of the first write data, the method further comprising the step of: Storing the identifier in the non-volatile memory as at least a portion of a message header associated with the second write data. The method of claim 5, further comprising the step of: in the host, maintaining an image that associates the identifier with the physical location indication. The method of claim 5 or 6, wherein (i) the identifier is a logical block address and (ii) the indication comprises a physical address in the non-volatile memory of one of a plurality of read units, each of the read units comprising a corresponding range of Data and a corresponding error correction information that protects the corresponding area of data includes. The method of claim 7, wherein (i) the non-volatile memory has a plurality of page frames, (ii) the physical address is in a first one of the page frames, (iii) the first page frame contains a first number of the read units, (iv) a second one of the side frames includes a second number of the read units, and (v) the first number is different from the second number. The method of one of claims 1 to 8, wherein the next un-described location is adjacent to previously written data in a non-volatile memory physical address space. A method of using a partitioned flash transition layer, comprising the steps of: (A) at a device from a host, receiving a write command that includes variable-sized write data, (B) storing the write data at a physical location in a non-volatile memory, wherein the physical location is a next un-written location, and (C) in response to the write command, returning an indication of the physical location from the device to the host. The method of claim 10, further comprising the steps of: at the facility of the host, receiving a write command indicative of the physical location, and in response to the indication, retrieving the write data by reading a portion of the non-volatile memory including the physical location. The method of claim 11, further comprising the step of: Return the write data from the device to the host. The method of any of claims 10 to 12, wherein the write command further comprises a Identifier of the write data, the method further comprising the step of: storing the identifier in the non-volatile memory as at least a portion of a message header associated with the write data. The method of claim 13, further comprising the step of: in the host, maintain an image that associates the identifier with the physical location specification. The method of claim 13 or 14, wherein (i) the identifier is a logical block address and (ii) the indication comprises a physical address in the non-volatile memory of one of a plurality of readers, each of the readers comprising a corresponding portion of Data and a corresponding error correction information that protects the corresponding portion of data includes. The method of claim 15, wherein (i) the nonvolatile memory has a plurality of page frames, (ii) the physical address is in a first one of the page frames, (iii) the first page frame contains a first number of the read units, (iv) a second one of the side frames includes a second number of the read units, and (v) the first number is different from the second number. The method of any one of claims 10 to 16, wherein the next unsearched location is adjacent to previously written data in a non-volatile memory physical address space. An institution comprising: a non-volatile memory, and a circuit configured to (i) receive from a host a write command with first write data, (ii) generate second write data by compressing the first write data, (iii) second write data at a physical location in the non-volatile memory and (iv) in response to the write command, return an indication of the physical location to the host, wherein (a) the second write data is a variable size and (b) the physical location is a next un-written location. The device of claim 18, wherein the device is implemented as one or more integrated circuits.

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