CN104679446A

CN104679446A - A method for using a partitioned flash translation layer and a device

Info

Publication number: CN104679446A
Application number: CN201410407142.XA
Authority: CN
Inventors: 厄尔·T·科恩; 苏米特·普里
Original assignee: Infineon Technologies North America Corp
Current assignee: LSI Corp; Infineon Technologies North America Corp
Priority date: 2013-08-16
Filing date: 2014-08-18
Publication date: 2015-06-03
Anticipated expiration: 2034-08-18
Also published as: GB2519211A; CN104679446B; KR20150020136A; TW201518944A; JP6443794B2; JP2015036982A; GB201414515D0; TWI637262B; DE102014111670A1; KR102328612B1

Abstract

The invention discloses a method for using a partitioned flash translation layer and a device. Step (A): receiving a writing command having first written data from a host in the position of equipment. Step (B): generating second written data by compressing the first written data in the equipment, the second written data usually having a variable size. Step (C): storing the second written data in a physical location of a nonvolatile memory, the physical location being the next unwritten position. Step (D): returning an indication of the physical position from the equipment to the host in response to the writing command.

Description

For using the method and apparatus through segmentation quick flashing transitional layer

cROSS REFERENCE TO RELATED reference

The U.S. Provisional Application case the 61/893rd that this application case relates on October 21st, 2013 files an application, the U.S. Provisional Application case the 61/888th that on October 9th, No. 383 1 files an application, the U.S. Provisional Application case the 61/873rd that on September 3rd, No. 681 1 files an application, the U.S. Provisional Application case the 61/866th that on August 16th, No. 357 1 files an application, No. 672 and the U.S. Provisional Application case the 61/755th of filing an application on January 22nd, 2013, No. 169, the mode that each in described U.S. Provisional Application case is quoted hereby is in full incorporated to.

The U.S. the 13/053rd that this application case relates on March 21st, 2011 files an application, No. 175, described U.S. the 13/053rd, No. 175 U.S. Provisional Application cases the 61/316th relating on March 22nd, 2010 and file an application, No. 373, described U.S. the 13/053rd, the mode that each in No. 175 and described U.S. Provisional Application case is quoted hereby is in full incorporated to.

This application case also relates to the international application case PCT/US2012/058583 with October 4 2012 international application date, the U.S. Provisional Application case the 61/543rd that described international application claims is filed an application on October 5th, 2011, the rights and interests of No. 707, the mode that each in described international application case and described U.S. Provisional Application case is quoted in full is incorporated to.

The U.S. the 13/936th that this application case relates on July 10th, 2013 files an application, No. 010, described U.S. the 13/936th, No. 010 relates to the international application case PCT/US2012/049905 with August 8 2012 international application date, the U.S. Provisional Application case the 61/531st that described international application claims is filed an application on September 6th, 2011, No. 551 and the U.S. Provisional Application case the 61/521st of filing an application on August 9th, 2011, the rights and interests of No. 739, described U.S. the 13/936th, No. 010, the mode that each in described international application case and described U.S. Provisional Application case is quoted in full is incorporated to.

Technical field

The present invention one relate to computation host and input/output device technology, and more particularly relate to the method and/or equipment that are provided in the transitional layer split between main frame and controller.

Background technology

Conventional solid driver stores a fixing integer host logic block in every one page of nonvolatile memory.When the available size of every one page of user data size or nonvolatile memory is not fixed, there will be storage efficiency problem.Framework for the variable-size quick flashing transitional layer in solid-state drive is hardware intensive.Page header for identifying the where in the middle of multiple reading units of storage of subscriber data in the page of solid-state drive, and extracts data and relates to and first read and dissect page header.

Summary of the invention

The present invention relates to a kind of method for using through segmentation quick flashing transitional layer.Step (A) receives the write order with the first write data from main frame at equipment place.Step (B) produces the second write data by compressing described first write data in the apparatus.Described second write data have variable-size usually.Described second write data are stored in the physical locations in nonvolatile memory by step (C).Described physical location is next non-writing position.The instruction of described physical location is turned back to described main frame from described equipment in response to said write order by step (D).

Accompanying drawing explanation

From following detailed description and appended claims and graphicly will understand embodiments of the invention, wherein:

Fig. 1 is the diagram that LBA (Logical Block Addressing) arrives the selected details of the embodiment of the mapping in the fixed size region in nonvolatile memory page;

Fig. 2 is that LBA (Logical Block Addressing) arrives optionally across the diagram of the selected details of the embodiment of the mapping in the variable-size region of nonvolatile memory page;

Fig. 3 is the diagram of the embodiment of the nonvolatile memory page comprising an integer reading unit;

Fig. 4 is the diagram that LBA (Logical Block Addressing) arrives the selected details of the embodiment of the mapping in the variable-size region across one or more reading unit;

Fig. 5 is the diagram of the selected details of the embodiment of the reading unit comprising header and data;

Fig. 6 is the diagram of the selected details of the embodiment of the nonvolatile memory page comprising header and data;

Fig. 7 is the diagram of the selected details of another embodiment of the nonvolatile memory page comprising header and data;

Fig. 8 is the diagram of the selected details of the embodiment of various types of header;

Fig. 9 is the diagram of the selected details of the embodiment of map entry;

Figure 10 is the diagram of the selected details of the embodiment of various compressed map entry;

Figure 11 A is the diagram of the selected details of the embodiment of solid-state drive controller;

Figure 11 B is the diagram of the selected details of the embodiment of data routing segmentation;

Figure 11 C is the diagram of the selected details of the various embodiments of system according to an embodiment of the invention;

Figure 12 is the process flow diagram writing data into nonvolatile memory;

Figure 13 is the process flow diagram reading data from nonvolatile memory; And

Figure 14 is the process flow diagram making data recycle in the nonvolatile memory.

Embodiment

Embodiments of the invention comprise the transitional layer being provided in and splitting between main frame and controller, described transitional layer can: (i) supports the size of data of wide region; (ii) operate with non-block-based data; (iii) handle is turned back to main frame in response to write data; (iv) utilize described handle to read data; And/or (v) is embodied as one or more integrated circuit and/or the firmware that is associated.

Main frame is coupled to input/output device (such as solid-state drive (such as, SSD) controller), and input/output device is coupled to and/or comprises nonvolatile memory (such as, NVM).The example of main frame to comprise on computation host, server, personal computer, laptop computer, mobile computer, workstation computer, personal digital assistant, smart phone, cell phone, media player or register, i/o controller, chip cheapness/Redundant Array of Independent Disks (RAID) (such as, RAID) (such as, ROC) controller and comprise other device any of processor or computing machine.Main frame is initiated in order to access (such as via input/output device, read or write) request of nonvolatile memory, and described request by main frame combination (such as, at least in part by the software that main frame runs) and performed by input/output device (such as, at least in part by the firmware that input/output device runs).

In certain embodiments, quick flashing translation layer (such as, FTL) by the LBA (Logical Block Addressing) in LBA (Logical Block Addressing) space (being such as used for performing input/output operations to input/output device by main frame) (such as, LBA) physical location (physical storage address such as, in physical address space) in (or translating into) nonvolatile memory (such as NAND flash non-volatile memory) is mapped to.According to various embodiment, the mapping of the LBA (Logical Block Addressing) in LBA (Logical Block Addressing) space carries out via one or many person in the following: one-level maps; Two-stage maps; Multistage-mapping; Direct mapping; Be associated mapping; Hash table; B sets; Trie; The cache memory of the part mapped; And other component any that LBA (Logical Block Addressing) is associated with the physical location in nonvolatile memory.In a further embodiment, mapping comprises multiple entry, such as, for an entry of each LBA (Logical Block Addressing) in LBA (Logical Block Addressing) space.

In other embodiments, the mark of corresponding data or other unique identifier are mapped to the physical location in nonvolatile memory by quick flashing transitional layer.For example, described mark can be the hash function (such as SHA-256 or SHA-512 hash function) of corresponding data, or be stored as corresponding data or be stored in the object identifier of the corresponding object in corresponding data, or the file system identifier (such as index node) of corresponding data (wherein corresponding data is file system object).According to various embodiment, the mapping of the mark of corresponding data or other unique identifier carries out via one or many person in the following: one-level maps; Two-stage maps; Multistage-mapping; Direct mapping; Be associated mapping; Hash table; B sets; Trie; The cache memory of the part mapped; And other component any that mark or other unique identifier are associated with the physical location of nonvolatile memory.In a further embodiment, map and comprise multiple entry, such as, for an entry of each existing markers or other unique identifier.Still further in embodiment, mapping is dynamic and its number with existing markers or other unique identifier increases or reduces and increase or tighten in size.In one example, the size of mapping increases with the number of existing markers or other unique identifier or reduces and increase linearly or tighten.In another example, the size of mapping increases with the number of existing markers or other unique identifier or reduces by more than respective threshold and step-by-step movement (with discrete chunk form) increases or tighten.

In various embodiments, multistage-mapping is for providing the scope of unique identifier and/or restriction unique identifier.For example, in first-phase relationship maps, mark is searched to produce the length unique identifier shorter than mark.Then described unique identifier is searched to produce the physical location in nonvolatile memory in mapping second.In a further embodiment, second mapping is multiple mappings, such as a mapping of multiple physically unitary part (such as, being present in different solid magnetic disc) of nonvolatile memory and/or each functionally in different piece (such as, dissimilar).

Each in multiple mark (or handle or LBA (Logical Block Addressing) or identifier or other similar terms) corresponds to respective data object (or sector or block or project or other similar terms) usually, and quick flashing transitional layer makes each in mark be associated with corresponding data object physical location in the nonvolatile memory.Mark it is said it is make via mapping with the relevance of corresponding data object physical location in the nonvolatile memory, and performs described relevance howsoever.Although various examples herein use the mapping of LBA (Logical Block Addressing), and other example uses the mapping of object tag or object identifier, in the spirit of teaching in this article, can use many similar data markers technical batterys homophase relationship maps technology.

As used herein, term " map unit " is the size of the data object mapped by quick flashing transitional layer of making a comment or criticism.In certain embodiments, map unit is fixed size, and in other embodiments, the size of data object is variable (and therefore the size of map unit is not fixing).

In certain embodiments, operating in aligned units of one or more logic sector or block is mapped in.Each map unit be one or more logic sector or block through aligned units.Each map unit has the corresponding physical location (if map unit is never written into or is trimmed, so comprising the possibility of NULL physical location) of the data wherein storing map unit.For example, when 4 kilobyte (such as, KB) map unit, eight adjacent (and usual eight sector alignments) Serial Advanced Technology Attachment (such as, SATA) 512 byte sector are mapped as individual unit.Usually, for the mapping of LBA (Logical Block Addressing) have every map unit entry with store to the LBA (Logical Block Addressing) that map unit is associated to the corresponding translation of the physical address nonvolatile memory and/or other control information.

In various embodiments, the size (size of each map unit) of the data object just mapped and/or be stored in the size variation of the data object in nonvolatile memory.In one example, each in the entry in mapping stores the size of respective data object.Continuing described example, in key/value stores, storing the mark of the entry for accessing mapping according to key, and value is for respective data object, different in the middle of the size of the described value different persons in key.In another example, each in the entry in mapping store in order to read with retrieval the instruction of amount of nonvolatile memory of storage data object.In the version of another example, the amount of the nonvolatile memory of being specified by the entry mapped comprise location in the amount of the nonvolatile memory of being specified by the entry mapped one or more store the header of corresponding the stored data object in the middle of data object or its part.In another version of another example, amount in order to read the nonvolatile memory retrieve respective data object specifies the definite size and location of corresponding the storage data object in the page of nonvolatile memory, and regardless of nonvolatile memory error recovery how.Extra computation is for determining in order to the out of Memory reading the relatively large of nonvolatile memory to retrieve corresponding storages data object and be enough to the data execution error correction of reading from nonvolatile memory.

According to various embodiment, nonvolatile memory is one or many person in the following: NAND quick flashing, its every unit stores a position (such as, single level-cell), two positions (such as, multi-level-cell), three positions (such as, three-level cells) or three with upper and for (two dimension) of plane or (such as, the 3D) of three-dimensional; NOR quick flashing; The flash memory of other type any or electricity erasable memorizer; Phase transition storage (such as, PCM); Magnetic RAM (such as, MRAM); Racing track storer; Resistive random access memory (such as, ReRAM); Battery backed static RAM (such as, SRAM) or dynamic RAM (such as, DRAM); Any magnetic or optic storage medium; Or other nonvolatile memory any.

In certain embodiments, nonvolatile memory (such as) is by being physically isolated from different input/output device (such as, in different solid magnetic disc) or be organized into one or more group (such as by having different physical location or access mechanism, a part of nonvolatile memory is NAND quick flashing, and Part II is phase transition storage).In some embodiments in an embodiment, be mapped as global map, wherein each entry specifies the physical location in input/output device mark (such as, ID) and described input/output device.In other embodiments, map segments is become multiple part, such as every input/output device part, and the selected one in the function determination input/output device of more senior mapping and/or respective markers.

Some nonvolatile memories (such as NAND quick flashing) provide be called nonvolatile memory page (or for example, when referring to NAND quick flashing, quick flashing page) write (or able to programme) unit.The most I writing unit of nonvolatile memory page normally nonvolatile memory.In some embodiments and/or use in sight, nonvolatile memory page comprises several users (non-erroneous correcting code) data byte and a certain amount of clearance spaces for metadata and error recovery decoding (such as, ECC).Typical NAND quick flashing page size is the user data of 8KB or 16KB or 32KB, and is 4KB or 8KB for the typical map unit size of LBA (Logical Block Addressing).Although (use term " user " data about nonvolatile memory page, some nonvolatile memory pages store " system " data of such as mapping (enum) data and/or checkpoint data.User data intend one refer to nonvolatile memory page non-erroneous correct decoding portion.) NAND quick flashing page is organized into some pieces, every block 128,256 or 512 quick flashing pages usually.One piece of minimal size unit for being wiped free of, and NAND quick flashing page can be write by (again) after described page is wiped free of.

Some nonvolatile memories (such as NAND quick flashing) have multiple plane and/or memory block and permit accessing abreast from each two or more planes " many planes " operation of (read or programming or erasing) page and/or block.Use many planes to programme and advantageously increase write bandwidth, and cause basic writing unit to be many planes page but not single monoplane page.According to the mode using nonvolatile memory, nonvolatile memory page (or non-volatile memory block) represents single nonvolatile memory page (or block) or many planes nonvolatile memory page (or block) as used herein, the term.

Although use term " quick flashing " translation layer (such as, FTL) herein, the concept of the translation layer between logical address and physical address is applicable to polytype nonvolatile memory.In one example, before rewriting, in big unit, the nonvolatile memory of particular type is wiped, such as NAND quick flashing.In another example, the nonvolatile memory of some types stands loss, thus causes wear leveling (data are moved to less loss part from the more loss part of nonvolatile memory).In a further example, the new model (such as partition strategy magnetic recording) of hard disk magnetic recording not have when not wiping other data of much bigger quantity overriding previously write the ability of data.In various embodiments, for coarseness or there is limited persistent types of non-volatile benefit from (quick flashing) translation layer.

With reference to figure 1, it shows the diagram of LBA (Logical Block Addressing) to the selected details of the embodiment of the mapping in the fixed size region in nonvolatile memory page.The number of the bytes of user data in some traditional flash transitional layers supposition nonvolatile memory page (such as, nonvolatile memory page 100) is the power (and/or multiple of sector-size) of 2 and nonvolatile memory page is divided into an integer map unit (each is shown as data in FIG).For example, when the map unit of the user data of every nonvolatile memory page 16KB and 4KB, each nonvolatile memory page contains four map unit, and the one in the address (such as, LBA [M:U] 110) of each map unit is mapped in corresponding nonvolatile memory page and corresponding nonvolatile memory page by quick flashing transitional layer four map unit.That is, each map entry contains respective field, such as:

nonvolatile__memory_page_address[n-1：0]，mapping_unit_within_nonvolatile_memory_page[k-1：0]

Wherein nonvolatile_memory_page_address refers to the unique nonvolatile memory page in nonvolatile memory, and mapping_unit_within_nonvolatile_memory_page refers to 2 of each nonvolatile memory page ^kone (k is fixing for whole nonvolatile memory) in the large fraction of individual map unit.Sub-page address 104 is combinations of nonvolatile_memory_page_address and mapping__unit_within_nonvolatile_memory_page.For based on sector (such as, the granularity thinner than map unit) addressing, subdivision is specified in the lower-order position of LBA (Logical Block Addressing) (such as, LBA [U-1:0] 111), such as, several sectors (sector 113 such as, in subpage) in map unit.

With reference to figure 2, it shows that LBA (Logical Block Addressing) is to optionally across the diagram of the selected details of the embodiment of the mapping in the variable-size region of nonvolatile memory page.Variable-size quick flashing translation layer (such as, VFTL) the conceptive address by map unit (or mark) (such as, LBA [M:U] 110) be mapped to the variable-size region of one or more nonvolatile memory page (for example, this is because the data of map unit were compressed before being stored in nonvolatile memory and/or in another example, because map unit is write, such as, for object memory block by the section of main frame as variable-size).But, in each map entry, provide complete byte address 204 and byte data length 206 to make map entry larger compared with traditional flash transitional layer time.

With reference to figure 3, it shows the diagram comprising the embodiment of the nonvolatile memory page of an integer reading unit.In certain embodiments, variable-size quick flashing translation layer performs the mapping from the address (or mark) of map unit to physical address by being mapped to Epage (such as, error recovery decoding page) address (also referred to as " reading unit " address).Epage (or reading unit) can read from nonvolatile memory and minimum data amount by correcting for the protection of the error-correcting code of the content of nonvolatile memory.That is, each reading unit contains a certain amount of data and protects the corresponding error recovery decoding check byte of described data.In certain embodiments by a nonvolatile memory page (such as nonvolatile memory page 100) or in other embodiments the nonvolatile memory page group being considered as a unit for write object is divided into an integer reading unit, as illustrated in figure 3.

When nonvolatile memory (such as the NAND quick flashing) of some types, the data be stored in nonvolatile memory are mixing of bytes of user data and error-correcting code byte (error recovery information), and which byte of the higher level controller determination nonvolatile memory of accessing non-volatile memory and how many bytes are used for which byte of user data and nonvolatile memory and how many bytes are used for error recovery decoding.In various embodiments, the number of variations of the reading unit of every nonvolatile memory page is allowed.For example, the some parts of nonvolatile memory uses the error-correcting code (use comparatively multibyte in nonvolatile memory page come for error recovery decoding information) stronger than other parts, and has less reading unit and/or the less data available of every reading unit.In another example, the number of variations of the reading unit of every nonvolatile memory page when using nonvolatile memory, because program/erase cycle often weakens nonvolatile memory, thus cause stronger error-correcting code when more using (loss) nonvolatile memory.

According to various embodiment, the error-correcting code used is one or many person in the following: Reed-Solomon (such as, RS) code; Bo Si-Cha Dehuli-Huo Kun lattice mother (such as, BCH) code; Turbine code; Hard decision and/or soft decision low-density checksum (such as, LDPC) code; Polar code; Nonbinary code; Cheapness/Redundant Array of Independent Disks (RAID) (such as, RAID) code; Erasure codes; Other error-correcting code any; Aforementioned every any combination, comprises composition, juxtaposition and interlocks.Typical case's codeword size is between from 512 bytes (adding error recovery decoding byte) in the scope of 2176 bytes (adding error recovery decoding byte).The typical number of error recovery decoding byte between only several byte in the scope of a hundreds of byte.In some multi-level-cells NAND flash device, error recovery criterion is user data 40 positions of every 1KB.In some multi-level-cells NAND flash device, code check (ratio of the total byte in user octet and reading unit) is less than 94% usually.For example, MLC NAND flash device has the quick flashing page of size 17664 bytes, 16384 bytes Nominal ground of described quick flashing page is mapping (enum) data for storing, and 1280 bytes are " vacant " byte nominally for storing metadata and error recovery decoding byte.Recommendation error recovery decoding intensity for MLC NAND flash device is every 1 kilobyte 40 correction bits, and it uses 70 bytes in the vacant byte of every 1 kilobyte of institute's mapping (enum) data byte.

With reference to figure 4, it shows the diagram of the selected details of embodiment LBA (Logical Block Addressing) being mapped to the variable-size region across one or more reading unit.In certain embodiments, VFTL maps by variable-size (such as, compressed) address of map unit (or mark) (such as, LBA [M:U] 110) be mapped to several reading units being expressed as reading unit address 404 and span (number of reading unit) 406 in each entry mapped.By the reading unit of the one reference in map entry in one or more (in logic and/or physically) in proper order nonvolatile memory page, for example, several reading units described optionally and/or optionally cross over nonvolatile memory page boundary.By in the various embodiments of data stacking in reading unit, the entry mapped is typically not enough to location associated data (because entry is not only with reference to reading unit and with reference to the position of the data in reading unit) individually, and the further information (such as header) in referenced reading unit is for accurately locating associated data.

In certain embodiments, data are written in nonvolatile memory page in the mode of the multiple nude film stripings crossing over nonvolatile memory.Cross over multiple nude film stripe write data by only once being written in given nude film by every for nonvolatile memory page band and advantageously realizing larger write bandwidth.The block band crossing over multiple nude film is called redundant block, because in further embodiment and/or use sight, use (for example) redundancy nude film to add class RAID redundancy on redundant block basis.In various embodiments, some blocks of nonvolatile memory are defective and are skipped when writing, with " hole " that make the striping occasional one had in wherein nude film be skipped (but not being written in the nonvolatile memory page of bad block).In this little embodiment, the logical order that " in proper order " nonvolatile memory page is determined by the order by write nonvolatile memory page is in proper order.

With reference to figure 5, it shows the diagram comprising the selected details of the embodiment of the reading unit of header and data.In various embodiments, illustrated in Fig. 4 mapping produces the criterion in reading unit inner position variable-size data.As illustrated in figure 5, each reading unit (such as, reading unit 500 and 510) there is one group of zero or more header 501, and usually write described header by hardware, (such as, pile up thick and fast and without the space of waste) is in one or more reading unit because variable-size data " are pieced together ".When reading non-volatile storage, usually carry out decipher header to extract variable-size data by other hardware.By there is in header respective offsets in the one of the LBA (Logical Block Addressing) (or mark) of coupling and length locates variable-size data, and data are optionally and/or optionally across some reading units (such as by the variable-size data that " data; start " and " data continue " are illustrated).

In various embodiments, described header is also used as recycle (such as, garbage collection and/or wear leveling) part-comprise in header LBA (Logical Block Addressing) (or equivalently, map unit address or mark) not only realized the variable-size data found out in reading unit but also provided a kind of in order to determine when the specific one read in described reading unit, variable-size data in it be still effectively or be written (by search LBA (Logical Block Addressing) in the map and determine described mapping whether still with reference to specific reading unit physical address or be updated to reference to the another one in reading unit) mode.Therefore, header it is said formation " inverse mapping ", is similar to information in mapping but from the relevant information being linked to LBA (Logical Block Addressing) (or mark) of physical location because have to the header that the physical location of reading unit combines.

In certain embodiments, the specialized hardware extracting data in order to logic-based block address (or mark) from reading unit through enforcement for reading with high efficiency manipulation at random.Specialized hardware dissects header in one or more reading unit to find out in described header the one with given LBA (Logical Block Addressing) (or mark) and then to use corresponding length and skew to extract the variable-size data be associated.But hardware based solution is expensive (on silicon area and power).For the low side that wherein the random performance of Performance Ratio is important in proper order and/or mobile environment, implement to change to reduce silicon area, save power and realize high handling rate in proper order to variable-size quick flashing translation layer.

In certain embodiments, through reading the variable-size quick flashing translation layer of optimization in proper order (such as, SRO-VFTL) data (will be piled up) thick and fast and piece nonvolatile memory page together (or in certain embodiments, the nonvolatile memory page group of a unit is considered as write object) in, and in data, useless any gap in header-all headers are all grouped in a part of nonvolatile memory page.In a further embodiment, header not dynamically for access data (as in some variable-size quick flashing translation layers), but only for recycle and recovery.Instead, the entry of mapping comprises the complete information for finding out variable-size (such as, the compressed) data in nonvolatile memory page.To cause only comprising the reading unit of header, the reading unit (but as in figure 6, every nonvolatile memory page is this type of reading unit only) mixed comprising header and data and the reading unit only comprising data in header and data separating to the different piece of nonvolatile memory page.

Although be configured with low cost for reading process amount in proper order, but the variable-size quick flashing translation layer through reading optimization in proper order can be measured by other (random reading input/output operations (such as, IOP), random writing input/output operations per second such as per second and write treatment capacity in proper order) reasonably well shows.But that assists the hardware of the function such as pieced together by the VFTL formula data of header in each reading unit removes and can cause larger burden to control processor.Or in certain embodiments, the variable-size quick flashing translation layer through reading optimization in proper order uses that hardware comes that auxiliary data is pieced together, data are extracted or other operation.

With reference to figure 6, it shows the diagram of the embodiment of SRO-VFTL nonvolatile memory page.With reference to figure 7, it shows the diagram of another embodiment of SRO-VFTL nonvolatile memory page.Difference between the embodiment of Fig. 6 and Fig. 7 is be before header or afterwards from the continuation data of previous nonvolatile memory page 640.The present invention expects the various embodiment of the data in nonvolatile memory page and layout.

According to various embodiment, nonvolatile memory page comprises one or many person in the following:

-header, it comprises principal mark head 610, optionally and/or optionally redundant block header 620 (header such as, added in the first page of each block for redundant block) and zero or more is additionally through piling up header 630.Each quick flashing page has at least one counting of the number of the header continued and in nonvolatile memory page, starts the pointer of part to data (being associated with described header).In certain embodiments, described header can be byte-aligned, but is separately only 6 bytes (such as, B).Described header can including but not limited to data header, period header and filling up.Data header utilizes map unit address and length.Imply skew, because all data are all piled up adjacently.

-optionally and/or optionally, from the continuation data (parts for the variable-size data of map unit) 640 of previous nonvolatile memory page.

-in order to fill one or more map unit of nonvolatile memory page through pile up (such as, optionally and/or optionally compressed) data 650, the last of described nonvolatile memory page optionally and/or optionally continues in follow-up nonvolatile memory page.

-optionally the filling up (being contained in 650) of end of nonvolatile memory page.In various embodiments, data are (such as, atresia) that byte is piled up, if but high compression (such as, too much header), so may fill up in the end of nonvolatile memory page.For example, use when following situation and fill up: (therefore the last variable-size data segment that (i) adds nonvolatile memory page to is left the unused bytes fewer than the size of header, new header cannot be added to start another variable-size data segment), and (ii) optionally and/or optionally, exceed the specifying number of the header of every nonvolatile memory page (number therefore, being stored in the map unit in nonvolatile memory page by header specifying number but not size of data by map unit limits).

In certain embodiments, about the recovery of the variable-size quick flashing translation layer through reading optimization in proper order and/or recycle (such as, garbage collection) the only Header portion of each advantageously through enabling to read and/or in error recovery and/or inspection nonvolatile memory page, but not as read in without the variable-size quick flashing translation layer reading optimization in proper order and/or error recovery and/or check each reading unit.If the data of recycle determination rewritable nonvolatile memory page, so also can read described data and also can carry out error recovery to it.In certain embodiments, read whole nonvolatile memory page to carry out recycle, but error recovery is carried out to only Header portion until make and should make only being defined as of some data recirculation in nonvolatile memory page.

In various embodiments, the number of the header of every nonvolatile memory page through limiting the number of the reading unit that can read to retrain every nonvolatile memory page, thus is guaranteed to read all headers from nonvolatile memory.In the embodiment in fig 6, the some reading units being enough to hold a maximum number header are only read.In the embodiment of Fig. 7, read an additional number reading unit to consider the largest amount (such as, continuation data 640) of the data of the ending from previous nonvolatile memory page.But, the embodiment of Fig. 7 makes it possible to determine in order to access from previous nonvolatile memory page (such as from the map entry that is associated, continuation data 640) the number of reading unit of the end of data because the number of the byte in the end of data can be determined based on the number of the byte of the respective offsets of the map entry that is associated and length and user's (non-erroneous correcting code) data previously in nonvolatile memory page.In addition, the header that only has before the end of data is optional redundant block header (existing only in specified nonvolatile memory page, such as, first page in each block) and principal mark head (being present in all the time in each nonvolatile memory page).In the embodiment in fig 6, in order to when the ending of data need not be read, assuming that there is a maximum number header (or reading whole nonvolatile memory page) when twice accessing non-volatile memory.

In certain embodiments, the variable-size quick flashing translation layer through reading optimization in proper order uses the single-stage with multiple map entry to map.In other embodiments, variable-size quick flashing translation layer through reading optimization in proper order uses multistage-mapping, such as two-stage maps, it has the sensing second level and maps (such as, SLM) first order of page maps (such as, FLM), each wherein in the mapping page of the second level comprises multiple leaf-size class map entry.In a further embodiment, multistage-mapping has two or more level, such as three levels.In some embodiments and/or use sight, the use of multistage-mapping makes it possible to only by being correlated with (such as of mapping, in use) part stores (such as, high-speed cache) at local storage (such as, the local DRAM of SRAM or main frame on the chip of solid-state drive controller) in, thus reduce the cost maintaining and map.For example, if typical using forestland has 1 GB of some place effect at any time (such as, GB) LBA (Logical Block Addressing) space, so in order to quick access only stores the part being enough to the 1GB part of the effect accessing LBA (Logical Block Addressing) space mapped partly, but not be stored in nonvolatile memory.Reference outside the agency part in LBA (Logical Block Addressing) space obtains institute's requested part of one or more level of multistage-mapping from nonvolatile memory, thus optionally and/or optionally replaces the part of other local storage of mapping.

Each in leaf-size class map entry is associated (corresponding) with the address (or mark) of the one in multiple map unit.In one example, LBA (Logical Block Addressing) is converted to map unit address, such as by removing zero or more least significant bit (LSB) of LBA (Logical Block Addressing) (such as, LSB) and/or for aligning object add constant to LBA (Logical Block Addressing), and search map unit address in the map to determine the corresponding entry of described mapping.In another example, in hash table (or other associated data structures), mark is searched to determine to be used as the unique identifier of map unit address.

With reference to figure 8, it shows the diagram of the details of the embodiment of various types of header.In the example of Fig. 8, described header has formatd to load six bytes separately.According to various embodiment, various types of header is one or many person in the following: all have formed objects; Optionally and/or optionally there is different size; Each comprises the respective field of the size of specifying header; Vary in size in different non-volatile storage page; And aforementioned every any combination.

According to various embodiment, the header in nonvolatile memory page comprises one or many person in the following:

-data header 810, it indicates the information be associated with variable-size data division.In certain embodiments, start in the nonvolatile memory page identical with the nonvolatile memory page that described data header occurs with the data that data header is associated.In further embodiment and/or use sight, if nonvolatile memory page only has the remaining space for data header, so all associated data start in follow-up nonvolatile memory page.

-map header, such as the second level maps (such as, SLM) header 820.The second level maps header and comprises the first order map index (such as, FLMI) just storing which second level mapping page in order to instruction (such as mapping recycle and/or recovery for the second level).

Daily record/checkpoint header 820.Daily record/checkpoint header instruction is used for the data of recycle, recovery, error handling, debugging or other special status.

The part that-period, header 830 was used as to reclaim is associated with correspondence mappings/checking point information to make data.Usually, there is header at least one in every nonvolatile memory page in period.

The every nonvolatile memory page of-principal mark head 870 uses once with the information that the number and the where of non-header data in nonvolatile memory page that provide about the header in nonvolatile memory page start.Various technology determines the beginning of non-header data, such as illustrated in the embodiment of Fig. 6 and Fig. 7.

-in some nonvolatile memory pages (being such as the first nonvolatile memory page in each block of redundant block), use redundant block header 880.

The header 840 of-other type, such as, fill up header, support the checkpoint header etc. of greater depth.

In certain embodiments, some headers comprise the TYPE field of the multiple subtypes providing header.In various embodiments, some headers comprise LEN (length) field of the length containing the data be associated with header.In various embodiments, not len field or except len field except, some headers also comprise OFFSET (skew) field (displaying) contained to the skew (in nonvolatile memory page) of the end of the data be associated with header.(in certain embodiments, if the last one in variable-size data segment is across a nonvolatile memory page, so OFFSET is the number of the skew in follow-up nonvolatile memory page or the byte in follow-up nonvolatile memory page.) the usual only one implemented in len field or OFFSET field, because when piling up variable-size data segment without the space wasted, the starting position of each in the variable-size data segment in nonvolatile memory page and end position by the first variable-size data segment in nonvolatile memory page starting position (such as, after header, as in the figure 7) and the list hint of LEN or OFFSET field.

With reference to figure 9, it shows the diagram of the selected details of the embodiment of map entry 900.According to various embodiment, the entry of mapping comprises one or many person in the following:

-physical non-volatile memory page address,

To the skew (such as, OFFSET) of variable-size data items in-nonvolatile memory page,

The length (such as, LEN__M128) of-variable-size data items, and

-other control information.

In certain embodiments, to length encode (for example, by skew) with make be zero value correspond to and specify minimum length.For example, if minimum length is 128 bytes, be so LEN_M128 value expression 128 bytes of 0.In other embodiments, specify the data filling of minimum length to the size of at least specifying minimum length by being compressed to be less than.

In various embodiments, SRO-VFTL map entry is greater than VFTL map entry, because SRO-VFTL map entry stores full migration and the byte length of corresponding data.Therefore, reducing the size of map entry when being stored in nonvolatile memory can be favourable.In typical use, usually at least read sequentially with a certain granularity and/or the average number of map unit in proper order that is greater than 1 and write data.Utilize the map entry compressed format of the character in proper order of write to implement also relatively inexpensive and produce high mapping compressibility.Identical nonvolatile memory page is entered into until leap nonvolatile memory page boundary helps the compression of map entry further by making the data write in proper order.

With reference to Figure 10, it shows the diagram of the selected details of the embodiment of various compressed map entry.Described various map entry comprise uncompressed 1010, there is the nonvolatile memory page address 1020 identical with previous map entry, there is the nonvolatile memory page address identical with previous map entry and in the skew place beginning 1030 of previous ED, and there is the nonvolatile memory page address identical with previous map entry, start in skew place of previous ED and there is the length 1040 identical with previous map entry.

In some embodiments with multistage-mapping, maintain the cache memory of more rudimentary (such as leaf-size class) mapping page.Be uncompressed form through cache map page, thus the quick access undertaken by processor (such as the control processor of main frame or solid-state drive controller) is provided.When mapping page move (such as from nonvolatile memory or dynamic RAM (such as, DRAM)) in cache memory time, described mapping page is unpressed.When rinsing mapping page (such as owing to being modified) from cache memory, compressing mapping page is for storage (being such as stored in nonvolatile memory).According to wherein using DRAM with by some or all in mapping page being stored in dynamic RAM the various embodiments reducing the stand-by period, store the mapping page in dynamic RAM with one or many person in following form: compressed form; Uncompressed form; Optionally, compressed or uncompressed form; And by the indirection table of (variable-size) the compressed version for accessing the mapping page in dynamic RAM.

In certain embodiments, described main frame write data optionally and/or are optionally compressed when the main frame of host write command writes data to and reaches solid-state drive controller place, and it is stored in (such as on the chip) storer of local in the mode of class first in first out (such as, FIFO).For example, in certain embodiments, main frame is write the part (such as preserve the cache memory of one or more page of mapping) of data together with firmware data structure, quick flashing statistics, mapping, the reading data from nonvolatile memory (comprise recycle and read data), the header being written to the data of nonvolatile memory, software code, firmware code and other use to be stored in unified impact damper (UBUF such as, in Figure 11 A).In various embodiments, the various local storage criterions for solid-state drive use one or more private memory.

In certain embodiments, be sent to the Optional of solid-state drive controller in the main frame write data of host write command and/or optionally compress described main frame write data at main frame place.For example, before data-base recording is written to input/output device, described data-base recording is compressed by host data base.

In various embodiments, about each map unit of the data arrived from main frame, to solid-state drive control processor (such as, central processing unit CPU in Figure 11 A) notify in the following one or many person: corresponding map unit address, wherein store the corresponding length of the corresponding topical storage address of data and/or each map unit of variable-size (such as, compressed) host data be associated with corresponding map unit address.In each in the write order of control processor through enabling to determine nonvolatile memory page and nonvolatile memory page, available non-erroneous corrects the total number of decoding byte.Correct the total number of decoding byte according to non-erroneous available in the given one in nonvolatile memory page, control processor is through enabling to determine to be positioned over the header amount in described given nonvolatile memory page and data volume.For example, control processor add up given nonvolatile memory page header (and following the trail of the number of the byte of used up to now header) and add the variable-size data of map unit and header to given nonvolatile memory page one at a time, until described given nonvolatile memory page is full.When given nonvolatile memory page is for time full, the decline of adding the data of the final one in the map unit of given nonvolatile memory page to not to load in given nonvolatile memory page and is used as nonvolatile memory page (such as, continuation data 640) in the end of data part of subsequent one, thus reduce the total number that non-erroneous available in follow-up nonvolatile memory page corrects decoding byte, for new header and data.

In certain embodiments, at particular point in time place, zero or more nonvolatile memory page through enable with main frame write data stuffing and zero or more nonvolatile memory page through enabling to fill with through recycled data.For example, at least two bands can be filled respectively (such as, the redundant block of class FIFO series), a band uses " heat " data (such as, just come from main frame) fill and another band " cold " data (such as, through recycle) fill, and the useful space of zero or more nonvolatile memory page is assigned to each band from impact damper.Continue described example, in various embodiments, main frame write data optionally and/or optionally through enabling to be directed in the torrid zone or cold belt, and through recycled data optionally and/or optionally through enabling to be directed in the torrid zone or cold belt.

In certain embodiments, control processor is through enabling using the one or many person a series of corresponding map unit address, local memory address and corresponding length converted in the following: be written to nonvolatile memory page and a series of headers of Header portion as nonvolatile memory page; Be written to nonvolatile memory page and as the user data part of nonvolatile memory page local storage in proper order part the first start address and the first length, the user data part of described nonvolatile memory page comprises the data of at least one map unit at least partially; Be written to follow-up nonvolatile memory page and as the second start address of the part in proper order of the local storage of the user data ending of follow-up nonvolatile memory page and the second length, described user data ending comprise the data of a map unit a part or for empty; Zero or more being written to nonvolatile memory page fills up the number of byte, wherein for example, uses fill up byte when user data ending is empty and nonvolatile memory page is discontented.Advantageously, control processor is ordered through enabling with the header simply corresponding map unit address of described series, corresponding topical storage address and corresponding length being converted to described series by reformatting and producing the peanut direct memory access (DMA) (such as, the DMA) part being formed nonvolatile memory page (ending of the header of described series, previously nonvolatile memory page, user data part and anyly fill up byte) being sent to nonvolatile memory.

In various embodiments, the compression of main frame write data optionally and/or is optionally enabled.In one example, host write command header length enable compression.In another example, the LBA (Logical Block Addressing) (or mark) according to host write command optionally enables compression.In a further example, if the compression of main frame write data had not reduced the size of main frame write data, compression of so optionally stopping using.If do not enable compression, so main frame write data are stored uncompressedly.According to various embodiment, the entry of mapping indicates corresponding data to be compressed or uncompressed by one or many person in the following: the corresponding positions in each entry of mapping; And/or be stored in the value of the length in each map entry.For example, if map unit is 4KB, the associated data of the Length Indication map entry so for 4KB in map entry is unpressed, and the Length Indication associated data being less than 4KB is compressed.Whether in some embodiments and/or use in sight, specifying institute's storage host to write data with the header that optionally and/or optionally compressed version is associated stored that main frame writes data is compressed.

In certain embodiments, data recirculation is made: select redundant block to be recycled by following operation, described page is read with the order of the nonvolatile memory page writing redundant block, the only reading unit of the header of process containing nonvolatile memory page, look for the LBA (Logical Block Addressing) of each header of data header in the map (or equivalently, map unit address or mark) to check that whether data are still effective, if and data are still effective, the new header that so construction is suitable and command dma are with the part by data to be recycled compilation being new nonvolatile memory page.Then new nonvolatile memory page is written to nonvolatile memory.

With reference to figure 11A, it shows the diagram of the selected details of the embodiment of solid-state drive controller 1100.In certain embodiments, solid-state drive controller 1100 implements one or more quick flashing transitional layer or its part with (such as) by implementing quick flashing transitional layer with host collaboration through enabling.In various embodiments, controller 1100 can be embodied as one or more integrated circuit.

Illustrate as illustrated in Figure 11 A, the I/O receiver (such as SerDes (such as, serializer/de-serializers)) of solid-state drive controller 1100 is coupled to main frame via external interface 1111.Host interface (such as, HIF) receives order (such as read and write order) via SerDes, receives write data and send and read data.Via shared storage (such as, OpRAM), order is sent to CPU (central processing unit).Order described in CPU (central processing unit) decipher and control the other parts of solid-state drive controller via shared storage.For example, CPU (central processing unit) via shared storage command dma is delivered to various data routing launch and receiving element (such as host data path receives segmentation (such as, HDRx) or flash data outlet openings segmentation (such as, FDTx)) and to launch from described data routing and receiving element receives response.

The write data receiving segmentation (such as, HDRx) from host interface in future via host data path are sent to unified impact damper (such as, UBUF).In various embodiments, host data path receives fragmented packets containing the logic in order to optionally and/or optionally to compress and/or to encrypt main frame write data.Then optionally and/or optionally compressed and/or encrypted main frame write data nonvolatile memory will be sent to from unified impact damper via the segmentation of flash data outlet openings and generic flash interface (such as, GAFI).In various embodiments, flash data outlet openings fragmented packets is containing the logic in order to perform encryption and/or scramble and/or error recovery coding.In response to host read command, via generic flash interface from nonvolatile memory read data and via flash data path receive segmentation (such as, FDRx) described data are sent to unified impact damper.In various embodiments, reception segmentation in flash data path is incorporated to wrong correction decoder and/or deciphering and/or separates scramble.In other embodiments, independent error correction decoder (such as, in order to implement the LDPC-D of LDPC code) is through enabling to operate being received fragmented storage " original " data in unified impact damper by flash data path.Then via host data outlet openings segmentation (such as, HDTx) by reading data through decoding and be sent to host interface in unified impact damper.In various embodiments, host data outlet openings fragmented packets contains in order to optionally and/or optionally will read the logic of data deciphering and/or decompression through decoding.In certain embodiments; class RAID and soft decision processing unit (such as, RASP) use for together with LDPC-D to protect the main frame be stored in nonvolatile memory to write data and/or system data in addition and/or to perform soft decision process operation through enabling to produce class RAID redundancy.

According to various embodiment, solid-state drive controller through enabling not implement one or more quick flashing transitional layer, some the quick flashing transitional layers implemented in one or more quick flashing transitional layer, all quick flashing transitional layer or implement the part of one or more quick flashing transitional layer.In one example, main frame performs the more senior demapping section of quick flashing transitional layer, and in solid-state drive controller, perform the more rudimentary demapping section of quick flashing transitional layer.In another example, abstract physics element address (such as reading unit address and span) is sent to main frame and receives abstract physics element address (such as reading unit address and span) from main frame by solid-state drive controller, and LBA (Logical Block Addressing) (or mark) is mapped to abstract physics element address by main frame.Solid-state drive controller locates described particular data through enabling with the identifier (such as LBA (Logical Block Addressing) (or mark)) via the particular data be associated with abstract physics element address be stored in header.In a further example, the skew in the mapping generation nonvolatile memory page address of LBA (Logical Block Addressing) (or mark) at main frame place, nonvolatile memory page and byte length.Solid-state drive controller several reading units through enabling to determine to treat to access in the nonvolatile memory are to retrieve the specific data in one or more nonvolatile memory page.Advantageously, in one or many person in instances, maintained the details (such as, the number of bytes of user data of every nonvolatile memory page or the size of reading unit) of error recovery decoding by solid-state drive controller, thus reduce the added burden on main frame.

With reference to figure 11B, the diagram of the selected details of the embodiment of its display data path segments.Data routing segmentation 1190 the host data path of graphic extension Figure 11 A can receive segmentation or the segmentation of flash data outlet openings.Data routing segmentation 1190 comprises reads sequencer 1130, write sequencer 1140 and zero or more data path unit (such as, DPU).Figure 11 B graphic extension has the example of two data path unit 1150-1 and 1150-2.

Read sequencer 1130 and be coupled to OpRAM (see Figure 11 A) to receive the control information of the data of specifying to be read/access.For example, described information can be address in unified impact damper and/or length or to host interface or generic flash interface order and the order will mixed with data can be specified.Read sequencer 1130 and be also coupled to reader 1110 with (such as) from UBUF, host interface or generic flash interface reading/access data.Read sequencer 1130 through enabling the cross-current reading data and order to be sent to zero or more data path unit 1150-1 and 1150-2 and write sequencer 1140 according to the request received from OpRAM.

Write sequencer 1140 is through enabling the cross-current receiving data and the order sent by reading sequencer 1130.Write sequencer 1140 is coupled to write device 1120 so that data are write (such as) to UBUF, host interface or generic flash interface.Described data write according to the order (such as passing through the order of assigned address and/or length) in the data stream received by write sequencer 1140.Write sequencer 1140 be also coupled to OpRAM (see Figure 11 A) with according to receptions order and transmission about the status information of the data write.For example, status information is written in OpRAM to indicate the ending of the specified portions (such as, a 4KB map unit) of write data stream.

Data path unit 1150-1 and 1150-2 is through enabling with the transform data when data are advanced between reading sequencer 1130 and write sequencer 1140.The order produced by reading sequencer 1130 in data stream optionally and/or is optionally intended to be received by one or many person in data path unit 1150-1 and 1150-2 or write sequencer 1140.The example of data path unit 1150-1 and 1150-2 comprises:

-ciphering unit, it receives the order comprising the encryption salt (initialization vector) being ready to use in encryption and the data encryption will continued according to encryption salt.In a further embodiment, order also comprises the specification of encryption key.

-decryption unit, it receives the order comprising the encryption salt (initialization vector) being ready to use in deciphering and the data deciphering will continued according to encryption salt.In a further embodiment, order also comprises the specification of decruption key.

-compression unit, it receives the order of the beginning on instruction compression unit (such as, map unit) border and compresses the data continued.In various embodiments, order also comprises the data volume of boil down to one unit, compression type, the one or many person be used in maximum working time of compressing and other compression control.

-decompression unit, it receives the order of beginning on instruction compression unit border and the data decompression that will continue.In various embodiments, order also comprise decompress(ion) is condensed to a unit data volume, through the expection size of decompressed data, decompression type, be used for maximum working time of decompressing and other one or many person in controlling that decompresses.

-cyclic redundancy check (CRC) (such as, CRC) unit, it receives the order that comprises the encryption salt (initialization vector) being ready to use in calculating cyclic redundancy proof test value and cyclic redundancy check value in the data continued according to encryption salt and calculating.In a further embodiment, order optionally and/or optionally makes cyclic-redundancy-check unit previous institute calculating cyclic redundancy proof test value can be attached to the previous received data covered by cyclic redundancy check value.

-error recovery coding and/or decoding unit, its receive the order that comprises code check and according to the error-correcting code of described code check the data continued of encoding and/or decode.In a further embodiment, order optionally and/or optionally comprises extra control, such as soft decision process information, a maximum number to be used iteration and other scrambler and/or demoder control information.

In example operation, write order is received in response to from main frame, the command list (CLIST) receiving the reading sequencer of segmentation for host data path is built by CPU (central processing unit), and according to described command list (CLIST), host data path receives segmentation through enabling, via host interface, the write data of write order are transmitted into unified impact damper from main frame.The data path unit that host data path receives in segmentation compressed write data through enabling before being written to unified impact damper in (compressed) write data.Multiple (compressed) map unit is through enabling closely to be piled up in the space without waste in unified impact damper.CPU (central processing unit) is notified by being written to the position of each in (compressed) map unit of OpRAM (receiving the write sequencer of segmentation via host data path) and the status information of size.CPU (central processing unit) is through enabling with the construction header and determine the header of a filling nonvolatile memory page and the amount of (compressed) map unit according to status information.CPU (central processing unit) is further through enabling to build command list (CLIST) for the reading sequencer of flash data outlet openings segmentation so that the nonvolatile memory page of header and data is transmitted into nonvolatile memory.The extra byte being used for error recovery decoding protection through enabling will just be sent to header and the data encoding of nonvolatile memory, thus is added to each in multiple reading unit by the data path unit in the segmentation of flash data outlet openings.After the state having received the write of NVM page from the write sequencer of flash data outlet openings segmentation, the space used by (compressed) map unit at once in recoverable (can reuse) unified impact damper.

In another example operation, reading order is received in response to from main frame, the command list (CLIST) of the reading sequencer of segmentation is received by CPU (central processing unit) construction for flash data path, and according to described command list (CLIST), flash data path receives segmentation through enabling, via generic flash interface, one or more reading unit read from nonvolatile memory is received unified impact damper.In certain embodiments, the data path unit that flash data path receives in segmentation will just be sent to the data decode of nonvolatile memory through enabling to use the extra byte for error recovery decoding protection about each reading unit.In other embodiments, error recovery occurs via independent data routing segmentation (LDPC-D such as, in Figure 11 A).By the accepting state from the flash data path reception write sequencer of segmentation or the write sequencer of (in other embodiments) LDPC-D data routing segmentation by the reception notification CPU (central processing unit) of (calibrated) data in unified impact damper.CPU (central processing unit) is further through enabling to build command list (CLIST) for the segmentation of host data outlet openings via host interface corrected data is transmitted into main frame from unified impact damper at least partially.Corrected data decompressed before being transmitted into main frame in corrected data through enabling by the data path unit in the segmentation of host data outlet openings.After receiving the state of successfully launching corrected data from the write sequencer of host data outlet openings segmentation, the space used by corrected data at once in recoverable (can reuse) unified impact damper.

With reference to figure 11C, the diagram of the selected details of the various embodiments of its display systems according to embodiments of the invention.Described embodiment comprises one or more example of the solid-state drive controller 1100 of Figure 11 A usually.Several solid-state drive 1101a to 1101n comprises solid-state drive controller 1100a to the 1100n being coupled to nonvolatile memory 1199a to 1199n respectively via device interface 1190a to 1190n usually.Described figure graphic extension other embodiment various types of: the single solid-state drive being directly coupled to main frame 1102; Multiple solid-state drives of main frame 1102 are directly coupled to separately respectively via respective external interface 1111a to 1111n; And one or more solid-state drive of main frame 1102 is indirectly coupled to via various interconnection element.

As the example embodiment of single solid-state drive being directly coupled to main frame, an example of solid-state drive 1101a is directly coupled to main frame 1102 (such as, omit, walk around or pass interchanger/group structure/middle controller 1103) via external interface 1111a.As the respective example embodiment being directly coupled to multiple solid-state drives of main frame via respective external interface, each in the Multi-instance of solid-state drive 1101a to 1101n is directly coupled to main frame 1102 (such as, omit, walk around or pass interchanger/group structure/middle controller 1103) via the respective instance of outer interface 1111a to 1111n respectively.As the example embodiment of one or more solid-state drive being indirectly coupled to main frame via various interconnection element, each in one or more example of solid-state drive 1101 is indirectly coupled to main frame 1102 respectively.Each indirect coupling is all via being coupled to external interface 1111a to the 1111n of interchanger/group structure/middle controller 1103 and being coupled to the respective instance of intermediary interface 1104 of main frame 1102.

Some embodiments comprised in the embodiment of interchanger/group structure/middle controller 1103 comprise and to be coupled via memory interface 1180 and can by solid-state drive 1101a to 1101n and/or the card memory 1112C accessed by main frame 102.In various embodiments, one or more solid-state drive 1101a to 1101n, interchanger/group structure/middle controller 1103 and/or card memory 1112C are contained in physics identifiable design module, card or can in insertion element (such as, input/output cards 1116).In certain embodiments, solid-state drive 1101a to 1101n (or its version) is corresponding to being coupled to the serial attached SCSI of the initiator being operating as main frame 1102 (such as, SAS) driver or Serial Advanced Technology Attachment (such as, SATA) driver.

Main frame 1102 through enabling the various elements performing host software 1115, the such as various combinations of operating system (such as, OS) 1105, driver 1107, application program 1109 and many device managements software 1114.Dotted arrow 1107D represents that two-way communication between host software and input/output device (such as, via driver 1107 and application program 1109 (via driver 1107 or directly as (such as, PCIe) virtual function (such as, VF)) any one or many person that data are sent to one or many person in the example of solid-state drive 1101a to 1101n from any one or many person operating system 1105 and data are sent to from one or many person the example of solid-state drive 1101a to 1101n in operating system 1105).

In some embodiments and/or use sight, host software 1115 comprises some the quick flashing transitional layers used together with solid-state drive 1101a to 1101n, all quick flashing transitional layer or part in quick flashing transitional layer.In one example, in various embodiments, driver 1107 implements using at least partially together with solid-state drive 1101a to 1101n of quick flashing transitional layer.In another example, in various embodiments, using at least partially together with solid-state drive 1101a to 1101n of quick flashing transitional layer implemented by many device managements software 1114.

Operating system 1105 comprises for being situated between the driver (by driver 1107 conceptually graphic extension) that connects and/or operate with described driver through enabling with solid-state drive 1101a to 1101n.The various versions of Windows (such as, 95,98, ME, NT, XP, 2000, Server, Vista, 7 and 8), the various versions of Linux (such as, Red Hat, Debian and Ubuntu) and the various versions (such as, 8,9 and X) of MacOS be the example of operating system 1105.In various embodiments, driver be the standard and/or generic driver (being sometimes referred to as " tightening coated " or " pre-installation ") that can operate with standard interface and/or agreement (such as SATA), advanced host controller interface (such as, AHCI) or NVM Express or optionally customize and/or supplier distinctive to make it possible to use the distinctive order of solid-state drive 1101a to 1101n and/or quick flashing transitional layer.Some drivers and/or driver have direct mode operation and enable application-level program (such as application program 1109) so that order is directly delivered to solid-state drive 1101a to 1101n to access (being sometimes referred to as DNA) technology via optimal N AND access (being sometimes referred to as ONA) or direct NAND, thus make custom application even can use the distinctive order of solid-state drive 1101a to 1101n and/or quick flashing transitional layer together with generic driver.ONA technology comprises one or many person in the following: the use of non-standard modifier (prompting); The use of supplier's uniqueness order; The transmission of non-standard statistics, such as, use according to the actual nonvolatile memory of compressed capability; The use of the peculiar agreement of quick flashing transitional layer, such as, transmit reading unit address and span or such as transmit nonvolatile memory page address, skew and byte length; And other technology.DNA technique comprises one or many person in the following: provide the use of reading, write and/or wiping non-standard command or the supplier's uniqueness order accessed without mapping to nonvolatile memory; Such as originally the format of the data of carrying out is provided the use of the unique order of non-standard or supplier of the more direct access to nonvolatile memory by walking around input/output device; And other technology.The example of driver does not support the driver of ONA or DNA, enables the driver of ONA, enables the driver of DNA and enables the driver of ONA/DNA.The driver that other example of driver is that supplier provides, supplier development and/or supplier strengthen and the driver that client provides, client exploitation and/or client strengthen.

The example of application-level program does not support the application program of ONA or DNA, enables the application program of ONA, enables the application program of DNA and enables the application program of ONA/DNA.Dotted arrow 1109D represent application program with for application program (such as, the application program of enabling ONA and the driver enabling ONA such as using operating system to communicate with solid-state drive as middleware when not having application program) input/output device (such as, via the bypass of driver or the bypass via virtual function) between two-way communication.Dotted arrow 1109V represent application program with for application program (such as, the application program of enabling DNA and the driver enabling DNA such as using operating system or driver to communicate with solid-state drive as middleware when not having application program) input/output device (such as, via the bypass of virtual function) between two-way communication.

In certain embodiments, one or more part of nonvolatile memory 1199a to 1199n is used for firmware storage (such as, firmware 1106a to 1106n).Firmware storage comprises one or more firmware image (or its part).For example, one or more image of the firmware that firmware image has performed by (such as, by the CPU (central processing unit) of solid-state drive controller 1100a to 1100n).For another example, firmware image has (for example) by one or more image of the constant of CPU (central processing unit) reference the firmware term of execution, parameter value and non-volatile memory device information.For example, the image of firmware corresponds to current firmware image and zero or more previous (upgrading relative to firmware) firmware image.In various embodiments, firmware provides generic, standard, ONA and/or DNA operator scheme and operating together with one or more quick flashing transitional layer.In certain embodiments, enable one or many person in firmware operation pattern (such as, " unblock " one or more application programming interfaces (such as, API) are carried out) via the key optionally transmitted by driver and/or provide or various software engineering.In a further embodiment, the different persons in firmware image are used for the different person in operator scheme and/or the different persons in quick flashing transitional layer.

In certain embodiments, main frame 1102 comprises the mapping 1108 as implementing the different hardware resource mapped.In other embodiments, demapping section ground or fully via mapping 1108 and/or mainframe memory 1112H and/or via the mapping 1141 in solid-state drive controller 1100 and/or implement via card memory 1112C.Map 1108, mainframe memory 1112H, example one or more volatibility that to be (such as) implement via DRAM, SRAM and/or quick flashing or other non-volatile memory device of mapping 1141 in solid-state drive controller 1100 and card memory 1112C and/or non-volatile memory device.Other example of mainframe memory is that system storage, main frame primary memory, host cache, host-accessible memory and input/output device can access memories.In some embodiments and/or use in sight (such as there is input/output cards 1116 and use the optional card memory 1112C of Figure 11 C as some embodiments of memory storage (for mapping at least partially)), the mapping in one or more input/output device and/or main frame 1102 access card storer 1112C.

In various embodiments, one or many person in the example of main frame 1102 and/or solid-state drive 1101 is through enabling to access mapping 1108, mainframe memory 1112H, card memory 1112C and/or map 1141 and can be used for LBA (Logical Block Addressing) (or other specificator to preserve and to retrieve, such as mark) be converted to the whole or any part of the map information of one or more part of input/output device nonvolatile memory (element of one or many person in the example of such as nonvolatile memory 1199a to 1199n) non-volatile memory location (such as block and/or page address and/or reading unit address) that is target.Conceptually, can there is single mapping, and according to various embodiment, the control of mapping and/or storage and/or use provides by one or many person in main frame 1102 and/or by solid-state drive controller 1100a to 1100n.

In some embodiments lacking interchanger/group structure/middle controller 1103, solid-state drive 1101a to 1101n is directly coupled to main frame 1102 via external interface 1111a to 1111n.In various embodiments, solid-state drive controller 1100a to 1100n is coupled to main frame 1102 via one or more intermediate level of other controller (such as RAID controller or i/o controller).In certain embodiments, solid-state drive 1101a to 1101n (or its version) is corresponding to SAS drive or SATA drive, and interchanger/group structure/middle controller 1103 corresponds to expander, described expander is coupled to initiator again, or alternatively, interchanger/group structure/middle controller 1103 corresponds to bridge, and described bridge is indirectly coupled to initiator via expander.In certain embodiments, interchanger/group structure/middle controller 1103 comprises one or more PCIe interchanger and/or group structure.

In various embodiments, such as wherein main frame 1102 is as computation host (such as, computing machine, workstation computer, server computer, storage server, personal computer, laptop computer, mobile computer, net book and/or flat computer) embodiment in some embodiments, computation host is optionally through enabling with and/or remote server local with one or more (such as, optional server 1118) communication is (such as, via optional I/O and memory storage/resource 1117 and optional LAN/Wide Area Network (such as, LAN/WAN) 1119).For example, described communication realizes this locality and/or remote access, management and/or the use of any one or many person in solid-state drive element.In certain embodiments, described communication is completely or partially via Ethernet.In certain embodiments, described communication is completely or partially via optical-fibre channel.In various embodiments, LAN/Wide Area Network 1119 represents one or more LAN and/or Wide Area Network, any one or many person in such as, network in server farm, the coupling network of server farm, Metropolitan Area Network (MAN) and the Internet.

In various embodiments, solid-state drive controller and/or computation host non-volatile memory controller are embodied as non-volatile storage components together in conjunction with one or more nonvolatile memory, such as USB (universal serial bus) (such as, USB) memory module, general flash memory devices are (such as, UTS) memory module, Compact Flash are (such as, CF) memory module, multimedia card are (such as, MMC) memory module, secure digital (such as, SD) memory module, memory stick memory module and xD picture card memory module.

In various embodiments, whole or any part of solid-state drive controller (or computation host non-volatile memory controller) or its Function implementation in described controller by the main frame (such as, the main frame 1102 of Figure 11 C) that is coupled with it.In various embodiments, whole or any part or its function of solid-state drive controller (or computation host non-volatile memory controller) are via hardware (such as, logical circuit), software and/or firmware (such as, driver software or solid-state drive control firmware) or its any combination and implement.

With reference to Figure 12, it shows the process flow diagram 1200 writing data into nonvolatile memory.In step 1202, process starts, and in step 1206, make about data write (storage) that will such as, be associated with the specific one in multiple mark (or other unique identifier, object identity or LBA (Logical Block Addressing)) determination to nonvolatile memory.For example, describedly determine to be made by one or many person in application program, operating system, supervisory routine or other software any or firmware module.In certain embodiments, writing data is variable-size (such as, may change with each write operation).In other embodiments, write data are unit of several fixed sizes, such as several SATA sectors.

In step 1210, write order and (possible variable-size) the write data that are associated are received.In one example, application program uses system call that write order and write data (such as via the pointer pointing to data) are sent to driver.In another example, write order is sent to solid-state drive controller together with information thus makes solid-state drive controller can retrieve the write data that are associated by main frame.For example, write order comprises SATA Native Command Queue (such as, NCQ) label, and Native Command Queue label is used for obtaining the write data that are associated.

In step 1214, optionally and/or optionally compress or otherwise reduce the size of (possible variable-size) write data.Writing data even if be associated has been variable-size, and compression also may be able to reduce to be associated to write the size of data further.In certain embodiments, (possible variable-size, may compressed) write data optionally and/or optionally encrypted.

In step 1218, next of nonvolatile memory determining writing data does not write physical location (in physical address space).In one example, determine that next does not write physical location next-door neighbour and is bordering on the variable-size data (not wasting the space in nonvolatile memory) previously write.In another example, determine that next does not write physical location in the reading unit identical with previous write variable-size data and starts.In certain embodiments, to determine that next does not write physical location be according to band specified in write order.

In step 1222, will (possible variable-size, may compressed) write data be stored in nonvolatile memory determine that next does not write physical locations.In certain embodiments, (possible variable-size, possibility are compressed) write data are pieced together in the image (such as, will being written to a part for the impact damper of nonvolatile memory page) of nonvolatile memory page by hardware cell.

In step 1226, the header of the identifier comprising write data is stored in and writes in the nonvolatile memory page identical at least partially of data with (possible variable-size, possibility are compressed).For example, header is stored in the nonvolatile memory page identical at least partially write data with (the possible variable-size, may be compressed) in such as Fig. 6, and/or header is stored in the reading unit identical at least partially writing data with (the possible variable-size, possible compressed) in such as Fig. 5.According to various embodiment, identifier is one or many person in the following: identical with the specific markers of write data; The function of the specific markers of write data; Via the identifier that a table is associated with the specific markers of write data; Be stored in the unique identifier in the middle of all data in nonvolatile memory; And aforementioned every any combination.

According to various embodiment, the storage of (possible variable-size, possibility are compressed) write data and/or header betides in step 1222 and/or 1226 and/or is postponed, until the nonvolatile memory page of accumulation header and data (such as from multiple write operation).In certain embodiments, as being stored into the part of nonvolatile memory and execution error correction coding.In a further embodiment, several error recovery decoding bytes are attached to the User Part of each reading unit to form the reading unit as being stored in nonvolatile memory by error recovery coding.Still further in embodiment, before error recovery coding, perform scramble.

In step 1230, return determine that next does not write the instruction of physical location.In one example, determine that the instruction that next does not write physical location comprises reading unit address, such as, write the address of the one of data in reading unit for storing (possible variable-size, may compressed).Continue described example, in certain embodiments, determine that next instruction not writing physical location comprises by several reading units of (possible variable-size, may compressed) write data span further, for example, must be read to retrieve all and be no more than several reading units that (possible variable-size, possibility are compressed) writes data.One or many person in several reading units described optionally and/or optionally contains the data be associated with other data in mark, but each in several reading units described contains at least some write data in (possible variable-size, possibility are compressed) write data.In another example, determine that instruction that next does not write physical location comprises the address of nonvolatile memory page and/or (possible variable-size, may be compressed) writes the skew in the nonvolatile memory page at least partially of data for storing.Continue another example described, in certain embodiments, institute determines that the instruction that next does not write physical location comprises further, and (possible variable-size, possible compressed) writes length in the byte of data.Another example described in further continuation, still further in embodiment, (possible variable-size, possibility are compressed) write data span more than one nonvolatile memory page (such as, start in the first nonvolatile memory page and proceed in one or more follow-up nonvolatile memory page).For example, when skew place in the first nonvolatile memory page and remaining users data volume are afterwards less than the length in the byte of (possible variable-size, possibility are compressed) write data, (possible variable-size, possibility are compressed) write data span more than one nonvolatile memory page.

In step 1234, maintain make specific markers with determine the mapping that the instruction that next does not write physical location is associated.For example, maintain the data that described mapping makes to be associated with specific markers to be retrieved by subsequent read operations.

In step 1238, maintain statistics according to write order.For example, write the data be associated with specific markers and use the particular space amount and the particular space amount optionally and/or optionally discharged in the redundant block of the older version wherein storing the data be associated with specific markers that wherein write in the redundant block of data.Statistics follows the trail of institute's usage space amount in each redundant block (or equivalently, in certain embodiments, free space amount).In step 1290 place, described process terminates.

In certain embodiments, lock (such as semaphore) for prevent process 1200 at least partially period to map access at least partially.For example, in certain embodiments, the entry locking the mapping be associated with specific markers from step 1210 to 1234 is to prevent from accessing other of entry when just upgrading entry.

With reference to Figure 13, it shows the process flow diagram 1300 reading data from nonvolatile memory.In step 1302 place, process starts, and in step 1306 place, make the determination of the data such as, be associated about the specific one read from nonvolatile memory in (retrieval) and multiple mark (or other unique identifier, object identifier or LBA (Logical Block Addressing)).For example, describedly determine to be made by one or many person in application program, operating system, supervisory routine or other software any or firmware module.In certain embodiments, data are variable-size (such as, may change with each read operation).In other embodiments, data are several fixed size unit, such as several SATA sectors.

In step 1310, specific markers is searched in the map to determine the instruction with the institute's storage version physical location in the nonvolatile memory marking the data be associated.According to various embodiment, Map Searching is by initiating the software module of read operation or being performed by another software module of the calling software module by initiation read operation.For example, application program initiates read operation, and the driver layer on main frame or the firmware layer on solid-state drive controller perform Map Searching.

In step 1314, the reading order of the instruction of the physical location had in nonvolatile memory is received.In one example, after the driver layer executed Map Searching on main frame, the instruction of the physical location in reading order and nonvolatile memory is sent to solid-state drive controller by driver layer.In another example, after first processor executed Map Searching in solid-state drive controller, the instruction of the physical location in reading order and nonvolatile memory is sent to and controls the second processor in the solid-state drive controller of the access of nonvolatile memory by first processor.

In step 1318, the instruction of the physical location in nonvolatile memory is used to determine position and the number of the reading unit of the institute's storage version containing the data be associated with specific markers in nonvolatile memory.In one example, the instruction of physical location comprises reading unit address, such as, for storing the address of the one in one or more reading unit of institute's storage version of the data be associated with specific markers.Continue described example, in certain embodiments, the instruction of physical location comprises the number of one or more reading unit further, for example, must be read to retrieve the whole of the data be associated with specific markers and be no more than the number of the reading unit of institute's storage version.(one or many person in one or more reading unit optionally and/or optionally contains the data be associated with other data in mark, but each in one or more reading unit contains at least some version in institute's storage version of the data be associated with specific markers.) in another example, the instruction of physical location comprise nonvolatile memory page address and/or for the skew in the nonvolatile memory page at least partially of institute's storage version of storing the data be associated with specific markers.Continue another example described, in certain embodiments, the instruction of physical location comprises the length in the byte of institute's storage version of the data be associated with specific markers further.Another example described in further continuation, still further in embodiment, institute's storage version of the data be associated with specific markers across more than one nonvolatile memory page (such as, start and proceed in one or more follow-up nonvolatile memory page) in the first nonvolatile memory page.For example, when skew place in the first nonvolatile memory page and remaining users data volume are afterwards less than the length in the byte of institute's storage version of the data be associated with specific markers, institute's storage version of the data be associated with specific markers is across more than one nonvolatile memory page.Another example described in further continuation, according to the skew in the byte of institute's storage version of the data be associated with specific markers and length, determine the number of the one in one or many person in the reading unit in the first nonvolatile memory page and the reading unit in the first nonvolatile memory page according to the number of the reading unit in the first nonvolatile memory page and/or size.If institute's storage version of the data be associated with specific markers is across more than one nonvolatile memory page, so use similar procedure to determine the extra reading unit at least partially of the institute's storage version containing the data be associated with specific markers in follow-up nonvolatile memory page about the follow-up nonvolatile memory of one or more in nonvolatile memory page page.

In step 1322, read institute from nonvolatile memory and determine reading unit.In certain embodiments, reading unit execution error correction decoder is being stored in nonvolatile memory to correct and/or is being sent to nonvolatile memory or any mistake of generation during transmitting from nonvolatile memory.In a further embodiment, after error correcting/decoding, solution scramble is performed.Because the error recovery of determined reading unit is encoded, therefore determine both the error recovery decoding bytes several byte packet read from nonvolatile memory contained in the user data in reading unit and each in reading unit.In certain embodiments, the number (such as) of the error recovery decoding byte in each in reading unit dynamically changes because of the loss of nonvolatile memory under the control of solid-state drive controller.In various embodiment and/or use sight, such as when at least one in determined reading unit contain with the data that are associated of another one in mark at least partially time, determine that the total number of the byte of the user data in reading unit exceedes the length in the byte of institute's storage version of the data be associated with specific markers.

In step 1326, extract institute's storage version of the data be associated with specific markers from determined reading unit.In certain embodiments, extraction is the identifier according to possessing reading order.According to various embodiment, identifier is one or many person in the following: identical with the specific markers of data; The function of the specific markers of data; The identifier that is associated with the specific markers of data is shown via one; Be stored in the unique identifier in the middle of all data in nonvolatile memory; And any combination of foregoing teachings.In one example, reading unit comprises one or more header, as illustrated in figure 5, and the coupling one using identifier to determine in header, then use described coupling header to locate institute's storage version of the data be associated with specific markers in determined reading unit.In another example, the instruction of physical location comprise specify determine the information of the position of institute's storage version of the data be associated with specific markers in reading unit.According to various embodiment, institute's storage version of the data be associated with specific markers is variable-size.For example, the data be associated with specific markers are compressed before storing, and/or the data self be associated with specific markers are variable-size.

In step 1330, institute's storage version of the data be associated with specific markers is optionally and/or optionally through to decipher and/or optionally and/or optionally through decompressing to produce the data be associated with specific markers.

In step 1334, return the data be associated with specific markers in response to read operation.

In step 1338, maintain statistics according to reading order.In one example, a reading order access given number non-volatile memory block determines reading unit to retrieve, and maintains the statistics of the number of the reading interference incident of the every non-volatile memory block of counting.In another example, a reading order access given number non-volatile memory block determines reading unit to retrieve, determine that the error recovery of reading unit corrects several the corresponding mistakes in each that institute determines in reading unit, and maintain the maximum number wrong statistics corrected in any reading unit in each in non-volatile memory block.In step 1390 place, described process terminates.

Usually for reading not across the data of the single map unit of multiple nonvolatile memory page, treat that the number of the reading unit of institute's storage version of the data accessing to obtain map unit in nonvolatile memory page is less than all reading units in nonvolatile memory page.In addition, because institute's storage version of the data of map unit is variable-size, therefore treat that the number of the reading unit accessed in nonvolatile memory page is different from the number treating the reading unit accessed in nonvolatile memory page for the second reading order with reference to the second LBA (Logical Block Addressing) (or mark) with reference to the first LBA (Logical Block Addressing) (or mark) for the first reading order, the second LBA (Logical Block Addressing) is different from the first LBA (Logical Block Addressing).In certain embodiments, the described number reading unit treated in the access of nonvolatile memory page is only read from nonvolatile memory page.That is, the reading unit of a part for institute's storage version of the data containing map unit reading unit is only read so that institute's storage version of the data of access and retrieval map unit from nonvolatile memory.

With reference to Figure 14, it shows the process flow diagram making data recycle in the nonvolatile memory.In step 1402 place, process starts, and in step 1406, makes the determination in the region of the band recycle about nonvolatile memory.According to various embodiment and/or use sight, described region is one or many person in the following: redundant block; One or more non-volatile memory block; The part maintaining free space and/or institute's usage space statistics within it of nonvolatile memory; The part maintaining wear leveling statistics within it of nonvolatile memory; And aforementioned every any combination.According to various embodiment and/or use sight, recycle is performed to one or many person in the following: the garbage collection (total free space) in nonvolatile memory; The wear leveling (to keep the block of nonvolatile memory relatively equal in corresponding program/erase counting) of nonvolatile memory; And the procedural error relevant with nonvolatile memory and/or exception, such as program mal, excessively read interference and/or excess error rate.In a further embodiment, (such as cross over multiple solid-state drive) globally by main frame and perform recycle.

In step 1410, one or more nonvolatile memory page is read from the region of nonvolatile memory.In certain embodiments, integrally error recovery is carried out to nonvolatile memory page.Error recovery is carried out to all reading units in nonvolatile memory page.In other embodiments, only first error recovery is carried out to the part that the determination of nonvolatile memory page contains header (illustrated in such as Fig. 6), if and determine (such as, step 1426) nonvolatile memory page containing the data needing recycle, so error recovery is carried out to the other parts of nonvolatile memory page.

In step 1414, extract header from nonvolatile memory page.In one example, in embodiment illustrated in such as Fig. 5, extract header from each reading unit in each nonvolatile memory page.In another example, in embodiment illustrated in such as Fig. 6, extract header from a part (first one or more reading unit in each in such as nonvolatile memory page) for each nonvolatile memory page.

In step 1418, dissect from nonvolatile memory page extract header to determine the identifier of the data be associated with (such as) in nonvolatile memory page.

In step 1422, search identifier in the map to determine the corresponding instruction of the data physical location be in the nonvolatile memory associated to identifier.In certain embodiments, identifier is identical with the respective markers of the data used when writing nonvolatile memory.In other embodiments, identifier and out of Memory (such as solid-state drive identifier) are combined to form the mark searched in the map.In still other embodiment, maintain the mapping making identifier be associated with mark and/or identifier is associated with the instruction of the data physical location being in the nonvolatile memory associated with identifier.

In step 1426, any data be associated with identifier still for current (in the nonvolatile memory page of positive recycle) are written to the new physical locations in nonvolatile memory.For example, corresponding reading unit address is converted to by the corresponding instruction of the data that identifier is associated physical location in the nonvolatile memory, if and corresponding reading unit address is in the nonvolatile memory page of positive recycle, the nonvolatile memory page of so positive recycle contains the latest edition of the data be associated with identifier.In various embodiments, be similar to the step 1218 to 1230 of process 1200 and perform the new physical locations be still written to for current data in nonvolatile memory will be associated with identifier.In various embodiments, if compression and/or encryption be still current data, so with compressed and/or rewrite still for current data through encrypted form " in statu quo ".In certain embodiments, by still for current data from the nonvolatile memory page of positive recycle move to new nonvolatile memory page in solid-state drive controller (and will still for current data are sent to main frame to make to be still current data recirculation).In other embodiments, recycle comprises still for current data are sent to main frame and to be similar to process 1200 and to rewrite be still current data.In a further embodiment, cross over multiple solid-state drive and perform recycle globally, and for recycle object, by the one that was previously stored in solid-state drive still for current rewriting data is to the another one in solid-state drive.

In step 1430, upgrade the instruction of the new physical locations of any data mapped to reflect recycle.

In step 1434, the determination that whether will process more plurality of nonvolatile memories page is in the zone made.If so, so process proceeds to step 1410 to continue to make other nonvolatile memory page recycle.

In step 1438, during process recycling, maintain statistics according to the reading of nonvolatile memory and write.In one example, a reading non-volatile storage access given number non-volatile memory block to retrieve nonvolatile memory page, and maintains the statistics of the number of the reading interference incident of the every non-volatile memory block of counting.In another example, a reading non-volatile storage access given number non-volatile memory block is to retrieve nonvolatile memory page, the error recovery of nonvolatile memory page corrects several the corresponding mistakes in each in the reading unit of error correcting/decoding of nonvolatile memory page, and maintains the statistics of the maximum number mistake corrected in any reading unit in each in non-volatile memory block.In a further example, made by write nonvolatile memory data recirculation use and wherein write the particular space amount in the redundant block of recycled data, and optionally and/or optionally discharge the particular space amount in the redundant block of positive recycle.Statistics follows the trail of institute's usage space amount in each redundant block (or equivalently, in certain embodiments, free space amount).In certain embodiments, when institute's usage space amount in the region of positive recycle goes to zero, no longer make to be still current (not overriding) data recirculation in described region, and process 1400 can complete before all nonvolatile memory pages in the region of the positive recycle of reading.In step 1490 place, described process terminates.

In certain embodiments, lock (such as semaphore) for prevent process 1400 at least partially period to map access at least partially.For example, in certain embodiments, the entry locking the mapping be associated with the one identifier with current data from step 1422 to 1430 is to prevent from accessing other of entry when just upgrading entry.

According to various embodiment, the region to be recycled of Selection of chiller nonvolatile memory; The region to be recycled of nonvolatile memory selected by solid-state drive controller; The region to be recycled of nonvolatile memory selected by main frame for first reason, and the region to be recycled of nonvolatile memory selected by solid-state drive controller for the second different reason; And aforementioned every any combination.In one example, main frame performs whole selections in the region to be recycled of nonvolatile memory.In another example, the region to be recycled of nonvolatile memory selected by main frame for garbage collection reason, and the region to be recycled of nonvolatile memory selected by solid-state drive controller for wear leveling reason.In a further example, the region to be recycled of nonvolatile memory selected by main frame for garbage collection and wear leveling reason, and the region to be recycled of nonvolatile memory selected by solid-state drive controller for unusual condition and/or mistake (such as program mal, excessively error recovery decoding error or reading interference incident) reason.In a further embodiment, solid-state drive controller is through enabling that one or more statistics (such as program/erase counting and/or institute's usage space statistics) of nonvolatile memory is delivered to main frame.For example, statistics is via the reserve part in the LBA (Logical Block Addressing) space of solid-state drive controller or by transmitting as daily record (such as SMART daily record) in order to the special command of reading and/or write statistics.In some embodiments and/or use sight, statistics is delivered to main frame and makes main frame can select the region to be recycled of nonvolatile memory, and solid-state drive controller is through enabling with the maintenance from main frame unloading statistics.

In certain embodiments, solid-state drive controller is through enabling to make the recycle at least partially of nonvolatile memory independent of main frame and being delivered to main frame through more new physical locations.For example, in response to unusual condition and/or mistake, such as program mal, excessively error recovery decoding error or reading interference incident, the region of the necessary recycle of solid-state drive controller determination nonvolatile memory.Header in the region of solid-state drive controller reading non-volatile storage and any still for current data are repositioned onto corresponding new physical locations in the different piece of nonvolatile memory by the region of nonvolatile memory.According to various embodiment, in one or more embodiment: solid-state drive maintains and maps and can upgrade described mapping with reflection still for the corresponding new physical locations of current data; The unitary part that solid-state drive controller maintains the data of being reorientated by solid-state drive controller maps, described unitary part map make in the region of nonvolatile memory still for the instruction of the physical location of current data is associated with corresponding new physical locations; Corresponding new physical locations is delivered to main frame together with the information (being still such as the corresponding identifier of current data) from header by solid-state drive controller, and main frame upgrades mapping; And aforementioned every any combination.Advantageously, can access be still that current data are until the region of erasable nonvolatile memory in the region of nonvolatile memory and corresponding both new physical locations.In a further embodiment, not the region of erasable nonvolatile memory until after upgrading map with corresponding new physical locations.For example, main frame informs that solid-state drive controller upgrades mapping, and then only solid-state drive controller through enabling the region with erasable nonvolatile memory.

In various embodiments, main frame (such as) by request several nonvolatile memory pages to be read or be sent to main frame several extract header and control the reading (step 1410) of nonvolatile memory page from the nonvolatile memory for recycle.According to various embodiment, main frame performs header and dissects at least some step in (step 1418) and/or solid-state drive controller (such as) by pre-service and/or reformatting and/or filter institute and extract header and perform at least some step in header anatomy.In a further embodiment, main frame performs Map Searching (step 1422) and determines whether any data of needing in overwrite data.Rewrite (step 1426) by solid-state drive controller under the control of main frame (such as by main frame for any still for current data and occur " rewritings " order) execution.Rewrite command is similar to write order, but does not have write data, and rewrite command comprises the instruction of the physical location (just making data from the position of its recycle) in nonvolatile memory as reading order.Be similar to write order, rewrite command returns the instruction of the new physical locations of institute's overwrite data, and main frame performs step 1430 to upgrade mapping.In the one embodiment of the major part of main frame implementation 1400 wherein, it is still the current buffer position of data in solid-state drive controller that rewrite command comprises.

In certain embodiments, the part of the communication protocol between the unique order hosted of non-standard and/or supplier and solid-state drive controller.According to various embodiment, communication protocol is one or many person in the following: SATA, small computer systems interface are (such as, SCSI), SAS, periphery component interconnection express delivery are (such as, PCIe), NVM express delivery (Express) (nonvolatile memory), the upper SCSI of PCIe are (such as, SOP), other agreement any of communicating between two electronic installations of Mobile Express, USB, UFS, embedded multi-media card (such as, eMMC), Ethernet, optical-fibre channel or be suitable for.In one example, the transmission of instruction between main frame and solid-state drive controller of physical location uses supplier's uniqueness to order, the unique version of the supplier that such as standard reads and write is ordered.In another example, by be used for recycle extract header and be delivered to main frame with log page (such as SMART log page) form from solid-state drive controller.In a further example, extract header and be similar to and read data and processing, but " read institute by means of supplier's uniqueness and extract header " and order and read.

According to various embodiment, any one in the step of process 1200 and/or process 1300 and/or process 1400 is performed by one or many person in the following: the main frame being coupled to solid-state drive controller; Be coupled to the solid-state drive controller of main frame; And aforementioned every any combination.In one example, main frame performs Map Searching and map and maintain.In another example, in main frame and solid-state drive controller any one or both perform the determination of number of reading unit.In a further example, solid-state drive controller performs piece write data together in nonvolatile memory page (such as, step 1222).In one example, under the control of main frame, write data are pieced together in the nonvolatile memory page image in the impact damper of solid-state drive controller.In another example, solid-state drive controller performs from reading unit extraction data (such as, step 1326).In a further example, solid-state drive controller perform compression (such as, step 1214) and decompress (such as, step 1330).In one example, solid-state drive controller maintains statistics (such as, step 1238 or step 1338).In another example, main frame performs the region (such as, step 1406) to be recycled determining nonvolatile memory.In a further example, solid-state drive controller performs to be recycled is still moved to reposition (such as, step 1426) for current data from old position.

In certain embodiments, main frame and/or solid-state drive controller maintain the table that each in multiple regions of nonvolatile memory is associated with specified properties and/or feature.In one example, described table makes each in the region of nonvolatile memory be associated with the specific one in multiple code check (error-correcting code intensity), thus the data volume be stored in each in region can be changed according to " health " of each in region.Comparatively healthy area uses higher (more weak) code check and through enabling to store comparatively multi-user data, and comparatively weak-strong test uses lower (stronger) code check and through enabling to store less user data (but through enabling to correct more mistake).In another example, defectiveness or fault and should by the region used in described table indicating area.For example, when NAND quick flashing, some blocks in multiple pieces of NAND quick flashing are also even defective when NAND quick flashing is new, and other block in described piece is at the life period possible breakdown of NAND quick flashing.The block had to skip when multiple NAND flash device writes data (such as, making its striping) is in proper order being crossed in described table instruction.

In certain embodiments, main frame maintains the comparatively superordinate part mapped, and on solid-state drive controller, maintain the more rudimentary part mapped.The comparatively superordinate part mapped makes mark (or LBA (Logical Block Addressing)) be associated to the corresponding instruction of the physical location in nonvolatile memory.Then the more rudimentary part mapped is used to translate the instruction of the physical location in nonvolatile memory further to determine the physical piece of the to be read of nonvolatile memory and/or write by solid-state drive controller.From the angle of main frame, opaque handle is served as in the instruction of physical location, this is because the one in the instruction of physical location is assigned to the certain data objects in write by solid-state drive controller, and solid-state drive controller is through enabling to return certain data objects when indicating to back the correspondence of physical location.In other words, the knowledge of the specific details of the user data tissue in nonvolatile memory is hiding to main frame.Advantageously, solid-state drive controller through enabling to perform at least some management of nonvolatile memory, such as select code check or determine bad block or nonvolatile memory not by other parts that main frame uses.

In one example, when first using the specific one in multiple pieces of nonvolatile memory, each in multiple pages of specific piece is divided into multiple (such as, eight) corresponding reading unit and uses the specific one in multiple code checks of the error recovery being used for specific piece by solid-state drive controller.After a while, when when being reused described specific piece after more loss for specific piece, each in multiple pages of described specific piece is divided into multiple (such as, seven) corresponding reading unit and uses the stronger one in code check for the error recovery of described specific piece by solid-state drive controller.In both cases, when the data that main frame write is stored in specific piece, several reading units that the instruction of the physical location in described specific piece is divided into independent of the page of described specific piece.

In another example, during many persons in multiple pieces of variable-size data span nonvolatile memory, the instruction of the physical location used by main frame independent of any specific piece of nonvolatile memory be in use or be labeled as bad and not by the knowledge used.Continue another example described, the block 7 supposing the specific one in multiple nude films of nonvolatile memory is bad and is not used.When data span in the block 6 of the previous one in described nude film is to subsequent block, solid-state drive controller uses the block 6 of particular die.When data span in the block 7 of previous nude film is to subsequent block, solid-state drive controller skips the block 7 of particular die and the data continued in the block 7 of the lower one in nude film.Main frame does not have the knowledge about which one in data span block.

According to various embodiment, the consistency operation of such as reading scouring and recycle is performed by one or many person in main frame, solid-state drive controller and any combination thereof.

According to various embodiment, any operation of the processor of main frame and/or solid-state drive controller is by any one in one or more CPU (central processing unit), by one or more hardware cell and/or by aforementioned every any combination execution.

According to various embodiment, main frame and/or solid-state drive controller are through enabling the one or many person used in the following: traditional flash transitional layer; Variable-size quick flashing transitional layer; Through reading the variable-size quick flashing transitional layer of optimization in proper order; The quick flashing translation layer of other type any; To the direct access of nonvolatile memory; Any combination of the foregoing teachings in the different physical pieces of nonvolatile memory; Any combination of the foregoing teachings of the Different Logic part of the logical address space of solid-state drive controller; The original physical of nonvolatile memory is accessed; And aforementioned every any combination.

According to various embodiment, main frame write data are optionally and/or optionally encrypted and optionally and/or optionally decrypted after reading from nonvolatile memory before being written to nonvolatile memory.In a further embodiment, be encrypted in optionally and/or optionally compress main frame write data after occur, and deciphering occurred before the data just read optionally and/or are optionally decompressed to turn back to main frame.

Although several example embodiment have herein used solid-state drive and solid-state drive controller, described technology has been applicable to other input/output device and/or data storage device usually, such as hard disk drive.In various embodiments, the nonvolatile memory used in this little input/output device is the nonvolatile memory except " solid-state " nonvolatile memory, the such as magnetic sheet of hard disk drive (such as, using the hard disk drive of stacked tile type magnetic recording).

In certain embodiments, by multinode memory storage or its part (such as hard disk drive or through enabling with the solid magnetic disc of the input/output device with processor (such as CPU) interoperability or non-volatile memory controller, the part of i/o controller (on such as chip RAID nude film) and processor, microprocessor, system-on-a-chip, special IC, hardware accelerator or other all or part of circuit of aforementioned operation is provided) all or part of various combinations of operation that perform are specified by the specification of the process compatibility of carrying out with computer system.Described specification is according to various description, and such as hardware description language, circuit description, net table describe, shelter description or layout description.Example describe including but not limited to: Verilog, VHDL (Very High Speed Integrated Circuit (VHSIC) hardware description language), SPICE (integrated circuit GPS), SPICE variant (such as PSpice), IBIS (input/output (i/o) buffer information norm), LEF (storehouse Interchange Format), DEF (design Interchange Format), GDS-II (Graphic Database System II), OASIS (open artwork system exchange standard) or other describe.In various embodiments, pack processing containing any combination of decipher, compiling, simulation and synthesis to produce, inspection or specify and be applicable to being contained in the logic on one or more integrated circuit and/or circuit.According to various embodiment, each integrated circuit can design according to multiple technologies and/or manufacture.Described technology comprises Programmable Technology (such as, on-the-spot or shelter programmable gate array integrated circuit), semicustom technology (such as, completely or partially based on the integrated circuit of unit) and full custom technology (such as, in fact specialization integrated circuit), its any combination or with the design of integrated circuit and/or other technology any manufacturing compatibility.

One or many person in the following can be used to implement by the function of the graphic execution of Fig. 1 to 14: conventional general processor, digital machine, microprocessor, microcontroller, RISC (Reduced Instruction Set Computer) processor, CISC (complex instruction set computer (CISC)) processor, SIMD (single instruction multiple data) processor, signal processor, CPU (central processing unit) (CPU), ALU (ALU), video digital signal processor (VDSP) and/or the similar computing machine of programming according to the teaching of this instructions, as it will be apparent to those skilled in the art that.Skilled programmar can easily prepare suitable software, firmware, decoding, routine, instruction, operational code, microcode and/or program module based on teaching of the present invention, as those skilled in the art also will understand.Usually described software is performed by one or many person in the processor of machine embodiment from media or several media.

The present invention also implements by the preparation of the following: ASIC (special IC), platform ASIC, FPGA (field programmable gate array), PLD (programmable logic device), CPLD (complex programmable logic device), the door (sea-of-gate) of magnanimity, RFIC (radio frequency integrated circuit), ASSP (Application Specific Standard Product), one or more monolithic integrated optical circuit, be arranged as one or more chip or the nude film of flip-chip module and/or multi-chip module, or pass through the suitable network of interconnection conventional component circuits, as described in this article, those skilled in the art will easily understand the amendment of described conventional component circuits.

Therefore, the present invention also can comprise computer product, and it can be and comprises the machine that can be used for programming to perform medium according to the instruction of one or more process of the present invention or method and/or transmission medium.Input data can be transformed into one or more file in medium to the operation of the execution of instruction contained in computer product together with peripheral circuits and/or represent one or more output signal of physical object or assets (such as audio frequency and/or visual depiction) by machine.Described medium can be including but not limited to: the dish of any type, comprise floppy disk, hard disk drive, disk, CD, CD-ROM, DVD and magneto-optic disk and circuit, such as ROM (ROM (read-only memory)), RAM (random access memory), EPROM (erasable programmable ROM), EEPROM (electrically erasable ROM), UVPROM (ultraviolet light erasable programming ROM), flash memory, magnetic card, light-card and/or be suitable for the media of any type of store electrons instruction.

Key element of the present invention can form the part or all of of one or more device, unit, assembly, system, machine and/or equipment.Described device can be including but not limited to: server, workstation, storage array controllers, storage system, personal computer, laptop computer, mobile computer, palmtop computer, personal digital assistant, portable electron device, battery powdered device, Set Top Box, scrambler, demoder, code converter, compressor reducer, decompressor, pretreater, preprocessor, transmitter, receiver, transceiver, cryptochannel, cellular phone, digital camera, location and/or navigational system, medical equipment, HUD, wireless device, audio recording, audio storage and/or audio playback, videograph, video storage and/or video playback apparatus, gaming platform, peripherals and/or multi-chip module.Those skilled in the art will appreciate that, key element of the present invention can implement the criterion meeting application-specific in the device of other type.

Term "available" and " usually " are intended to pass on when using in conjunction with "Yes" and verb in this article and are described as exemplary and believe enough extensive with the intention including the particular instance presented in described disclosure and both alternate example that can derive based on described disclosure."available" and " usually " should not be construed as expectation or the possibility that certain hint omits corresponding key element as used herein, the term.

Although show with reference to embodiments of the invention and describe the present invention especially, those skilled in the art will appreciate that, the various changes in form and details can be made when not deviating from scope of the present invention.

Claims

1., for using the method through segmentation quick flashing transitional layer, it comprises the following steps:

(A) the write order with the first write data is received at equipment place from main frame;

(B) produce the second write data by compressing described first write data in the apparatus, wherein said second write data have variable-size;

(C) described second write data are stored in the physical locations in nonvolatile memory, wherein said physical location is next non-writing position; And

(D) in response to said write order, the instruction of described physical location is turned back to described main frame from described equipment.

2. method according to claim 1, it is further comprising the steps:

By (i), described instruction is stored in described main frame and the information be associated with described variable-size is stored in described equipment and between described equipment with described main frame, splits the quick flashing transitional layer be associated with described nonvolatile memory by (ii).

3. method according to claim 1, it is further comprising the steps:

Receive the reading order with the described instruction of described physical location from described main frame at described equipment place; And

Described second write data are retrieved by the part reading the described nonvolatile memory comprising described physical location in response to described instruction.

4. method according to claim 3, it is further comprising the steps:

By by as from as described in nonvolatile memory retrieve as described in the second write data decompression and the first write data as described in again being formed; And

By main frame as described in turning back to as the first write data as described in again being formed.

5. method according to claim 1, wherein said write order comprises the identifier of described first write data further, and described method is further comprising the steps:

Described identifier is stored in described nonvolatile memory and writes header that data are associated at least partially as with described second.

6. method according to claim 5, it is further comprising the steps:

The mapping that described identifier is associated with the described instruction of described physical location is maintained in described main frame.

7. method according to claim 5; wherein (i) described identifier is LBA (Logical Block Addressing) and (ii) described instruction comprises the physical address of one in described nonvolatile memory in multiple reading unit, and each in described reading unit comprises corresponding data part and protects the corresponding error recovery information of described corresponding data part.

8. method according to claim 7, wherein (i) described nonvolatile memory has multiple page, (ii) in the one of described physical address in described page, (iii) described first page comprises the first number described reading unit, (iv) both the in described pages comprise the second number described reading unit, and (v) described first number is different from described second number.

9. method according to claim 1, next non-writing position wherein said adjoins previous the write data in the physical address space of described nonvolatile memory.

10., for using the method through segmentation quick flashing transitional layer, it comprises the following steps:

(A) receive from main frame the write order comprising the write data with variable-size at equipment place;

(B) said write data are stored in the physical locations in nonvolatile memory, wherein said physical location is next non-writing position; And

(C) in response to said write order, the instruction of described physical location is turned back to described main frame from described equipment.

11. methods according to claim 10, it is further comprising the steps:

Said write data are retrieved by the part reading the described nonvolatile memory comprising described physical location in response to described instruction.

12. methods according to claim 11, it is further comprising the steps:

Said write data are turned back to described main frame from described equipment.

13. methods according to claim 10, wherein said write order comprises the identifier of said write data further, and described method is further comprising the steps:

Described identifier to be stored in described nonvolatile memory as the header be associated with said write data at least partially.

14. methods according to claim 13, it is further comprising the steps:

15. methods according to claim 13; wherein (i) described identifier is LBA (Logical Block Addressing) and (ii) described instruction comprises the physical address of one in described nonvolatile memory in multiple reading unit, and each in described reading unit comprises corresponding data part and protects the corresponding error recovery information of described corresponding data part.

16. methods according to claim 15, wherein (i) described nonvolatile memory has multiple page, (ii) in the one of described physical address in described page, (iii) described first page comprises the first number described reading unit, (iv) both the in described pages comprise the second number described reading unit, and (v) described first number is different from described second number.

17. methods according to claim 10, next non-writing position wherein said adjoins previous the write data in the physical address space of described nonvolatile memory.

18. 1 kinds of equipment, it comprises:

Nonvolatile memory; And

Circuit, it is configured to: (i) receives the write order with the first write data from main frame; (ii) the second write data are produced by the described first write data of compression; (iii) described second write data are stored in the physical locations in described nonvolatile memory; And the instruction of described physical location is turned back to described main frame in response to said write order by (iv), wherein (a) described second write data have variable-size and (b) described physical location is next non-writing position.

19. equipment according to claim 18, wherein said equipment is embodied as one or more integrated circuit.