CN104679446B

CN104679446B - For the method and apparatus using segmented quick flashing transition layer

Info

Publication number: CN104679446B
Application number: CN201410407142.XA
Authority: CN
Inventors: 厄尔·T·科恩; 苏米特·普里
Original assignee: Infineon Technologies North America Corp
Current assignee: Infineon Technologies North America Corp
Priority date: 2013-08-16
Filing date: 2014-08-18
Publication date: 2017-10-03
Anticipated expiration: 2034-08-18
Also published as: JP6443794B2; TWI637262B; GB2519211A; TW201518944A; GB201414515D0; KR20150020136A; KR102328612B1; DE102014111670A1; CN104679446A; JP2015036982A

Abstract

The present invention is disclosed for the method and apparatus using segmented quick flashing transition layer.Step (A) receives the writing commands with the first write-in data at equipment from main frame.Step (B) produces the second write-in data by compressing the first write-in data in the apparatus.The second write-in data generally have variable-size.Physical locations of the step (C) by the described second write-in data storage in nonvolatile memory.The physical location is next non-writing position.The instruction of the physical location is returned to the main frame by step (D) in response to said write order from the equipment.

Description

For the method and apparatus using segmented quick flashing transition layer

CROSS REFERENCE TO RELATED is referred to

This application case is related to the U.S. Provisional Application case the 61/893,383rd filed an application on October 21st, 2013,2013 The U.S. that U.S. Provisional Application case the 61/888,681st, the September in 2013 that on October 9, in files an application are filed an application on the 3rd faces When the U.S. Provisional Application case the 61/866,672nd filed an application for 16th of application case the 61/873,357th, August in 2013 and It is every in the U.S. Provisional Application case the 61/755th, 169 that on January 22nd, 2013 files an application, the U.S. Provisional Application case One is incorporated in entirety by reference hereby.

This application case is related to the U.S. the 13/053rd, 175 filed an application on March 21st, 2011, the U.S. the 13/th 053, No. 175 is related to the U.S. Provisional Application case the 61/316th, 373 filed an application on March 22nd, 2010, the U.S. Each of No. 13/053,175 and the U.S. Provisional Application case are incorporated in entirety by reference hereby.

This application case further relates to the international application case PCT/US2012/ with 4 days October 2012 international application date 058583, the U.S. Provisional Application case the 61/543rd, 707 that the international application claims are filed an application on October 5th, 2011 Rights and interests, each of the international application case and the U.S. Provisional Application case are incorporated in entirety by reference.

This application case is related to the U.S. the 13/936th, 010 filed an application on July 10th, 2013, the U.S. the 13/th 936, No. 010 are related to international application date in August, the 2012 international application case PCT/US2012/049905 of 8 days, the state Border application case advocates U.S. Provisional Application case that September in 2011 files an application on the 6th the 61/531,551st and August in 2011 9 days The rights and interests of the U.S. Provisional Application case filed an application the 61/521st, 739, the U.S. the 13/936th, 010, the world Each of application case and the U.S. Provisional Application case are incorporated in entirety by reference.

Technical field

The present invention is related to calculating main frame and input/output device technology for one, and exists more particularly to providing The method and/or equipment for the transition layer split between main frame and controller.

Background technology

Conventional solid driver stores fixed integer host logic block in the every page of nonvolatile memory.When When the available size of user data size or the every page of nonvolatile memory is not fixed, it may appear that storage efficiency problem.With The framework of variable-size quick flashing transition layer in solid-state drive is hardware intensive.Page header is used to recognize that user data is deposited The where among multiple reading units in the page of solid-state drive is stored up, and extracts data and is related to and read and dissect page mark first Head.

The content of the invention

It is used for the method using segmented quick flashing transition layer the present invention relates to a kind of.Step (A) connects at equipment from main frame Receive the writing commands with the first write-in data.Step (B) is produced by compressing the first write-in data in the apparatus Raw second writes data.The second write-in data generally have variable-size.Step (C) writes data storage by described second Physical locations in nonvolatile memory.The physical location is next non-writing position.Step (D) is in response to described Writing commands and the instruction of the physical location is returned into the main frame from the equipment.

Brief description of the drawings

Embodiments of the invention are will become apparent from from described in detail below and appended claims and schema, wherein：

Fig. 1 is logical block address selecting to the embodiment of the mapping in the fixed size region in nonvolatile memory page The diagram of details；

Fig. 2 be logical block address to optionally across the variable-size region of nonvolatile memory page mapping implementation The diagram of the selected details of example；

Fig. 3 is the diagram of the embodiment for the nonvolatile memory page for including integer reading unit；

Fig. 4 is choosing of the logical block address to the embodiment of the mapping in the variable-size region across one or more reading units Determine the diagram of details；

Fig. 5 is the diagram of the selected details of the embodiment for the reading unit for including header and data；

Fig. 6 is the diagram of the selected details for the embodiment for including header and the nonvolatile memory page of data；

Fig. 7 is the diagram of the selected details for another embodiment for including header and the nonvolatile memory page of data；

Fig. 8 is the diagram of the selected details of the embodiment of various types of headers；

Fig. 9 is the diagram of the selected details of the embodiment of map entry；

Figure 10 is the diagram of the selected details of the embodiment of various compressed map entrys；

Figure 11 A are the diagrams of the selected details of the embodiment of solid state drive controller；

Figure 11 B are the diagrams of the selected details of the embodiment of data path segmentation；

Figure 11 C are the diagrams of the selected details of the various embodiments of system according to an embodiment of the invention；

Figure 12 is the flow chart for writing data into nonvolatile memory；

Figure 13 is the flow chart that data are read from nonvolatile memory；And

Figure 14 is the flow chart for making data recycle in the nonvolatile memory.

Embodiment

The transition layer that embodiments of the invention are split comprising offer between main frame and controller, the transition layer can：(i) Support the size of data of wide scope；(ii) operated with the data for being not based on block；(iii) in response to write-in data by handle Return to main frame；(iv) data are read using the handle；And/or (v) is embodied as one or more integrated circuits and/or correlation Join firmware.

Main frame is coupled to input/output device (such as solid-state drive (for example, SSD) controller), and input/output is filled Put and be coupled to and/or comprising nonvolatile memory (for example, NVM).The example of main frame includes calculating main frame, server, individual Computer, laptop computer, mobile computer, workstation computer, personal digital assistant, smart phone, honeycomb fashion hand Machine, media player or logger, i/o controller, cheap/RAID (for example, RAID) on chip (for example, ROC) controller and any other device including processor or computer.Main frame initiates to be used to via input/output The request of device access (for example, read or write) nonvolatile memory, and the request by the combination of main frame (for example, extremely The software partially run on main frame) and by input/output device (for example, at least in part on input/output device The firmware of operation) perform.

In certain embodiments, quick flashing translation layer (for example, FTL) by logical block address space (for example by main frame be used for pair Input/output device performs input/output operations) in logical block address (for example, LBA) to be mapped to (or translating into) non-volatile Physical location in property memory (such as NAND Flash nonvolatile memory) is (for example, the physics in physical address space is deposited Store up address).According to various embodiments, the mapping of the logical block address in logical block address space is via one in the following Or many persons and carry out：One-level maps；Two-stage maps；Multistage-mapping；Directly map；Associated mapping；Hash table；B-tree；Trie knot Structure；The cache memory of a part for mapping；And make logical block address and the physical location phase in nonvolatile memory Any other component of association.In a further embodiment, mapping includes multiple entries, such as in logical block address space Each logical block address an entry.

In other embodiments, the mark of corresponding data or other unique identifiers are mapped to non-volatile by quick flashing transition layer Physical location in property memory.For example, the mark can for corresponding data hash function (such as SHA-256 or SHA-512 hash functions), or the object identifier of corresponding data or the corresponding object being stored in corresponding data is stored as, or The file system identifier (such as index node) of corresponding data (wherein corresponding data is file system object).According to various realities Example is applied, the mapping of the mark of corresponding data or other unique identifiers is carried out via one or more of the following：One Level mapping；Two-stage maps；Multistage-mapping；Directly map；Associated mapping；Hash table；B-tree；Trie；A part for mapping Cache memory；And make mark or other unique identifiers are associated with the physical location of nonvolatile memory to appoint What its component.In a further embodiment, mapping includes multiple entries, such as each existing markers or other unique knowledges The entry not accorded with.In still further embodiment, mapping be dynamic in size and its with existing markers or it is other only The number of one identifier increases or decreases and increases or tighten.In one example, the size of mapping with existing markers or it is other only The number of one identifier increases or decreases and linearly increases or tighten.In another example, the size of mapping is with existing markers Or the number of other unique identifiers increases or decreases more than respective threshold step-by-step movement (in discrete chunk form) and increased or tight Contracting.

In various embodiments, multistage-mapping is used to provide unique identifier and/or limits the scope of unique identifier.Lift For example, search mark to produce length than marking short unique identifier in the first associated mapping.Then reflected second The lookup unique identifier is hit to produce the physical location in nonvolatile memory.In a further embodiment, second Mapping is multiple mappings, and for example multiple physically unitary parts for nonvolatile memory are (for example, be present in different solid-states In disk) and/or a functionally mapping of each of different piece (for example, different type).

Each of multiple marks (or handle or logical block address or identifier or other similar terms) generally correspondence In respective data object (or sector or block or project or other similar terms), and quick flashing transition layer make each of mark with The physical location of corresponding data object in the nonvolatile memory is associated.Mark is deposited with corresponding data object non-volatile The relevance of physical location in reservoir is purportedly to be made via mapping, but regardless of how performing the relevance.Although this Various examples in text use the mapping of logical block address, and other examples are using the mapping of object tag or object identifier, But in the spirit of teaching herein, many similar data markers technical batterys can be used with associated mapping techniques.

As used herein, term " map unit " is the size of the data object just mapped by quick flashing transition layer. In certain embodiments, map unit is fixed size, and in other embodiments, the size of data object be it is variable (and Therefore the size of map unit is not fixed).

In certain embodiments, it is mapped on the aligned unit of one or more logic sectors or block and operates.Each mapping Unit is the aligned unit of one or more logic sectors or block.Each map unit has the data of wherein storage mapping unit Corresponding physical location (if map unit is never written to or is trimmed, then include the possibility of NULL physical locations). For example, in the case of 4 kilobytes (for example, KB) map unit, by eight adjoinings (and usual eight sector alignment) string The byte sector of row Advanced Technology Attachment (for example, SATA) 512 is mapped as individual unit.It is commonly used for the mapping of logical block address With every one entry of map unit to store from the logical block address associated with map unit into nonvolatile memory Physical address corresponding translation and/or other control information.

In various embodiments, the size (size of each map unit) of the data object just mapped and/or it is stored in The size variation of data object in nonvolatile memory.In one example, each of entry in mapping storage phase Answer the size of data object.Continue the example, in key/value storage, the bar for accessing mapping is stored according to key Purpose is marked, and value is respective data object, and the size of described value is different among the different persons in key.In another example In, each of entry in mapping stores the amount to read the nonvolatile memory of data storage object to retrieve Instruction.In the version of another example, the amount for the nonvolatile memory specified by the entry mapped is included by mapping The amount of nonvolatile memory specified of entry in positioning one or more institute's data storage objects or part thereof among phase Answer the header of institute's data storage object.In another version of another example, to read to retrieve respective data object Nonvolatile memory amount specify nonvolatile memory page in corresponding institute's data storage object definite size and Position, but regardless of nonvolatile memory error correction how.Extra computation is used to determine accordingly to be deposited to retrieve to read Store up nonvolatile memory relatively large of data object and be enough to perform mistake to the data read from nonvolatile memory The other information of correction.

According to various embodiments, nonvolatile memory is one or more of the following：NAND Flash, it is per unit One position of storage (for example, single level-cell), two positions (for example, multi-level-cell), three positions (for example, three-level cells) or Three with upper and (two dimension) or (for example, the 3D) of three-dimensional for plane；NOR quick flashings；The flash memory of any other type Or electricity erasable memorizer；Phase transition storage (for example, PCM)；Magnetic RAM (for example, MRAM)；Racing track is stored Device；Resistive random access memory (for example, ReRAM)；Battery backed static RAM (for example, SRAM) or Dynamic random access memory (for example, DRAM)；Any magnetical or optical storage media；Or any other non-volatile memories Device.

In certain embodiments, nonvolatile memory (such as) is by physically separating in different input/output devices In (for example, different solid magnetic disc in) or by being organized into one or more groups with different physical locations or access mechanism (for example, a part of nonvolatile memory is NAND Flash, and Part II is phase transition storage).In embodiment In some embodiments, global map is mapped as, each of which entry specifies input/output device mark (for example, ID) and institute State the physical location in input/output device.In other embodiments, by map segments into some, for example often input/ One part of output device, and more senior mapping and/or respective markers function determine in input/output device selected one Person.

Some nonvolatile memories (such as NAND Flash) offer referred to as nonvolatile memory page (or for example, When referring to NAND Flash, quick flashing page) writable (or programmable) unit.Nonvolatile memory page is typically non-volatile The minimum writable unit of memory.In some embodiments and/or using scene, nonvolatile memory page includes several User's (non-erroneous correcting code) data byte and a certain amount of sky that (for example, ECC) is decoded for metadata and error correction Complementary space.Typical NAND Flash page size is 8KB or 16KB or 32KB user data, and is used for the typical case of logical block address Map unit size be 4KB or 8KB.Although (using term " user " data on nonvolatile memory page, some are non- Volatile memory page storage such as mapping data and/or " system " data for verifying point data.User data intends one Refer to the non-erroneous correction decoding portion of nonvolatile memory page.) NAND Flash page be organized into some pieces, generally every piece 128, 256 or 512 quick flashing pages.One piece of minimal size unit for that can be wiped free of, and NAND Flash page is after the page is wiped free of Can be by (again) write-in.

Some nonvolatile memories (such as NAND Flash) there is multiple planes and/or memory block and permit from two or Each of two or more plane abreast accesses and (reads or program or wipe) " many planes " operation of page and/or block.Make Bandwidth is write with many planes programming advantageously increase, and causes basic writing unit to be many planes page rather than single monoplane page. According to the mode using nonvolatile memory, nonvolatile memory page is (or non-volatile as used herein, the term Memory block) represent single nonvolatile memory page (or block) or many plane nonvolatile memories page (or block).

Although term " quick flashing " translation layer (for example, FTL) used herein, turning between logical address and physical address The concept for translating layer is applied to polytype nonvolatile memory.In one example, before rewriting, wiped in big unit Certain types of nonvolatile memory, such as NAND Flash.In another example, some type of non-volatile memory It is lost, so as to cause wear leveling (data to be partially moved into less loss portion from the more loss of nonvolatile memory Point).In a further example, the new model (such as partition strategy magnetic recording) of hard disk magnetic recording, which does not have, is not wiping much bigger Overriding is previously written the ability of data in the case of other data of quantity.In various embodiments, it is coarseness or has Limited persistent types of non-volatile benefits from (quick flashing) translation layer.

With reference to Fig. 1, it shows logical block address to the reality of the mapping in the fixed size region in nonvolatile memory page Apply the diagram of the selected details of example.Some traditional flash transition layers assume nonvolatile memory page (for example, non-volatile memories Device page 100) in bytes of user data number for 2 power (and/or multiple of sector-size) and by nonvolatile memory Page is divided into integer map unit (each is shown as data in Fig. 1).For example, in every nonvolatile memory page In the case of 16KB user data and 4KB map unit, each nonvolatile memory page contains four map units, and Quick flashing transition layer is by the address of each map unit (for example, LBA [M：U] 110) be mapped to corresponding nonvolatile memory page and One of four map units in corresponding nonvolatile memory page.That is, each map entry contains corresponding word Section, for example：

nonvolatile__memory_page_address[n-1：0], mapping_unit_within_ nonvolatile_memory_page[k-1：0]

Wherein nonvolatile_memory_page_address refers to unique non-volatile in nonvolatile memory Storage page, and mapping_unit_within_nonvolatile_memory_page refers to each nonvolatile memory The 2 of page^kOne of the individual big fraction of map unit (k is fixed for whole nonvolatile memory).Sub-page address 104 It is nonvolatile_memory_page_address and mapping__unit_within_nonvolatile_memory_ Page combination.For the addressing based on sector (for example, granularity thinner than map unit), logical block address is (for example, LBA [U- 1：0] relatively low component level 111) specifies several sectors in subdivision, such as map unit (for example, the sector in subpage 113)。

With reference to Fig. 2, it shows logical block address to optionally across the variable-size region of nonvolatile memory page The diagram of the selected details of the embodiment of mapping.Variable-size quick flashing translation layer (for example, VFTL) is conceptive by map unit Address (or mark) is (for example, LBA [M：U] 110) it is mapped to the variable-size region (act of one or more nonvolatile memories page For example, because the data of map unit are compressed before being stored in nonvolatile memory and/or in another reality It is because map unit is by main frame writes as the section of variable-size, such as object memory block in example).However, every Complete byte address 204 is provided in one map entry and byte data length 206 causes map entry to change with traditional flash Layer is larger when comparing.

With reference to Fig. 3, it shows the diagram of the embodiment for the nonvolatile memory page for including integer reading unit.One In a little embodiments, variable-size quick flashing translation layer is by being mapped to Epage (for example, error correction decoding page) address (also referred to as " reading unit " address) and perform from the address (or mark) of map unit to the mapping of physical address.Epage (or read single Member) it is that the error-correcting code that the content for protecting nonvolatile memory can be read and passed through from nonvolatile memory is corrected Minimum data amount.That is, each reading unit contains the wrong school of the correspondence of a certain amount of data and the protection data Positive decoding check byte.In certain embodiments by nonvolatile memory page (such as nonvolatile memory page 100) or The nonvolatile memory page group division for being considered as a unit for write-in purpose is read into integer in other embodiments Unit is taken, as illustrated in figure 3.

In the case of some type of nonvolatile memory (such as NAND Flash), nonvolatile memory is stored in In data be bytes of user data and error-correcting code byte (error recovery information) mixing, and access non-volatile memories The higher level controller of device determines which byte and how many byte of nonvolatile memory are used for user data and non-easy Which byte and how many byte of the property lost memory are decoded for error correction.In various embodiments, it is allowed to per non-volatile The number of variations of the reading unit of storage page.For example, some parts of nonvolatile memory are used than other parts Strong error-correcting code (being used for error correction decoding information using the relatively multibyte in nonvolatile memory page), and have Less reading unit and/or the less data available of every reading unit.In another example, nonvolatile memory is being used When per nonvolatile memory page reading unit number of variations because program/erase circulation often weaken non-volatile deposit Reservoir, so as to cause stronger error-correcting code when more using (loss) nonvolatile memory.

According to various embodiments, used error-correcting code is one or more of the following：Reed-Solomon (for example, RS) code；Bo Si-Cha Dehuli-Huo Kun lattice mother's (for example, BCH) code；Turbine code；Hard decision and/or soft decision low-density Even-odd check (for example, LDPC) code；Polar code；Nonbinary code；Inexpensively/RAID (for example, RAID) code；Wipe Except code；Any other error-correcting code；Foregoing every any combinations, comprising composition, juxtaposition and staggeredly.Typical codeword size is situated between In the scope from 512 bytes (decoding byte plus error correction) to 2176 bytes (decoding byte plus error correction) It is interior.The typical number of error correction decoding byte is in the range of only several bytes to hundreds of bytes.In some many level In unit NAND Flash device, error correction criterion is 40 positions of user data per 1KB.It is fast in some multi-level-cells NAND Dodge in device, code check (ratio of the total byte in user octet and reading unit) is typically smaller than 94%.For example, MLC NAND Flash device has the quick flashing page of 17664 bytes of size, is used to store 16384 bytes Nominals of the quick flashing page Mapped data, and 1280 bytes decode " vacant " byte of byte to be nominally used to store metadata and error correction. Recommendation error correction decoding intensity for MLC NAND Flash devices is every 1 kilobytes, 40 correction bits, and it is using being mapped 70 bytes in the vacant byte of every 1 kilobytes of data byte.

With reference to Fig. 4, logical block address is mapped to across the variable-size region of one or more reading units by its displaying The diagram of the selected details of embodiment.In certain embodiments, VFTL is mapped variable-size (for example, compressed) map unit Address (or mark) (for example, LBA [M：U] 110) it is mapped to and is expressed as reading unit address 404 in each entry of mapping And several reading units of span (number of reading unit) 406.The reading unit referred to by one of map entry exists One or more (in logic and/or physically) are in proper order in nonvolatile memory page, for example, several described reading units Optionally and/or optionally cross over nonvolatile memory page boundary.By data stacking in the various realities in reading unit Apply in example, the entry of mapping is individually typically not enough to positioning associated data (because entry only with reference to reading unit and is not joined Examine the position of the data in reading unit), and further information (such as header) in referenced reading unit is used for accurately Position associated data.

In certain embodiments, data are written to non-in the way of multiple nude film stripings across nonvolatile memory In volatile memory page.Across multiple nude film stripe write datas by only by nonvolatile memory page per band once Ground is written in given nude film and is advantageously carried out larger write-in bandwidth.Block band across multiple nude films is referred to as redundant block, because For in further embodiment and/or using scene, (for example) a redundancy nude film is added on the basis of redundant block for use Class RAID redundancies.In various embodiments, some blocks of nonvolatile memory are defective and are skipped in write-in, with So that striping occasional have wherein one of nude film be skipped (rather than be written to bad block nonvolatile memory page In) " hole ".In this little embodiment, " in proper order " nonvolatile memory page is pressed by the order of write-in nonvolatile memory page The logical order of determination is in proper order.

With reference to Fig. 5, it shows the diagram of the selected details of the embodiment for the reading unit for including header and data.Various In embodiment, illustrated mapping produces the criterion that variable-size data are positioned in reading unit in Fig. 4.As in Fig. 5 Illustrated, each reading unit (for example, reading unit 500 and 510) has one group of zero or more header 501, And the header is generally write by hardware because variable-size data " being pieced together " (for example, densely accumulation and without waste Space) into one or more reading units.When reading non-volatile storage, generally interpreted by other hardware header with Extract variable-size data.By having respective offsets and length in one of logical block address of matching (or mark) in header Spend to position variable-size data, and data are optionally and/or optionally across some reading units (such as by " data are opened Begin " and " data continue " illustrated variable-size data).

In various embodiments, the header also serves as recycling (for example, garbage collection and/or wear leveling) Partly-comprising logical block address (or equally, map unit address or mark) both realized and find out in reading unit in header Variable-size data provide again it is a kind of to determine when to read the specific one in the reading unit, it is variable big in it Small data be still effectively or be written (by search in the map logical block address and determine it is described mapping whether again referring to The physical address of specific reading unit the other of has still been updated to reference to reading unit) mode.Therefore, header evidence Claim to form " inverse mapping ", because header combine with the physical location of reading unit has the information that is similar in mapping but from thing Reason position correlation is linked to the information of logical block address (or mark).

In certain embodiments, the special hard of data is extracted from reading unit to logic-based block address (or mark) Part is through implementation for random read take with high efficiency manipulation.Specialized hardware dissects the header in one or more reading units to find out There is one of given logical block address (or mark) in the header and then correlation is extracted using corresponding length and skew The variable-size data of connection.However, hardware based solution is expensive (on silicon area and power).For wherein following Sequence can be more important than random performance low side and/or mobile environment, variable-size quick flashing translation layer is implemented to change to reduce silicon Area, saving power simultaneously realize high handling rate in proper order.

In certain embodiments, the variable-size quick flashing translation layer (for example, SRO-VFTL) through reading optimization in proper order will be (close The accumulation of collection ground) data piece nonvolatile memory page together and (or in certain embodiments, are considered as one for write-in purpose single Member nonvolatile memory page group) in, and data in without be used for header any gap-all headers be grouped in it is non- In one part of volatile memory page.In a further embodiment, header is not dynamically used for access data (such as one In a little variable-size quick flashing translation layers), it is only used for recycling and reclaims.Instead, the entry of mapping includes being used to find out The complete information of variable-size (for example, compressed) data in nonvolatile memory page.By header and data separating to non- Cause the reading of the only mixing of reading unit including header and data including header in the different piece of volatile memory page Unit (but as in figure 6, the such reading unit of page only one per nonvolatile memory) and only include the reading unit of data.

Although being configured for reading process amount in proper order with low cost, through the variable-size quick flashing for reading optimization in proper order Translation layer can be by other measurement (such as random read take input/output operations (for example, IOP) per second, random writings per second Input/output operations and sequentially write treating capacity) reasonably well show.However, to for example in each reading unit by mark The removal of the hardware auxiliary for the function that the VFTL formula data of head are pieced together can cause larger burden to control processor.Or, In some embodiments, come that assistance data is pieced together, data are carried using hardware through reading the variable-size quick flashing translation layer of optimization in proper order Take or other operations.

With reference to Fig. 6, it shows the diagram of the embodiment of SRO-VFTL nonvolatile memories page.With reference to Fig. 7, it shows The diagram of another embodiment of SRO-VFTL nonvolatile memories page.Difference between Fig. 6 and Fig. 7 embodiment is from elder generation The continuation data of preceding nonvolatile memory page 640 is before or after header.The expected nonvolatile memory of the present invention The various embodiments and arrangement of data in page.

According to various embodiments, nonvolatile memory page includes one or more of the following：

- header, it is comprising principal mark first 610, optionally and/or optionally redundancy block header 620 is (for example, for redundancy The header added in each piece of first page of block) and zero or more is extra through accumulating header 630.Each quick flashing page tool Have the number of the header continued at least one counts and to data (associated with the header) in nonvolatile memory page Pointer in place of beginning.In certain embodiments, what the header can be for byte alignment, but be respectively only 6 bytes (for example, B).The header including but not limited to data header, period header and can be filled up.Data header utilizes map unit address and length Degree.Skew is implied that, because all data are adjacently accumulated.

- optionally and/or optionally, continuation data from previous nonvolatile memory page (map unit can Become a part for size data) 640.

- to fill nonvolatile memory page one or more map units through accumulation (for example, optionally and/or It is optionally compressed) data 650, nonvolatile memory page it is last optionally and/or optionally follow-up non- Continue in volatile memory page.

- optionally filling up and (being contained in 650) at the end of nonvolatile memory page.In various embodiments, number According to (for example, non-porous) accumulated for byte, but if high compression (for example, excessive header), then may be deposited non-volatile Filled up at the end of reservoir page.For example, in situations below using filling up：(i) it is added to nonvolatile memory page The last remaining unused bytes fewer than the size of header of variable-size data segment are (therefore, it is impossible to which it is another to start to add new header One variable-size data segment), and (ii) is optionally and/or optionally, more than the finger of the header of every nonvolatile memory page (number for the map unit therefore, being stored in nonvolatile memory page is specified number rather than reflected by header fixed number mesh Penetrate the size of data limitation of unit).

In certain embodiments, on the variable-size quick flashing translation layer through reading optimization in proper order recovery and/or follow again Ring (for example, garbage collection) is advantageously enabled to read and/or error correction and/or inspection nonvolatile memory page Each of only Header portion, rather than such as in the variable-size quick flashing translation layer without reading optimization in proper order read and/ Or error correction and/or each reading unit of inspection.If recycling determines the data of rewritable nonvolatile memory page, that It can also read the data and can also carry out error correction to it.In certain embodiments, whole non-volatile memories are read Device page should make one in nonvolatile memory page to the progress error correction of only Header portion to be recycled until making Being defined as of a little data recirculations is stopped.

In various embodiments, per nonvolatile memory, the number of the header of page is deposited through limiting with constraining per non-volatile The number of the reading unit that can be read of reservoir page, so that it is guaranteed that reading all headers from nonvolatile memory.Fig. 6's In embodiment, only read and be enough to accommodate the certain amount reading unit of maximum number header.In Fig. 7 embodiment, read Additional number reading unit is taken with the largest amount (example of the data in view of the ending from previous nonvolatile memory page Such as, continuation data 640).Determine to come from previously to access however, Fig. 7 embodiment makes it possible to slave phase relationship maps entry The number of the reading unit of the end of data of nonvolatile memory page (for example, continuation data 640), because in the end of data The number of byte can be based on associated map entry respective offsets and length and previous nonvolatile memory page in use The number of the byte of family (non-erroneous correcting code) data and determine.In addition, the only header before the end of data is optionally superfluous Remaining block header (existing only in specified nonvolatile memory page, such as the first page in each piece) and principal mark head is (all the time It is present in each nonvolatile memory page).In the embodiment in fig 6, in order to non-volatile memories need not be being accessed twice The ending of data is read in the case of device, it is assumed that there is maximum number header (or reading whole nonvolatile memory page).

In certain embodiments, there are multiple map entrys through reading the variable-size quick flashing translation layer of optimization in proper order and using Single-stage mapping.In other embodiments, multistage-mapping is used through reading the variable-size quick flashing translation layer of optimization in proper order, for example Two-stage maps, and it has the first order mapping (for example, FLM) for pointing to second level mapping (for example, SLM) page, and wherein the second level is reflected Penetrating each of page includes multiple leaf-size class map entrys.In a further embodiment, multistage-mapping has two or more level, Such as three levels.In some embodiments and/or using scene, the use of multistage-mapping makes it possible to the correlation of mapping only (for example, in use) part storage (for example, cache) is in local memory (for example, the core of solid state drive controller The local DRAM of SRAM or main frame on piece) in, so as to reduce the cost for maintaining mapping.For example, if typically using mould Formula has the logical block address space of 1 GB (for example, GB) acted at point at any time, then in order to quickly access Only partly storage mapping be enough access a part for the 1GB parts of the effect in logical block address space, rather than stored In nonvolatile memory.Reference outside the effect partial in logical block address space obtains many from nonvolatile memory Institute's requested part of one or more levels of level mapping, so that the other parts for optionally and/or optionally replacing mapping are deposited The part of storage.

Each of leaf-size class map entry is associated (relative with the address (or mark) of one of multiple map units Should).In one example, logical block address is converted into map unit address, such as by the zero that removes logical block address or Zero above least significant bit (for example, LSB) and/or for alignment purposes and give logical block address addition constant, and mapping It is middle to search map unit address to determine the corresponding entry of the mapping.In another example, it is (or other associated in hash table Data structure) in mark is searched to determine the unique identifier as map unit address.

With reference to Fig. 8, it shows the diagram of the details of the embodiment of various types of headers.In Fig. 8 example, the mark Head is formatted with each six bytes of loading.According to various embodiments, various types of headers are one in the following Or many persons：All with formed objects；Optionally and/or optionally there is different size；Each includes specifying header The respective field of size；It is of different sizes in different non-volatile storage page；And foregoing every any combinations.

According to various embodiments, the header in nonvolatile memory page includes one or more of the following：

- data header 810, it indicates the information associated with variable-size data division.In certain embodiments, with number The data being associated according to header are in the nonvolatile memory page identical nonvolatile memory occurred with the data header Start in page.In further embodiment and/or using scene, if nonvolatile memory page, which only has, is used for data header Remaining space, then all associated datas follow-up nonvolatile memory page in start.

- mapping header, such as second level mapping (for example, SLM) header 820.Second level mapping header is included to indicate (for example mapped for the second level and recycle and/or reclaim) is just storing the first order map index (example of which second level mapping page Such as, FLMI).

Daily record/checkpoint header 820.Daily record/checkpoint header indicate be used for recycle, reclaim, error handling, debugging or The data of other special statuss.

- period header 830 is used as the part reclaimed so that data are associated with correspondence mappings/checking point information.Generally, often There is at least one period header in nonvolatile memory page.

- principal mark first 870 per nonvolatile memory page using once to provide on the mark in nonvolatile memory page The information that where of the number and non-header data of head in nonvolatile memory page starts.Various technologies determine non-header number According to beginning, such as it is illustrated in Fig. 6 and Fig. 7 embodiment.

- at some nonvolatile memories page (the first nonvolatile memory page for example, in each piece of redundant block) Middle use redundancy block header 880.

- other types of header 840, such as filling up header, support the checkpoint header of greater depth.

In certain embodiments, some headers are included to the TYPE field for the multiple subtypes for providing header.Various In embodiment, some headers include LEN (length) field of the length containing the data associated with header.In various embodiments In, not len field or in addition to len field, some headers are also included containing the end to the data associated with header OFFSET (skew) field (not showing) of skew (in nonvolatile memory page).(in certain embodiments, if variable Last one in size data section is across nonvolatile memory page, then OFFSET is in follow-up nonvolatile memory Skew in page or the number of the byte in follow-up nonvolatile memory page.) generally implement in len field or OFFSET fields Only one because in accumulation variable-size data segment in the case of space without waste, in nonvolatile memory page The starting position of each of variable-size data segment and end position are variable big by first in nonvolatile memory page The starting position (for example, after header, such as in the figure 7) of small data segments and the list of LEN or OFFSET fields are implied.

With reference to Fig. 9, it shows the diagram of the selected details of the embodiment of map entry 900.According to various embodiments, mapping Entry include one or more of the following：

- physical non-volatile memory page address,

The skew (for example, OFFSET) of variable-size data items is arrived in-nonvolatile memory page,

The length (for example, LEN__M128) of-variable-size data items, and

- other control information.

In certain embodiments, (for example, by skew) is encoded to length the value for being zero is corresponded to Specify minimum length.For example, if minimum length is 128 bytes, then represent 128 words for 0 LEN_M128 values Section.In other embodiments, it will be compressed to and be less than the data filling for specifying minimum length to the size at least specifying minimum length.

In various embodiments, SRO-VFTL map entrys are more than VFTL map entrys, because SRO-VFTL map entrys Store the full migration and byte length of corresponding data.Therefore, map entry is reduced when being stored in nonvolatile memory Big I is favourable.Typical in use, the map unit in proper order typically at least with a certain granularity and/or more than 1 is averaged Number sequentially reads and write data.Implement also relatively honest and clean using the map entry compressed format of the property in proper order of write-in Valency and the high mapping compression ratio of generation.Entered by the data for making to sequentially write in identical nonvolatile memory page until crossing over Further help the compression of map entry untill nonvolatile memory page boundary.

With reference to Figure 10, it shows the diagram of the selected details of the embodiment of various compressed map entrys.It is described various to reflect Penetrate entry comprising uncompressed 1010, with previous map entry identical nonvolatile memory page address 1020, with Previous map entry identical nonvolatile memory page address and start 1030 at the skew of previous end of data, and have Start with previous map entry identical nonvolatile memory page address, at the skew of previous end of data and have and elder generation Preceding map entry identical length 1040.

In with some of multistage-mapping embodiments, the caches of lower level (such as leaf-size class) mapping page are maintained Device.Cached mapping page be in uncompressed form so that provide by processor (such as main frame or solid state drive controller Control processor) carry out quick access.When mapping page movement is (such as from nonvolatile memory or dynamic random access memory Device (for example, DRAM)) into cache memory when, the mapping page is unpressed.Rushed when from cache memory When washing mapping page (such as due to being changed), compression mapping page is for storage (such as being stored in nonvolatile memory). According to wherein using DRAM with by by some or all of mapping page be stored in dynamic random access memory reduce etc. The various embodiments of time are treated, the mapping page in dynamic random access memory is stored in one or more of following form： Compressed form；Uncompressed form；Optionally, compressed or uncompressed form；And by for accessing dynamic randon access The indirect table of (variable-size) compressed version of the mapping page in memory.

In certain embodiments, host write command main frame write data to it is former up at solid state drive controller Selection of land and/or main frame write-in data are optionally compressed, and it is stored in the way of class first in first out (for example, FIFO) In local (such as on chip) memory.For example, in certain embodiments, main frame is write into data together with firmware data Structure, quick flashing statistics, mapping part (cache memory for for example preserving one or more pages of mapping), from non- Volatile memory reading data (comprising recycling read data), be written to nonvolatile memory data mark Head, software code, firmware code and other use are stored in unified buffer (for example, UBUF in Figure 11 A) together.Each Plant in embodiment, the various local storage criterions for solid-state drive use one or more private memories.

In certain embodiments, before the main frame write-in data of host write command are sent to solid state drive controller The main frame write-in data optionally and/or are optionally compressed at main frame.For example, it is written in data-base recording defeated Enter/output device before the data-base recording is compressed by host data base.

In various embodiments, on each map unit of the data reached from main frame, to the control of solid-state drive Processor (for example, central processing unit CPU in Figure 11 A) notifies one or more of the following：Corresponding map unit Location, the corresponding topical storage address and/or variable-size (example for wherein storing the data associated with corresponding map unit address Such as, it is compressed) corresponding length of each map unit of host data.Control processor is enabled to determine non-volatile memories The total number of available non-erroneous correction decoding byte in each of write-in order and nonvolatile memory page of device page. The total number of available non-erroneous correction decoding byte, control processor in given one in nonvolatile memory page It is enabled to the header amount and data volume for determining to be positioned in the given nonvolatile memory page.For example, at control Manage the header (and following the trail of the number of the byte of header used to date) of the cumulative given nonvolatile memory page of device simultaneously The variable-size data and header of map unit are added to given nonvolatile memory page one at a time, given until described It is full to determine nonvolatile memory page.When given nonvolatile memory page is full, it is added to given non-volatile memories The decline of the data of final one in the map unit of device page is not loaded into given nonvolatile memory page and used Make the end of data part of the subsequent one in nonvolatile memory page (for example, continuation data 640), so as to reduce follow-up non- The total number of available non-erroneous correction decoding byte in volatile memory page, for new header and data.

In certain embodiments, at particular point in time, zero or more nonvolatile memory page is enabled to It is enabled to be filled with recycled data with main frame write-in data filling and zero or more nonvolatile memory page. For example, can fill at least two bands redundant block of series (for example, class FIFO) respectively, a band with " heat " data (for example, Just come from main frame) fill and " cold " data (for example, recycled) filling of another band, and zero or more is non-easily The useful space of the property lost storage page is assigned to each band from buffer.Continue the example, in various embodiments, main frame is write Enter data optionally and/or to be optionally enabled to be directed into the torrid zone or cold belt, and recycled data optionally and/ Or be optionally enabled to be directed into the torrid zone or cold belt.

In certain embodiments, control processor is enabled to a series of corresponding map unit address, local storage Device address and corresponding length are converted into one or more of the following：Be written to nonvolatile memory page and as it is non-easily A series of headers of the Header portion of the property lost storage page；Be written to nonvolatile memory page and as non-volatile memories The first start address and the first length of the part in proper order of the local memory of the user data part of device page, it is described non-volatile The user data part of storage page includes at least a portion of the data of at least one map unit；It is written to follow-up non-easy Lose property storage page and as follow-up nonvolatile memory page user data ending local memory portion in proper order The second start address divided and the second length, the user data ending include a part for the data of a map unit Or be empty；Zero or more for being written to nonvolatile memory page fills up the number of byte, wherein for example, In the case where user data ending is discontented for empty and nonvolatile memory page using filling up byte.Advantageously, control Processor is enabled to simply store the serial corresponding map unit address, corresponding topical by reformatting Device address and corresponding length are converted into the serial header and produced the part (system of composition nonvolatile memory page The header of row, the ending of previous nonvolatile memory page, user data part and any fill up byte) be sent to it is non-easily Peanut direct memory access (DMA) (for example, DMA) order of the property lost memory.

In various embodiments, optionally and/or be selectively enabled main frame write data compression.In one example, Enable compression the header length of host write command.In another example, the logical block address according to host write command (or mark) is selectively enabled compression.In a further example, if the compression of main frame write-in data had not reduced main frame and write Enter the size of data, then optionally disable compression.If not enabling compression, then data are uncompressed is deposited for main frame write-in Storage.According to various embodiments, the entry of mapping by one or more of the following indicate corresponding data be it is compressed or It is uncompressed：Corresponding positions in each entry of mapping；And/or it is stored in the value of the length in each map entry.For example, If map unit is 4KB, then the associated data of the Length Indication map entry in map entry for 4KB is uncompressed , and the Length Indication associated data less than 4KB is compressed.In some embodiments and/or using scene, with main frame The header that optionally and/or optionally compressed version is associated stored of write-in data specifies institute's storage host write-in Whether data are compressed.

In certain embodiments, data recirculation is made by following operation：Select redundant block to be recycled, with write-in Redundant block nonvolatile memory page order come read the page, only handle containing nonvolatile memory page header Reading unit, look in the map data header each header logical block address (or equally, map unit address Or mark) whether still effectively to check data, and if data are still effective, then the appropriate new header of construction and command dma with By the part of data compilation to be recycled for new nonvolatile memory page.Then new nonvolatile memory page is written to Nonvolatile memory.

With reference to Figure 11 A, it shows the diagram of the selected details of the embodiment of solid state drive controller 1100.In some realities Apply in example, solid state drive controller 1100 is enabled to (such as) and implements one by implementing quick flashing transition layer with host collaboration Or multiple quick flashing transition layers or part thereof.In various embodiments, controller 1100 can be embodied as one or more integrated circuits.

Illustrate as illustrated in Figure 11 A, input/output receiver (such as SerDes of solid state drive controller 1100 (for example, serializer/de-serializers)) it is coupled to main frame via external interface 1111.HPI (for example, HIF) is via SerDes Order (for example reading and writing commands) is received, write-in data is received and sends and read data.Via shared memory (for example, OpRAM CPU) is sent commands to.CPU interpretation is described to order and is controlled via shared memory solid The other parts of state driver controller.For example, command dma is delivered to respectively by CPU via shared memory Plant data path transmitting and receiving unit (such as host data path reception segmentation (for example, HDRx) or flash data path hair Penetrate segmentation (for example, FDTx)) and receive response from data path transmitting and receiving unit.

Segmentation (for example, HDRx) is received via host data path to be sent to the write-in data from HPI uniformly Buffer (for example, UBUF).In various embodiments, reception fragmented packets in host data path, which contain, is used to optionally and/or selects Property compress and/or encrypt main frame write data logic.Then connect via the segmentation of flash data outlet openings and generic quick flashing Optionally and/or optionally compressed and/or encrypted main frame is write data from unified buffer by mouthful (for example, GAFI) It is sent to nonvolatile memory.In various embodiments, flash data outlet openings fragmented packets contain to perform encryption and/or The logic of scramble and/or error correction coding.In response to host read command, via generic flash interface from non-volatile memories Device, which reads data and receives segmentation (for example, FDRx) via flash data path, sends said data to unified buffer. In various embodiments, flash data path receives segmentation and incorporates error correcting/decoding and/or decryption and/or descrambling.At it In its embodiment, independent error correction decoder (for example, LDPC-D to implement LDPC code) is enabled to by quick flashing Data path receives " original " data of fragmented storage in unified buffer and operated.Then sent out via host data path Penetrate segmentation (for example, HDTx) and the decoded reading data in unified buffer are sent to HPI.In various embodiments, Host data outlet openings fragmented packets contain to optionally and/or optionally by decoded reading data deciphering and/or decompression The logic of contracting.In certain embodiments, class RAID and soft decision processing unit (for example, RASP) are enabled to produce class RAID superfluous Remaining main frame write-in data and/or system data and/or the execution soft decision being stored in other protection in nonvolatile memory Processing is operable for being used together with LDPC-D.

According to various embodiments, solid state drive controller is enabled to not implement one or more quick flashing transition layers, implementation Some quick flashing transition layers in one or more quick flashing transition layers, whole quick flashing transition layers implement one or more quick flashing transition layers Part.In one example, the more senior demapping section of quick flashing transition layer is performed on main frame, and in solid state drive controller Perform the lower level demapping section of quick flashing transition layer.In another example, solid state drive controller is by abstract physical location Location (such as reading unit address and span) is sent to main frame and receives abstract physical location address (such as reading unit from main frame Address and span), and logical block address (or mark) is mapped to abstract physical location address by main frame.Solid state drive controller It is enabled to identifier (such as logic via the specific data associated with abstract physical location address being stored in header Block address (or mark)) and position the specific data.In a further example, logical block address (or mark) reflecting at main frame Penetrate and produce nonvolatile memory page address, the skew in nonvolatile memory page and byte length.Solid-state drive is controlled Device is enabled to determine to treat that several reading units accessed in the nonvolatile memory are non-volatile to retrieve one or more Specified data in storage page.Advantageously, in one or more in instances, wrong school is maintained by solid state drive controller The details (for example, number or the size of reading unit of the bytes of user data of every nonvolatile memory page) just decoded, from And reduce the added burden on main frame.

With reference to Figure 11 B, the diagram of the selected details of the embodiment of its display data path segments.Data path segmentation 1190 The host data path that Figure 11 A can be illustrated receives segmentation or the segmentation of flash data outlet openings.Data path segmentation 1190 Including reading sequencer 1130, write-in sequencer 1140 and zero or more data path unit (for example, DPU).Figure 11 B Illustrate the example with two data path units 1150-1 and 1150-2.

Read sequencer 1130 and be coupled to OpRAM (referring to Figure 11 A) with the control for the data for receiving specified to be read/access Information.For example, described information can be the address and/or length unified in buffer or be connect to HPI or generic quick flashing Mouthful order and may specify the order that will mix with data.Read sequencer 1130 be additionally coupled to reader 1110 with (such as) from UBUF, HPI or generic flash interface read/access data.Reading sequencer 1130 is enabled to basis and connect from OpRAM The request of receipts and by the cross-current for reading data and order be sent to zero or more data path unit 1150-1 and 1150-2 and write-in sequencer 1140.

Write-in sequencer 1140 is enabled to receive the cross-current of the data sent by reading sequencer 1130 and order.Write Enter sequencer 1140 to be coupled to write device 1120 to write data into (such as) to UBUF, HPI or generic flash interface. The data are (such as by specifying address and/or length according to the order in the data flow that is received by write-in sequencer 1140 Order) and write.Write-in sequencer 1140 is additionally coupled to OpRAM (referring to Figure 11 A) to send pass according to received command In the status information for the data having been written into.For example, status information is written in OpRAM to indicate the finger of write-in data flow The ending of fixed part (for example, a 4KB map unit).

Data path unit 1150-1 and 1150-2 are enabled in data in reading sequencer 1130 and write-in sequencer Data are converted when being advanced between 1140.The order produced by reading sequencer 1130 in data flow is optionally and/or selectivity Ground is intended to be received by one or more of data path unit 1150-1 and 1150-2 or write-in sequencer 1140.Data path list First 1150-1 and 1150-2 example are included：

- ciphering unit, it receives the order for the encryption salt (initialization vector) for including being ready to use in encryption and according to encryption salt And by the data encryption continued.In a further embodiment, order also includes the specification of encryption key.

- decryption unit, it receives the order for the encryption salt (initialization vector) for including being ready to use in decryption and according to encryption salt And by the data deciphering continued.In a further embodiment, order also includes the specification of decruption key.

- compression unit, its order and compression for receiving the beginning for indicating compression unit (for example, map unit) border continue Data.In various embodiments, order is also included by the data volume of the unit of boil down to one, compression type, for compression most Big one or more of run time and other compression controls.

- decompression unit, it receives the order for the beginning for indicating compression unit border and by the data decompression continued. In various embodiments, order also includes that the data volume for being condensed to a unit, the expection size of decompressed data, decompression will be decompressed Type, the maximum run time for decompression and other decompressions control one or more of.

- CRC (for example, CRC) unit, it, which is received, includes being ready to use in the encryption for calculating cyclic redundancy check value Salt (initialization vector) order and according to encryption salt and calculate the cyclic redundancy check value in the data continued.Further real Apply in example, order optionally and/or optionally enables cyclic-redundancy-check unit previously will calculate cyclic redundancy school Test value and be attached to the previous received data covered by cyclic redundancy check value.

- error correction coding and/or decoding unit, its reception include the order of code check and according to the wrong school of the code check Code and encode and/or decode the data continued.In a further embodiment, order optionally and/or optionally includes volume Outer control, such as soft decision processing information, maximum number iteration to be used and other encoders and/or decoder control letter Breath.

In example operation, in response to receiving writing commands from main frame, the reading of segmentation is received for host data path The command list (CLIST) of sequencer is built by CPU, and according to the command list (CLIST), host data path receives segmentation warp Enable that the write-in data of writing commands are transmitted into unified buffer from main frame via HPI.Host data path is received Data path unit in segmentation is enabled to the compression write-in number before (compressed) write-in data are written to unified buffer According to.Multiple (compressed) map units are enabled to closely be piled up in unified buffer and the space without waste.By writing Enter to each of OpRAM (the write-in sequencer that segmentation is received via host data path) (compressed) map unit The status information of position and size and notify CPU.CPU is enabled to the construction according to status information The header of one nonvolatile memory page of header and determination filling and the amount of (compressed) map unit.CPU is entered One step is enabled to build the command list (CLIST) for being used for the reading sequencer that flash data outlet openings are segmented with by header and data Nonvolatile memory page be transmitted into nonvolatile memory.Data path unit warp in the segmentation of flash data outlet openings Enable with the header and data encoding by nonvolatile memory is just sent to, so that the volume for protection being decoded for error correction Outer byte is added to each of multiple reading units.Received in the write-in sequencer being segmented from flash data outlet openings After the state for completing NVM page write-in, at once recoverable (can reuse) uniformly in buffer by (compressed) map unit Used space.

In another example operation, in response to receiving reading order from main frame, segmentation is received for flash data path The command list (CLIST) of sequencer is read by CPU construction, and according to the command list (CLIST), flash data path, which is received, to be divided Section is enabled to that one or more reading units read from nonvolatile memory are received into unification via generic flash interface Buffer.In certain embodiments, the data path unit that flash data path is received in segmentation is enabled to use on every The data solution that nonvolatile memory will be just sent to for the extra byte that error correction decoding is protected of one reading unit Code.In other embodiments, error correction is segmented (for example, LDPC-D in Figure 11 A) via independent data path and occurred.It is logical Cross from flash data path and receive the write-in sequencer of segmentation or writing for (in other embodiments) LDPC-D data paths segmentation Enter the reception state of sequencer and the reception of (calibrated) data in unified buffer is notified into CPU.Centre Reason unit, which is further enabled to build, is used for command list (CLIST) that host data outlet openings are segmented with will be through via HPI At least a portion of correction data is transmitted into main frame from unified buffer.Data path list in the segmentation of host data outlet openings Member is enabled to before corrected data is transmitted into main frame decompress corrected data.Divide from host data outlet openings The write-in sequencer of section has been received after the successfully state of transmitting corrected data, at once recoverable (can reuse) system The space as used in corrected data in one buffer.

The diagram of the selected details of the various embodiments of display systems with reference to Figure 11 C, its embodiments in accordance with the present invention. The embodiment generally comprises one or more examples of Figure 11 A solid state drive controller 1100.Several solid-state drives 1101a to 1101n, which is generally comprised, to be coupled to nonvolatile memory 1199a via device interface 1190a to 1190n respectively and arrives 1199n solid state drive controller 1100a to 1100n.The figure illustrates various types of other embodiment：It is directly coupled to The single solid-state drive of main frame 1102；Each it is directly coupled to main frame via respective external interface 1111a to 1111n respectively 1102 multiple solid-state drives；And one or more solid-states driving of main frame 1102 is indirectly coupled to via various interconnection elements Device.

It is used as the example embodiment for the single solid-state drive for being directly coupled to main frame, one of solid-state drive 1101a Example is directly coupled to main frame 1102 (for example, omitting, bypassing or through exchanger/group structure/centre via external interface 1111a Controller 1103).Implement as the example for multiple solid-state drives that main frame is each directly coupled to via respective external interface , each of solid-state drive 1101a to 1101n multiple examples are respectively via outer interface 1111a to 1111n phase Example is answered to be directly coupled to main frame 1102 (for example, omit, bypass or through exchanger/group structure/middle controller 1103).As The example embodiment of one or more solid-state drives of main frame, solid-state drive 1101 are indirectly coupled to via various interconnection elements Each of one or more examples be indirectly coupled to main frame 1102 respectively.Each INDIRECT COUPLING is via being coupled to exchange External interface 1111a to the 1111n of device/group structure/middle controller 1103 and the intermediary interface 1104 for being coupled to main frame 1102 Respective instance.

Comprising exchanger/embodiment of group structure/middle controller 1103 in some embodiments comprising being connect via memory The coupling of mouth 1180 and the card memory 1112C that can be accessed by solid-state drive 1101a to 1101n and/or by main frame 102.Each Plant in embodiment, one or more solid-state drives 1101a to 1101n, exchanger/group structure/middle controller 1103 and/or card are deposited Reservoir 1112C is contained in physics and can recognize that on module, card or pluggable element (for example, input/output cards 1116).In some realities Apply in example, solid-state drive 1101a to 1101n (or its version) corresponds to the initiator for being coupled to operation for main frame 1102 Serial attached SCSI (for example, SAS) drivers or Serial Advanced Technology Attachment (for example, SATA) driver.

Main frame 1102 be enabled to perform host software 1115 various elements, such as operating system (for example, OS) 1105, The various combinations of driver 1107, application program 1109 and many device management softwares 1114.Dotted arrow 1107D represents main frame Two-way communication between software and input/output device is (for example, via driver 1107 and application program 1109 (via drive Dynamic program 1107 or directly as (for example, PCIe) virtual function (for example, VF)) by data from any in operating system 1105 One or more is sent to one or more of solid-state drive 1101a to 1101n example and by data from solid-state drive One or more of 1101a to 1101n example is sent to any one or more in operating system 1105).

In some embodiments and/or using scene, host software 1115 includes being driven with solid-state in quick flashing transition layer Some quick flashing transition layers, whole quick flashing transition layers or part that device 1101a to 1101n is used together.In one example, various In embodiment, driver 1107 implements be used together with solid-state drive 1101a to 1101n at least the one of quick flashing transition layer Part.In another example, in various embodiments, many device management softwares 1114 implement being driven with solid-state for quick flashing transition layer At least a portion that device 1101a to 1101n is used together.

Operating system 1105 includes the driver for being used for interfacing with solid-state drive 1101a to 1101n (by driver 1107 conceptually illustrate) and/or it is enabled and operated with the driver.Windows various version (examples Such as, 95,98, ME, NT, XP, 2000, Server, Vista, 7 and 8), Linux various versions are (for example, Red Hat, Debian And Ubuntu) and MacOS various versions (for example, 8,9 and X) be operating system 1105 example.In various embodiments, drive Dynamic program is can be with standard interface and/or agreement (such as SATA), advanced host controller interface (for example, AHCI) or NVM Standard and/or generic driver (sometimes referred to as " tightening coated " or " pre-installation ") or appoint that Express is operated Selection of land customization and/or supplier it is distinctive enable to using solid-state drive 1101a to 1101n it is distinctive order and/ Or quick flashing transition layer.Some drivers and/or driver have direct mode operation (to be sometimes referred to as via optimal N AND accesses ONA) or directly NAND accesses (sometimes referred to as DNA) technology enables application-level program (such as application program 1109) to order Order be directly delivered to solid-state drive 1101a to 1101n so that custom application can in addition with generic driver It is used together the distinctive orders of solid-state drive 1101a to 1101n and/or quick flashing transition layer.ONA technologies are included in the following One or more：The use of non-standard modifier (prompting)；The use of supplier's uniqueness order；The biography of non-standard statistics Pass, for example, used according to the actual nonvolatile memory of compressed capability；The use of the peculiar agreement of quick flashing transition layer, for example, transmit Reading unit address and span or such as transmission nonvolatile memory page address, skew and byte length；And other technologies. DNA technique includes one or more of the following：There is provided to nonvolatile memory without mapping read, write-in and/or Wipe the non-standard command of access or the use of supplier's uniqueness order；It will such as be entered originally by bypassing input/output device The formatting of capable data provides the unique order of non-standard or supplier being more directly accessed to nonvolatile memory Use；And other technologies.The example of driver is not support ONA or DNA driver, enable ONA driver, open With DNA driver and enable ONA/DNA driver.Other examples of driver are supplier's offer, supplier Exploitation and/or the enhanced driver of supplier and client are provided, client is developed and/or the enhanced driving journey of client Sequence.

The example of application-level program is not support ONA or DNA application program, enable ONA application program, enable DNA application program and the application program for enabling ONA/DNA.Dotted arrow 1109D represents application program with being used for application program (for example, enable ONA application program and for example used in the case of without application program operating system as middleware with Solid-state drive communication the driver for enabling ONA) input/output device (for example, bypass or warp via driver By the bypass of virtual function) between two-way communication.Dotted arrow 1109V represent application program with for application program (for example, Enable DNA application program and operating system or driver are for example used in the case of without application program as centre What part communicated with solid-state drive enables DNA driver) input/output device (for example, via the side of virtual function Road) between two-way communication.

In certain embodiments, nonvolatile memory 1199a to 1199n one or more parts are used for firmware storage dress Put (for example, firmware 1106a to 1106n).Firmware storage comprising one or more firmware images (or part thereof).Citing comes Say, firmware image has consolidating performed by (for example, as solid state drive controller 1100a to 1100n CPU) One or more images of part.For another example, firmware image has (for example) to be performed by CPU in firmware One or more images of constant, parameter value and non-volatile memory device information that period refers to.For example, the figure of firmware As corresponding to current firmware image and zero or more previous (being updated relative to firmware) firmware image.In various embodiments In, firmware provides generic, standard, ONA and/or DNA operator schemes and operated together with one or more quick flashing transition layers.One In a little embodiments, one or more of firmware operation pattern is enabled (for example, via optionally being transmitted and/or carried by driver The key of confession or various software engineerings carry out " unblock " one or more application programming interfaces (for example, API)).In further embodiment In, different persons and/or the different persons in quick flashing transition layer that the different persons in firmware image are used in operator scheme.

In certain embodiments, main frame 1102 includes the mapping 1108 as the different hardware resource for implementing mapping.At it In its embodiment, demapping section or fully drive via 1108 and/or mainframe memory 1112H of mapping and/or via solid-state Move the mapping 1141 in device controller 1100 and/or implement via card memory 1112C.Mapping 1108, mainframe memory The example of mapping 1141 and card memory 1112C in 1112H, solid state drive controller 1100 be (for example) via DRAM, SRAM and/or quick flashing or other non-volatile memory devices and one or more volatibility and/or non-volatile memories implemented Device element.Other examples of mainframe memory are system storage, main frame main storage, host cache, main frame Memory and input/output device, which can be accessed, can access memory.In some embodiments and/or use scene (such as with defeated Enter/output card 1116 and use Figure 11 C optional card memory 1112C as storage device (at least a portion of mapping) Some embodiments) in, the mapping in one or more input/output devices and/or the access of main frame 1102 card memory 1112C.

In various embodiments, one or more of example of main frame 1102 and/or solid-state drive 1101 is enabled to Access mapping 1108, mainframe memory 1112H, card memory 1112C and/or mapping 1141 can be used for patrolling to preserve and retrieve Volume block address (or other specificators, such as, mark) is converted to one or more with input/output device nonvolatile memory Partly (such as element of one or more of nonvolatile memory 1199a to 1199n example) is the non-volatile of target The whole or any part of the map information of memory location (such as block and/or page address and/or reading unit address).Concept Property, single mapping may be present, and according to various embodiments, the control and/or storage of mapping and/or using in main frame 1102 One or more and/or by solid state drive controller 1100a to 1100n provide.

In some embodiments for lacking exchanger/group structure/middle controller 1103, solid-state drive 1101a to 1101n Main frame 1102 is directly coupled to via external interface 1111a to 1111n.In various embodiments, solid state drive controller 1100a to 1100n via other controllers (such as RAID controller or i/o controller) one or more intermediate levels It is coupled to main frame 1102.In certain embodiments, solid-state drive 1101a to 1101n (or its version) drives corresponding to SAS Dynamic device or SATA drive, and exchanger/group structure/middle controller 1103 corresponds to expander, the expander is coupled to again Initiator, or alternatively, exchanger/group structure/middle controller 1103 corresponds to bridger, and the bridger is between expander Connect and be coupled to initiator.In certain embodiments, exchanger/group structure/middle controller 1103 is exchanged comprising one or more PCIe Device and/or group structure.

In various embodiments, for example wherein main frame 1102 as calculating main frame (for example, computer, workstation computer, Server computer, storage server, personal computer, laptop computer, mobile computer, net book and/or flat board Computer) embodiment in some embodiments, calculating main frame is optionally enabled to and one or more local and/or long-range clothes Device (for example, optional server 1118) communication be engaged in (for example, via optional input/output and storage device/resource 1117 and optionally LAN/Wide Area Network (for example, LAN/WAN) 1119).For example, the communication is realized in solid-state drive element The local and/or remote access of any one or more, manage and/or use.In certain embodiments, it is described communication fully or Partly via Ethernet.In certain embodiments, the communication is completely or partially via optical-fibre channel.Implement various In example, LAN/Wide Area Network 1119 is represented in one or more LANs and/or Wide Area Network, such as server farm Network, couple server farm network, Metropolitan Area Network (MAN) and internet in any one or more.

In various embodiments, solid state drive controller and/or calculating main frame non-volatile memory controller are combined One or more nonvolatile memories are embodied as non-volatile storage components together, and such as USB (for example, USB) is deposited Store up component, general flash memory devices (for example, UTS) storage assembly, Compact Flash (for example, CF) storage assembly, multimedia Block (for example, MMC) storage assembly, secure digital (for example, SD) storage assembly, memory stick storage assembly and the storage of xD picture cards Component.

In various embodiments, the whole of solid state drive controller (or calculating main frame non-volatile memory controller) Or any part or its function are implemented on the controller by coupled main frame (for example, Figure 11 C main frame 1102). In various embodiments, the whole or any part of solid state drive controller (or calculating main frame non-volatile memory controller) Or its function is (for example, driver software or solid-state drive via hardware (for example, logic circuit), software and/or firmware Control firmware) or its any combinations and implement.

With reference to Figure 12, it shows the flow chart 1200 for writing data into nonvolatile memory.In step 1202, mistake Journey starts, and in step 1206, makes on will (for example or other unique identifiers object identity or patrol with multiple marks Volume block address) in the associated data write-in (storage) of specific one to nonvolatile memory determination.For example, institute Determination is stated to be made by one or more of application program, operating system, management program or any other software or firmware module. In some embodiments, write-in data are variable-size (for example, it may be possible to changing with each write operation).In other embodiments In, write-in data are the unit of several fixed sizes, such as several SATA sectors.

In step 1210, writing commands and associated (possible variable-size) write-in data are received.In one example, Application program is called writing commands and write-in data (such as via the pointer for pointing to data) being sent to driving using system Program.In another example, writing commands are sent collectively to solid state drive controller so that solid by main frame together with information State driver controller can retrieve associated write-in data.For example, writing commands include SATA Native Command Queue (examples Such as, NCQ) label, and Native Command Queue label is for obtaining associated write-in data.

In step 1214, optionally and/or optionally compress or otherwise reduce (possible variable-size) Write the size of data.Even if associated write-in data have been variable-sizes, compression can may also further reduce phase The size of association write-in data.In certain embodiments, (possible variable-size, may compressed) write-in data optionally and/ Or be optionally encrypted.

In step 1218, it is determined that nonvolatile memory for writing data it is next do not write physical location ( In physical address space).In one example, determine next physical location that do not write close to being bordering on be previously written variable big Small data (does not waste the space in nonvolatile memory).In another example, determine that next physical location that do not write exists With starting in the variable-size data identical reading unit that is previously written.In certain embodiments, determine next not write It is according to band specified in writing commands to enter physical location.

In step 1222, (possible variable-size, possibility are compressed) write-in data storage is incited somebody to action in nonvolatile memory In next do not write physical locations determined.In certain embodiments, hardware cell is by (possible variable-size, Ke Nengjing Compression) write-in data piece together nonvolatile memory page image (for example, be written to nonvolatile memory page buffering A part for device) in.

In step 1226, the header of the identifier including writing data is stored in and (possible variable-size, Ke Nengjing Compression) write at least a portion identical nonvolatile memory page of data.For example, header is stored in such as scheming At least a portion identical nonvolatile memory page of (possible variable-size, possibility are compressed) write-in data in 6, and/ Or be stored in header and at least a portion identical such as (possible variable-size, possibility are compressed) write-in data in Fig. 5 Reading unit.According to various embodiments, identifier is one or more of the following：Specific markers phase with writing data Together；Write the function of the specific markers of data；Via the table identifier associated with the specific markers for writing data；It is stored in The unique identifier among all data in nonvolatile memory；And foregoing every any combinations.

According to various embodiments, the storage of (possible variable-size, possibility are compressed) write-in data and/or header is betided In step 1222 and/or 1226 and/or be postponed, until accumulation header and data (such as from multiple write operations) it is non-easily Untill the property lost storage page.In certain embodiments, wrong school is performed to a part for nonvolatile memory as storage Positive coding.In a further embodiment, several error corrections decoding byte is attached to each reading list by error correction coding The User Part of member is to form the reading unit being such as stored in nonvolatile memory.In still further embodiment, in mistake By mistake scramble is performed before correction coding.

In step 1230, return determines next instruction for not writing physical location.In one example, determine next Not writing the instruction of physical location includes being used to store (possible variable-size, possibility in reading unit address, such as reading unit It is compressed) write-in data one address.Continue the example, in certain embodiments, determine next not write thing The instruction of reason position further comprise by (possible variable-size, may compressed) write-in data across several read lists Member, for example, must be read to retrieve all and no more than (possible variable-size, may compressed) if writing data Dry reading unit.One or more of several described reading units optionally and/or optionally contain with mark The associated data of other data, but each of several reading units containing (possible variable-size, may be through pressing Contracting) write-in data at least some write-in data.In another example, next instruction bag for not writing physical location is determined Include the address of nonvolatile memory page and/or write-in data are at least for storing (possible variable-size, possibility are compressed) Skew in the nonvolatile memory page of a part.Continue another example, in certain embodiments, determine it is next not The instruction of write-in physical location further comprises the length in the byte of (possible variable-size, possibility are compressed) write-in data. Another example is continued to, in still further embodiment, (possible variable-size, possibility are compressed) write-in data are horizontal Across more than one nonvolatile memory page (for example, starting in the first nonvolatile memory page and proceeding to one or more In follow-up nonvolatile memory page).For example, when the first nonvolatile memory page in skew at and after residue When amount of user data is less than the length in the byte of (possible variable-size, may compressed) write-in data, (may it is variable greatly It is small, possible compressed) data are write across more than one nonvolatile memory page.

In step 1234, maintenance makes specific markers are associated with determined next instruction for not writing physical location to reflect Penetrate.For example, maintain the mapping that the data associated with specific markers are retrieved by subsequent read operations.

In step 1238, statistics is maintained according to writing commands.For example, write associated with specific markers Data discharge using the particular space amount in the wherein redundant block of write-in data and optionally and/or optionally and wherein store Particular space amount in the redundant block of the older version of the data associated with specific markers.Statistics follows the trail of each redundant block In use amount of space (or equally, in certain embodiments, free space amount).At step 1290, the process knot Beam.

In certain embodiments, locking (such as semaphore) is used to prevent the mapping during at least a portion of process 1200 At least one of access penetrated.For example, in certain embodiments, from step 1210 to 1234 locking and specific markers phase The entry of the mapping of association is to prevent other accesses to entry when just updating entry.

With reference to Figure 13, it shows the flow chart 1300 that data are read from nonvolatile memory.At step 1302, process Start, and at step 1306, make on reading (or the other unique knowledges of (retrieval) and multiple marks from nonvolatile memory Do not accord with, such as object identifier or logical block address) in the associated data of specific one determination.For example, it is described It is determined that being made by one or more of application program, operating system, management program or any other software or firmware module.One In a little embodiments, data are variable-size (for example, it may be possible to changing with each read operation).In other embodiments, number According to being several fixed size units, such as several SATA sectors.

In step 1310, specific markers are searched in the map to determine institute's storage version of the data associated with marking The instruction of physical location in the nonvolatile memory.According to various embodiments, Map Searching is by initiating read operation Software module is performed by another software module that the software module by initiation read operation is called.For example, apply Program initiates the driver layer on read operation, and main frame or the firmware layer on solid state drive controller performs mapping and looked into Look for.

In step 1314, the reading order of the instruction with the physical location in nonvolatile memory is received.One In example, after the driver layer executed Map Searching on main frame, driver layer is by reading order and non-volatile The instruction of physical location in memory is sent to solid state drive controller.In another example, in solid-state drive control After first processor executed Map Searching in device, first processor is by the thing in reading order and nonvolatile memory The instruction of reason position is sent to control to the second processor in the solid state drive controller of the access of nonvolatile memory.

In step 1318, nonvolatile memory is determined using the instruction of the physical location in nonvolatile memory In containing the data associated with specific markers institute's storage version reading unit position and number.In one example, thing Managing the instruction of position includes reading unit address, such as institute's storage version of the data associated with specific markers for storage The address of one in one or more reading units.Continue the example, in certain embodiments, the instruction of physical location is entered One step includes the number of one or more reading units, for example, must be read to retrieve the number associated with specific markers According to whole and no more than institute's storage version reading unit number.(one or more of one or more reading units are optionally Ground and/or optionally contain the data associated with other data in mark, it is but each in one or more reading units Person contains at least some versions in institute's storage version of the data associated with specific markers.) in another example, physical bit The instruction put includes the address of nonvolatile memory page and/or for storing being stored for the data associated with specific markers Skew at least one of nonvolatile memory page of version.Continue another example, in certain embodiments, thing The instruction of reason position further comprises the length in the byte of institute's storage version of the data associated with specific markers.Further Continue another example, in still further embodiment, institute's storage version of data associated with specific markers is across one Individual above nonvolatile memory page in the first nonvolatile memory page (for example, start and to proceed to one or more follow-up In nonvolatile memory page).For example, when the first nonvolatile memory page in skew at and after remaining users It is associated with specific markers when data volume is less than the length in the byte of institute's storage version of the data associated with specific markers Data institute's storage version across more than one nonvolatile memory page.Another example is continued to, according to The number and/or size and according to the institute of the data associated with specific markers of reading unit in one nonvolatile memory page Skew and length in the byte of storage version, determine one or more of the reading unit in the first nonvolatile memory page In one and the first nonvolatile memory page in reading unit number.If the data associated with specific markers Institute's storage version across more than one nonvolatile memory page, then on nonvolatile memory page in one or more Follow-up nonvolatile memory page is using similar procedure to determine to contain and specific markers phase in follow-up nonvolatile memory page At least one of extra reading unit of institute's storage version of the data of association.

In step 1322, read from nonvolatile memory and determine reading unit.In certain embodiments, to reading Unit perform error correcting/decoding with correct in nonvolatile memory is stored in and/or be sent to nonvolatile memory or Any mistake occurred during being transmitted from nonvolatile memory.In a further embodiment, error correcting/decoding it After perform descrambling.By the error correction of determined reading unit is encoded, it is thus determined that will be read from nonvolatile memory Several byte packets containing in each of user data and reading unit in reading unit error correction decode byte Both.In certain embodiments, the number (such as) of the error correction decoding byte in each of reading unit is in solid-state Dynamically change because of the loss of nonvolatile memory under the control of driver controller.In various embodiments and/or use In scene, for example when at least one of determined reading unit contain with mark the other of associated data at least During a part, determine that the total number of the byte of the user data in reading unit exceedes the data associated with specific markers Length in the byte of institute's storage version.

In step 1326, institute's storage version of the data associated with specific markers is extracted from determined reading unit. In certain embodiments, extraction is according to the identifier for possessing reading order.According to various embodiments, identifier is the following One or more of：It is identical with the specific markers of data；The function of the specific markers of data；Via a table and the specific mark of data The associated identifier of note；It is stored in the unique identifier among all data in nonvolatile memory；And foregoing teachings Any combinations.In one example, reading unit includes one or more headers, as illustrated in figure 5, and uses identifier To determine the matching one in header, then in determined reading unit and specific markers are positioned using the matching header Institute's storage version of associated data.In another example, the instruction of physical location includes specifying and determined in reading unit The data associated with specific markers institute's storage version position information.According to various embodiments, with specific markers phase Institute's storage version of the data of association is variable-size.For example, the data associated with specific markers are before storing Compressed, and/or the data itself associated with specific markers are variable-sizes.

In step 1330, institute's storage version of the data associated with specific markers optionally and/or is optionally passed through Decryption and/or optionally and/or optionally decompressed to produce the data associated with specific markers.

In step 1334, the data associated with specific markers are returned in response to read operation.

In step 1338, statistics is maintained according to reading order.In one example, reading order access certain number Mesh non-volatile memory block determination reading unit to retrieve, and the reading for maintaining to count per non-volatile memory block is dry Disturb the statistics of the number of event.In another example, reading order access given number non-volatile memory block with Retrieval determines reading unit, if determining, the error correction correction of reading unit is determined in each of reading unit Do the maximum number corrected in any reading unit in each of a corresponding mistake, and maintenance non-volatile memory block The statistics of mesh mistake.At step 1390, the process terminates.

Generally for read not across multiple nonvolatile memories page single map unit data, stay in non-volatile Property storage page in access the data to obtain map unit institute's storage version reading unit number be less than it is non-volatile All reading units in storage page.Further, since institute's storage version of the data of map unit is variable-size, therefore With reference to the first logical block address (or mark) reading accessed in nonvolatile memory page is stayed in for the first reading order The number of unit is different from staying in non-volatile memories for the second reading order with reference to the second logical block address (or mark) The number of the reading unit accessed in device page, the second logical block address is different from the first logical block address.In certain embodiments, The number reading unit for staying in nonvolatile memory page access is only read from nonvolatile memory page.Namely Say, from nonvolatile memory only read reading unit in the data containing map unit institute's storage version a part reading The institute's storage version for the data for taking unit to access and retrieve map unit.

With reference to Figure 14, its displaying makes the flow chart that data are recycled in the nonvolatile memory.At step 1402, mistake Journey starts, and in step 1406, makes the determination in the region recycled on the band of nonvolatile memory.According to various realities Apply example and/or use scene, the region is one or more of the following：Redundant block；One or more non-volatile memories Device block；The part that free space and/or used dimensional dtatistical figures are maintained in it of nonvolatile memory；It is non-volatile The part that wear leveling statistics is maintained in it of memory；And foregoing every any combinations.According to various embodiments And/or scene is used, recycling is performed to one or more of the following：Garbage collection in nonvolatile memory (total free space)；The wear leveling of nonvolatile memory is (to keep the block of nonvolatile memory in corresponding program/erase It is relatively equal in counting)；And the procedural error relevant with nonvolatile memory and/or exception, such as program mal, excessively reading Take interference and/or excess error rate.In a further embodiment, globally held by main frame (such as across multiple solid-state drives) Row recycling.

In step 1410, one or more nonvolatile memories page is read from the region of nonvolatile memory.One In a little embodiments, error correction is integrally carried out to nonvolatile memory page.To all readings in nonvolatile memory page Unit is taken to carry out error correction.In other embodiments, the determination only first to nonvolatile memory page contains header (for example It is illustrated in Fig. 6) a part carry out error correction, and if it is determined that (for example, step 1426) nonvolatile memory Page contains the data of recycling in need, then the other parts to nonvolatile memory page carry out error correction.

In step 1414, header is extracted from nonvolatile memory page.In one example, illustrated in such as Fig. 5 In the embodiment of explanation, header is extracted from each reading unit in each of nonvolatile memory page.In another reality In example, in such as Fig. 6 in embodiment illustrated, from a part (example of each of nonvolatile memory page Such as one or more reading units first in each of nonvolatile memory page) extract header.

In step 1418, dissect the header from nonvolatile memory page extraction to determine in nonvolatile memory page The identifier for starting associated data with (such as).

In step 1422, identifier is searched in the map to determine that the data associated with identifier are deposited non-volatile The corresponding instruction of physical location in reservoir.In certain embodiments, identifier when writing nonvolatile memory with being made The respective markers of data are identical.In other embodiments, by identifier and other information, (for example solid-state drive is recognized Symbol) combine the mark searched in the map to be formed.In still other embodiments, maintenance make identifier associated with mark and/ Or make the associated mapping of instruction of the identifier with being associated with the physical location of the data of identifier in the nonvolatile memory.

To be still the related to identifier of current (in the nonvolatile memory page just recycled) in step 1426 Any data of connection are written to the new physical locations in nonvolatile memory.For example, by the number associated with identifier Corresponding reading unit address is converted to according to the corresponding instruction of physical location in the nonvolatile memory, and if corresponding read Element address is in the nonvolatile memory page just recycled, then the nonvolatile memory page just recycled contains and knowledge The latest edition of associated data is not accorded with.In various embodiments, held similar to the step 1218 to 1230 of process 1200 It is about to the new physical locations that still for current data are written in nonvolatile memory associated with identifier.In various realities Apply in example, if compression and/or encryption are still current data, then come in compressed and/or encrypted form " as it is " Rewrite still is current data.In certain embodiments, will be still current data from the nonvolatile memory just recycled New nonvolatile memory page that page is moved in solid state drive controller (and main frame still will not be sent to for current data To make still to be current data recirculation).In other embodiments, recycling includes still being that current data are sent to master Machine and similar to process 1200 and rewrite still be current data.In a further embodiment, it is complete across multiple solid-state drives It is local to perform recycling, and for recycling purpose, it is still current for being previously stored on one of solid-state drive Rewriting data is the other of to solid-state drive.

In step 1430, the instruction of the new physical locations for any data that more new mappings have been recycled with reflecting.

In step 1434, whether make will handle the determination of more plurality of nonvolatile memories page in the zone.If It is, then process proceeds to step 1410 to continue to make other nonvolatile memory pages to recycle.

In step 1438, statistics is maintained according to the reading and write-in of nonvolatile memory during process recycling Data.In one example, reading non-volatile storage access given number non-volatile memory block is non-volatile to retrieve Property storage page, and maintain count per non-volatile memory block reading interference event number statistics.Another In example, reading non-volatile storage accesses given number non-volatile memory block to retrieve nonvolatile memory In page, the reading unit through error correcting/decoding of the error correction correction nonvolatile memory page of nonvolatile memory page Each in several corresponding mistakes, and maintain in any reading unit in each of non-volatile memory block The statistics of the maximum number mistake corrected.In a further example, data are made by writing nonvolatile memory Particular space amount in the recycled redundant block for wherein writing recycled data, and optionally and/or optionally release Put the particular space amount in the redundant block just recycled.Statistics, which is followed the trail of in each redundant block, uses amount of space (or to wait Effect ground, in certain embodiments, free space amount).In certain embodiments, when using space in the region just recycled When amount goes to zero, it is still current (not having override) data recirculation, and process 1400 can no longer to make in the region Completed before all nonvolatile memories page in reading the region just recycled.At step 1490, the process knot Beam.

In certain embodiments, locking (such as semaphore) is used to prevent the mapping during at least a portion of process 1400 At least one of access penetrated.For example, in certain embodiments, from step 1422 to 1430 locking with having in identifier There is the entry of the associated mapping of one of current data to prevent other accesses when just updating entry to entry.

According to various embodiments, the region to be recycled of Selection of chiller nonvolatile memory；Solid-state drive is controlled Device selects the region to be recycled of nonvolatile memory；Main frame selects nonvolatile memory for first reason Region to be recycled, and solid state drive controller selected for the second different reasons nonvolatile memory treat follow again The region of ring；And foregoing every any combinations.In one example, the to be recycled of nonvolatile memory is performed on main frame Region whole selections.In another example, main frame selects nonvolatile memory for garbage collection reason Region to be recycled, and solid state drive controller selected for wear leveling reason nonvolatile memory treat follow again The region of ring.In a further example, main frame selects nonvolatile memory for garbage collection and wear leveling reason Region to be recycled, and solid state drive controller is (such as program mal, excessively wrong for unusual condition and/or mistake Correction decoding error or reading interference event by mistake) reason and select the region to be recycled of nonvolatile memory.Entering one Walk in embodiment, solid state drive controller is enabled to (for example compile one or more statistics of nonvolatile memory Journey/erasing is counted and/or used dimensional dtatistical figures) it is delivered to main frame.For example, statistics is via solid-state drive The member-retaining portion in the logical block address space of controller or by using using read and/or write the special command of statistics as Daily record (such as SMART daily records) and transmit.In some embodiments and/or using scene, statistics is delivered into main frame makes Winner's machine can select the region to be recycled of nonvolatile memory, and solid state drive controller is enabled to from main frame Unload the maintenance of statistics.

In certain embodiments, solid state drive controller is enabled to make nonvolatile memory independently of main frame At least a portion recycles and updated physical location is delivered into main frame.For example, in response to unusual condition and/or mistake By mistake, such as program mal, excessive error correction decoding error or reading interference event, solid state drive controller determines non-volatile The region that must be recycled of property memory.Header in the region of solid state drive controller reading non-volatile storage and By any different portions that nonvolatile memory is still repositioned onto for current data in the region of nonvolatile memory Corresponding new physical locations in point.According to various embodiments, in one or more embodiments：Solid-state drive maintain mapping and The mapping can be updated to reflect the corresponding new physical locations still for current data；Solid state drive controller is maintained by solid The unitary part mapping for the data that state driver controller is repositioned, the unitary part mapping makes nonvolatile memory The instruction still for the physical location of current data in region is associated with corresponding new physical locations；Solid state drive controller Corresponding new physical locations are delivered to together with the information (such as being still the corresponding identifier of current data) from header Main frame, and main frame more new mappings；And foregoing every any combinations.Advantageously, can be in the region of nonvolatile memory and phase Answer accessed in both new physical locations still for current data untill the region of erasable nonvolatile memory.Further In embodiment, the region of erasable nonvolatile memory is not until untill after corresponding new physical locations more new mappings.Citing For, main frame informs solid state drive controller more new mappings, and then only solid state drive controller is enabled to erasing The region of nonvolatile memory.

In various embodiments, main frame (such as) is by asking several nonvolatile memories page or pending to be read Several for being sent to main frame extract header and control nonvolatile memory page from the nonvolatile memory for recycling Reading (step 1410).According to various embodiments, main frame perform header dissect at least some steps in (step 1418) and/ Or solid state drive controller (such as) extracts header by pretreatment and/or reformatting and/or filtering and performs mark At least some steps in head anatomy.In a further embodiment, main frame performs Map Searching (step 1422) and determined whether Need to rewrite any data in data.Rewrite (step 1426) by solid state drive controller under the control of main frame (for example Still occur " to rewrite " order for current data for any by main frame) perform.Rewrite command is similar to writing commands, but Without write-in data, the physical location that rewrite command is included as reading order in nonvolatile memory (just makes data From its recycling position) instruction.Similar to writing commands, rewrite command returns to the finger for the new physical locations for rewriteeing data Show, and main frame performs step 1430 with more new mappings.The relevant embodiment of the major part of main frame implementation procedure 1400 wherein In, rewrite command includes still being buffer position of the current data in solid state drive controller.

In certain embodiments, the unique order hosted of non-standard and/or supplier and solid state drive controller it Between communication protocol part.According to various embodiments, communication protocol is one or more of the following：SATA, small calculating Machine system interface (for example, SCSI), SAS, periphery component interconnection express delivery (for example, PCIe), NVM express deliveries (Express) are (non-volatile Property memory), the upper SCSI of PCIe (for example, SOP), Mobile Express, USB, UFS, embedded multi-media card (for example, EMMC), any other agreement that Ethernet, optical-fibre channel or be suitable for communicates between two electronic installations.In one example, Transmission of the instruction of physical location between main frame and solid state drive controller is read using supplier's uniqueness order, such as standard Take and writing commands the unique version of supplier.In another example, header will be extracted with log page (example for recycling Such as SMART log pages) form is delivered to main frame from solid state drive controller.In a further example, header is extracted to be similar to Read data and handle, but read by means of unique " header is extracted in the reading " order of supplier.

According to various embodiments, any one of the step of process 1200 and/or process 1300 and/or process 1400 by with One or more of lower items are performed：It is coupled to the main frame of solid state drive controller；It is coupled to the solid-state drive control of main frame Device processed；And foregoing every any combinations.In one example, Map Searching is performed on main frame and mapping is maintained.In another reality In example, the determination of the number of reading unit is performed on any one of main frame and solid state drive controller or both.Again In one example, performed on solid state drive controller and piece write-in data in nonvolatile memory page (for example, step together 1222).In one example, write-in data are pieced together under the control of main frame non-in the buffer of solid state drive controller In volatile memory page image.In another example, performed on solid state drive controller from reading unit and extract data (for example, step 1326).In a further example, compression (for example, step 1214) and solution are performed on solid state drive controller Compress (for example, step 1330).In one example, statistics is maintained on solid state drive controller (for example, step 1238 Or step 1338).In another example, the region (example to be recycled for determining nonvolatile memory is performed on main frame Such as, step 1406).In a further example, performed on solid state drive controller by it is to be recycled be still current data New position (for example, step 1426) is moved to from old position.

In certain embodiments, main frame and/or solid state drive controller maintain to make multiple areas of nonvolatile memory Each of domain table associated with specified properties and/or feature.In one example, the table makes nonvolatile memory Each of region is associated with the specific one in multiple code checks (error-correcting code intensity), so that being stored in region Each of in data volume can be changed according to " health " in each of region.Used compared with healthy area higher (weaker) code check and storage is enabled to compared with multi-user data, and weaker area is using relatively low (stronger) code check and is enabled to deposit Store up less user data (but being enabled to correct more mistake).In another example, it is defective in the table indicating area or Region that is failed and should not being used.For example, some in the case of NAND Flash, in multiple pieces of NAND Flash Block is also defective even when NAND Flash is new, and other pieces in described piece can during the life-span of NAND Flash Can failure.The table indicates to jump when sequentially writing data (for example, making its striping) across multiple NAND Flash devices The block crossed.

In certain embodiments, the relatively superordinate part of mapping is maintained on main frame, and is tieed up on solid state drive controller Hold the lower level part of mapping.The relatively superordinate part of mapping makes mark (or logical block address) and the thing in nonvolatile memory Managing the corresponding instruction of position is associated.Then further translate non-using the lower level part of mapping by solid state drive controller Physical department of the instruction of physical location in volatile memory to determine the to be read of nonvolatile memory and/or write Point.From the perspective of main frame, opaque handle is served as in the instruction of physical location, because solid state drive controller is by thing One of the instruction for managing position is assigned to certain data objects in write-in, and solid state drive controller be enabled to The correspondence for returning physical location returns to certain data objects when indicating.In other words, the subscriber data set in nonvolatile memory The knowledge for the specific details knitted is hiding to main frame.Advantageously, solid state drive controller be enabled to perform it is non-volatile At least some management of memory, for example select code check or determine bad block or nonvolatile memory do not used by main frame its Its part.

In one example, when the specific one in multiple pieces first by nonvolatile memory, solid-state drive Each of multiple pages of specific piece are divided into multiple (for example, eight) corresponding reading unit and special using being used for by controller Specific one in the multiple code checks for the error correction for determining block.Later, reused when after specific piece is more lost During the specific piece, each of multiple pages of the specific piece are divided into multiple (for example, seven by solid state drive controller It is individual) corresponding reading unit and the error correction for the specific piece use stronger one in code check.In both cases, when When main frame write-in is stored in the data in specific piece, the instruction of the physical location in the specific piece is independently of the specific piece Several reading units that page is divided into.

In another example, as many person of the variable-size data in multiple pieces of nonvolatile memory, by leading The instruction for the physical location that machine is used is in use or had been labeled as independently of any specific piece of nonvolatile memory Knowledge that is bad and being not used by.Continue another example, it is assumed that the specific one in multiple nude films of nonvolatile memory Block 7 be bad and be not used by.When the data in the block 6 of the previous one in the nude film span to subsequent block, solid-state Driver controller uses the block 6 of particular die.When the data in the block 7 of previous nude film span to subsequent block, solid-state driving Device controller skips the data in the block 7 of the block 7 of particular die and the lower one in continuation nude film.Main frame does not have on data The knowledge of any one in block.

According to various embodiments, for example, the consistency operation cleaned and recycled is read by main frame, solid state drive controller And its one or more of any combinations are performed.

According to various embodiments, any operation of the processor of main frame and/or solid state drive controller is by one or more Any one of CPU, perform by one or more hardware cells and/or by foregoing every any combinations.

According to various embodiments, main frame and/or solid state drive controller be enabled to use in the following one or Many persons：Traditional flash transition layer；Variable-size quick flashing transition layer；Through the variable-size quick flashing transition layer for reading optimization in proper order；Appoint What other types of quick flashing translation layer；Nonvolatile memory is directly accessed；The different physical departments of nonvolatile memory Any combinations of foregoing teachings in point；The Different Logic part of the logical address space of solid state drive controller it is foregoing in Any combinations of appearance；Original physical access to nonvolatile memory；And foregoing every any combinations.

According to various embodiments, main frame write-in data optionally and/or are optionally being written to nonvolatile memory It is encrypted and optionally and/or is optionally decrypted after being read from nonvolatile memory before.Further implementing In example, it is encrypted in after optionally and/or optionally compression main frame write-in data and occurs, and decrypts by the data just read Optionally and/or optionally decompress to return to generation before main frame.

Although several example embodiments herein use solid-state drive and solid state drive controller, described Technology be commonly available to other input/output devices and/or data storage device, such as hard disk drive.Implement various In example, the nonvolatile memory used in this little input/output device is in addition to " solid-state " nonvolatile memory The magnetic sheet of nonvolatile memory, such as hard disk drive (for example, using the hard disk drive of stacked tile type magnetic recording).

In certain embodiments, by multinode storage device or part thereof (for example hard disk drive or be enabled to and Manage solid magnetic disc or non-volatile memory controller, the input/output of the input/output device of device (such as CPU) interoperability It is the part of controller (such as RAID nude films on chip) and processor, microprocessor, system-on-a-chip, application specific integrated circuit, hard Part accelerator or provide aforementioned operation all or part of other circuits) perform operation all or part of various combinations Specified by the specification compatible with the processing that computer system is carried out.The specification is according to various descriptions, such as Hardware description language Speech, circuit description, netlist describe, shelter description or layout description.Example description including but not limited to：Verilog, VHDL are (super High-speed integrated circuit hardware description language), SPICE (integrated circuit GPS), SPICE variants (such as PSpice), IBIS (input/output (i/o) buffer information norm), LEF (storehouse DIF), DEF (design DIF), GDS-II (figure numbers According to storehouse system II), OASIS (open artwork system exchange standard) or other descriptions.In various embodiments, processing includes solution Any combination translated, compile, simulate and synthesized is suitable for inclusion in patrolling on one or more integrated circuits to produce, examine or specify Collect and/or circuit.According to various embodiments, each integrated circuit can be designed and/or manufactured according to multiple technologies.The technology Comprising Programmable Technology (for example, scene or shelter programmable gate array integrated circuit), semicustom technology (for example, completely or portion Point integrated circuit of the ground based on unit) and the full custom technology integrated circuit of specialization (for example, substantially), its any combinations or Any other technology compatible with the design and/or manufacture of integrated circuit.

The function of being performed by Fig. 1 to 14 schema can be used one or more of the following to implement：Conventional general place Manage device, digital computer, microprocessor, microcontroller, RISC (Reduced Instruction Set Computer) processor, CISC (complicated orders Collection computer) processor, SIMD (single-instruction multiple-data) processor, signal processor, CPU (CPU), arithmetic patrols Collect the similar computer of unit (ALU), video digital signal processor (VDSP) and/or the teaching programming according to this specification Device, such as it will be apparent to those skilled in the art that.Skilled programmar can easily be prepared suitable based on teachings of the present invention When software, firmware, decoding, routine, instruction, command code, microcode and/or program module, such as those skilled in the art also will Understand.Generally the software is performed by one or more of processor of machine embodiment from a media or several media.

The present invention can also be implemented by the preparation of the following：ASIC (application specific integrated circuit), platform ASIC, FPGA (field programmable gate array), PLD (programmable logic device), CPLD (complex programmable logic device), the door (sea- of magnanimity Of-gate), RFIC (RF IC), ASSP (Application Specific Standard Product), one or more monolithic integrated optical circuits, be arranged as down One or more chips or nude film of cartridge chip module and/or multi-chip module, or by interconnecting the appropriate net of conventional component circuits Network, as described in this article, those skilled in the art will be readily apparent that the modification of the conventional component circuits.

Therefore, the present invention can also include computer product, its can be comprising available for programming machine to perform according to this hair The storage media and/or transmission media of the instruction of bright one or more processes or method.Machine is to contained in computer product Instruction execution together with the operation of peripheral circuits input data can be transformed into one or more files in storage media and/or Represent one or more output signals of physical object or assets (such as audio and/or visual depiction).The storage media can be wrapped Contain but be not limited to：Any kind of disk, comprising floppy disk, hard disk drive, disk, CD, CD-ROM, DVD and magneto-optic disk and Circuit, such as ROM (read-only storage), RAM (random access memory), EPROM (erasable programmable ROM), EEPROM (electricity Erasable programmable ROM), UVPROM (ultraviolet light erasable programming ROM), flash memory, magnetic card, light-card and/or be adapted to In any kind of media of storage e-command.

The key element of the present invention can form the part or complete of one or more devices, unit, component, system, machine and/or equipment Portion.Described device can be including but not limited to：Server, work station, storage array controllers, storage system, personal computer, knee Laptop computer, mobile computer, palmtop computer, personal digital assistant, portable electron device, battery are powered dress Put, set top box, encoder, decoder, code converter, compressor reducer, decompressor, preprocessor, preprocessor, transmitter, reception Device, transceiver, cryptochannel, cellular phone, digital camera, positioning and/or navigation system, medical equipment, HUD, Wireless device, audio recording, audio storage and/or audio playback, videograph, video storage and/or video playback dress Put, gaming platform, ancillary equipment and/or multi-chip module.Those skilled in the art will appreciate that, key element of the invention can be Implement to meet the criterion of application-specific in other types of device.

Term "available" and " usual " be intended to when being used herein in conjunction with "Yes" and verb reception and registration be described as it is exemplary and Believe the particular instance presented extensively to include in the disclosure enough and can be based on derived from the disclosure The intention of both alternate examples."available" and " usual " should not be construed as certain imply and omit correspondence as used herein, the term The expectation of key element or possibility.

Although the present invention, those skilled in the art has been illustrated and described referring in particular to embodiments of the invention It will be understood that, the various changes in form and details can be made in the case of without departing substantially from the scope of the present invention.

Claims

1. a kind of method for being used to carry out data storage using segmented quick flashing transition layer, it comprises the following steps：

The first data to be written are received from main frame；And

The second data produced by first data are stored in the nonvolatile memory, wherein first data are compressed To produce second data, second data have a variable-size, and second data storage non-volatile is deposited described Multiple physical locations in reservoir, the initial physical location preserved in the multiple physical location of second data is institute Next non-writing position in nonvolatile memory is stated, the information related to the size of second data is stored in phase Be for the nonvolatile memory the local quick flashing transition layer the first subregion in, and to the non-volatile memories The instruction of the initial physical location of second data in device is stored in the quick flashing transition layer in the main frame In second subregion.

2. according to the method described in claim 1, it further comprises the steps：

The reading order of the initial physical location with second data is received from the main frame；

The size of second data is read from first subregion of the quick flashing transition layer；And

The nonvolatile memory is read by the size based on the initial physical location and second data A part and retrieve second data.

3. method according to claim 2, it further comprises the steps：

By the way that first data will be re-formed from second data decompression that the nonvolatile memory is retrieved； And

First data re-formed are returned into the main frame.

4. according to the method described in claim 1, it further comprises the steps：

The identifier associated with first data is stored in the nonvolatile memory as with described second and counted According at least a portion of associated header.

5. method according to claim 4, it further comprises the steps：

Mapping is maintained in the main frame, wherein the mapping makes described in the identifier and the nonvolatile memory the The initial physical location of two data is associated.

6. method according to claim 4, wherein the identifier is logical block address, the initial physical location is to protect The physical address in one of multiple reading units in the nonvolatile memory of second data is deposited, and it is described Each of multiple reading units include the appropriate section of second data and protect the described corresponding of second data Partial corresponding error recovery information.

7. method according to claim 6, wherein the nonvolatile memory has multiple pages, the address is being preserved In first page in the multiple page of second data, the first page preserves second data comprising the first number The multiple reading unit, the second page in the multiple page includes the described many of the second number preservation second data Individual reading unit, and first number is different from second number.

8. according to the method described in claim 1, wherein next non-writing position adjoins the nonvolatile memory Data are previously written in physical address space.

9. according to the method described in claim 1, wherein the step is performed in solid state drive controller.

10. a kind of method for being used to carry out data storage using segmented quick flashing transition layer, it comprises the following steps：

The data to be written are received from main frame, wherein the data have variable-size；And

By the data storage in nonvolatile memory, wherein the data storage is in the nonvolatile memory Multiple physical locations, wherein the initial physical location in preserving the multiple physical locations of the data is described non-volatile Next non-writing position in property memory, the information related to the size of the data is stored in non-volatile relative to described During property memory is the first subregion of the local quick flashing transition layer, and to the data in the nonvolatile memory The instruction of the initial physical location be stored in the second subregion of the quick flashing transition layer in the main frame.

11. method according to claim 10, it further comprises the steps：

Received from the main frame with the initial physical location in the nonvolatile memory for preserving the data Reading order；

The size of the data is read from first subregion of the quick flashing transition layer；And

The one of the nonvolatile memory is read by the size based on the initial physical location and the data Partly retrieve the data.

12. method according to claim 11, it further comprises the steps：

The data are returned into the main frame.

13. method according to claim 10, it further comprises the steps：

The identifier associated with the data is stored in the nonvolatile memory as associated with the data Header at least a portion.

14. method according to claim 13, it further comprises the steps：

Mapping is maintained in the main frame, wherein the mapping makes the identifier and number described in the nonvolatile memory According to the initial physical location be associated.

15. method according to claim 13, wherein the identifier is logical block address, the initial physical location is The physical address in one of multiple reading units in the nonvolatile memory of the data is preserved, and it is described many Each of individual reading unit includes the appropriate section of the data and protects the corresponding of the appropriate section of the data Error recovery information.

16. method according to claim 15, wherein the nonvolatile memory has multiple pages, the address is being protected Deposit in the first page in the page of the data, the first page preserves the multiple of the data comprising the first number Second page in reading unit, the multiple page preserves the multiple reading unit of the data comprising the second number, and First number is different from second number.

17. method according to claim 10, wherein next non-writing position adjoins the nonvolatile memory Physical address space in be previously written data.

18. method according to claim 10, wherein the step is performed in solid state drive controller.

19. a kind of equipment, it includes：

Interface, it is configured to multiple operations that processing is read or written to nonvolatile memory from nonvolatile memory； And

Circuit is controlled, it is configured to receive the first data from main frame, and the second data produced by first data are deposited Storage is in the nonvolatile memory, wherein first data are compressed to produce second data, described second counts According to variable-size, second data storage preserves described in multiple physical locations of the nonvolatile memory Initial physical location in the multiple physical location of second data is that next in the nonvolatile memory does not write Position, it is local that the information related to the size of second data, which is stored in relative to the nonvolatile memory, In first subregion of quick flashing transition layer, and to the initial physical position of second data in the nonvolatile memory The instruction put is stored in the second subregion of the quick flashing transition layer in the main frame.

20. equipment according to claim 19, wherein the interface and the control circuit are solid state drive controllers A part.