TWI633433B - 控制非易失性記憶體之系統與方法 - Google Patents

控制非易失性記憶體之系統與方法 Download PDF

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Publication number
TWI633433B
TWI633433B TW103104182A TW103104182A TWI633433B TW I633433 B TWI633433 B TW I633433B TW 103104182 A TW103104182 A TW 103104182A TW 103104182 A TW103104182 A TW 103104182A TW I633433 B TWI633433 B TW I633433B
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TW
Taiwan
Prior art keywords
volatile memory
interface
block
control
microsequencer
Prior art date
Application number
TW103104182A
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English (en)
Chinese (zh)
Other versions
TW201502775A (zh
Inventor
克里斯多福 布魯爾
厄爾 柯恩
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Lsi公司
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Publication of TW201502775A publication Critical patent/TW201502775A/zh
Application granted granted Critical
Publication of TWI633433B publication Critical patent/TWI633433B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0613—Improving I/O performance in relation to throughput
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Human Computer Interaction (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Microcomputers (AREA)
  • Memory System (AREA)
  • Advance Control (AREA)
TW103104182A 2013-02-15 2014-02-07 控制非易失性記憶體之系統與方法 TWI633433B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/768,215 US9081666B2 (en) 2013-02-15 2013-02-15 Non-volatile memory channel control using a general purpose programmable processor in combination with a low level programmable sequencer
US13/768,215 2013-02-15

Publications (2)

Publication Number Publication Date
TW201502775A TW201502775A (zh) 2015-01-16
TWI633433B true TWI633433B (zh) 2018-08-21

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW103104182A TWI633433B (zh) 2013-02-15 2014-02-07 控制非易失性記憶體之系統與方法

Country Status (6)

Country Link
US (2) US9081666B2 (enExample)
EP (1) EP2767899A3 (enExample)
JP (1) JP6577166B2 (enExample)
KR (1) KR102170644B1 (enExample)
CN (2) CN110134442A (enExample)
TW (1) TWI633433B (enExample)

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JP2017531856A (ja) * 2014-10-03 2017-10-26 エイジェンシー・フォー・サイエンス，テクノロジー・アンド・リサーチ アクティブストレージユニットおよびアレイ
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JP2020046918A (ja) 2018-09-19 2020-03-26 キオクシア株式会社 記憶装置及び制御方法
WO2020223849A1 (en) 2019-05-05 2020-11-12 Yangtze Memory Technologies Co., Ltd. Memory control system with a sequence processing unit
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US11249674B2 (en) * 2020-06-03 2022-02-15 Innogrit Technologies Co., Ltd. Electrical mirroring by NAND flash controller
DE102020207616A1 (de) * 2020-06-19 2021-12-23 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren zum Betreiben einer Recheneinheit
US11755208B2 (en) * 2021-10-12 2023-09-12 Western Digital Technologies, Inc. Hybrid memory management of non-volatile memory (NVM) devices for use with recurrent neural networks
US11893244B2 (en) 2021-10-12 2024-02-06 Western Digital Technologies, Inc. Hybrid memory management of non-volatile memory (NVM) devices for use with recurrent neural networks
EP4437417A1 (en) * 2021-11-22 2024-10-02 Rambus Inc. Logging burst error information of a dynamic random access memory (dram) using a buffer structure and signaling
KR102643031B1 (ko) * 2023-09-07 2024-03-04 주식회사 잇다반도체 프로그램 가능 시퀀서와 이를 이용한 시스템 온 칩 장치

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Also Published As

Publication number Publication date
KR102170644B1 (ko) 2020-10-27
US9262084B2 (en) 2016-02-16
EP2767899A3 (en) 2016-08-17
CN110134442A (zh) 2019-08-16
JP2014157603A (ja) 2014-08-28
CN103995686A (zh) 2014-08-20
JP6577166B2 (ja) 2019-09-18
EP2767899A2 (en) 2014-08-20
TW201502775A (zh) 2015-01-16
US20150268870A1 (en) 2015-09-24
US20140237162A1 (en) 2014-08-21
CN103995686B (zh) 2019-06-28
KR20140103048A (ko) 2014-08-25
US9081666B2 (en) 2015-07-14

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