WO2018039855A1 - 内存装置、内存控制器、数据缓存装置及计算机系统 - Google Patents

内存装置、内存控制器、数据缓存装置及计算机系统 Download PDF

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Publication number
WO2018039855A1
WO2018039855A1 PCT/CN2016/097130 CN2016097130W WO2018039855A1 WO 2018039855 A1 WO2018039855 A1 WO 2018039855A1 CN 2016097130 W CN2016097130 W CN 2016097130W WO 2018039855 A1 WO2018039855 A1 WO 2018039855A1
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data
signal line
memory
dqs signal
nvm
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PCT/CN2016/097130
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English (en)
French (fr)
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肖世海
杨伟
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华为技术有限公司
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Priority to PCT/CN2016/097130 priority Critical patent/WO2018039855A1/zh
Priority to CN201680058607.2A priority patent/CN108139993B/zh
Publication of WO2018039855A1 publication Critical patent/WO2018039855A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Definitions

  • the present invention relates to the field of computer storage, and in particular, to a memory device, a memory controller, a data cache device, and a computer system.
  • NVM Non-volatile Memory
  • PCM Phase Change Memory
  • the memory controller generally accesses the data in the DRAM through the DDR bus, and the data read and write has a certain delay, and the read latency and the write latency of the DRAM are generally fixed values of about 30 ns, and the PCM, etc.
  • the read latency of NVM is about 100ns, and the write latency is about 500ns. The difference between the two is large. Because the read and write timing of the DDR bus is designed based on the read and write latency of the DRAM, if you want to use NVM in DDR. On the bus, you need to solve the timing compatibility problem.
  • the NVM is usually not directly connected to the DDR bus, but is connected to the DDR bus through the NVM controller, and is temporarily stored in the NVM through the buffer space inside the NVM controller.
  • the structure of the NVM controller can be seen in Figure 1.
  • both the data to be written to the NVM and the data read from the NVM need to be scheduled and cached inside the NVM controller, which will result in delays in data reading and writing. fixed. Since the read/write delay is not fixed, the NVM controller and the memory controller need to exchange NVM-related information to ensure the accuracy of the data transmission process. For example, when the NVM controller sends the read data to the memory controller, it needs to notify the memory controller of the correspondence between the read data and the read request issued by the memory controller; for example, when the NVM internal cache space When it is full, the NVM controller needs to notify the memory controller that the internal cache space is full and cannot continue to write data.
  • the present application provides a memory device, a memory controller, a data cache device, and a computer system to solve the problem that no additional data can be transmitted between the NVM controller and the memory controller.
  • a memory device comprising: a non-volatile memory NVM; an NVM controller connected to the memory controller via a double rate DDR bus, the NVM controller according to the memory controller The command performs a memory access operation on the NVM and performs data transmission with the memory controller on a portion of the DQS signal line in the DDR bus.
  • the DDR bus includes a plurality of sets of data buses, wherein each set of data buses includes a DQ signal line, a first DQS signal line, and a second DQS signal line
  • the NVM controller performs the first DQS signal transmitted on the first DQS signal line in the first group of data buses on the DQ signal line and the second DQS signal line in the first group of data buses with the memory controller.
  • Data transmission, the first set of data buses being any one of the plurality of sets of data buses.
  • the NVM controller is in the first set of data buses according to a first DQS signal transmitted on a first DQS signal line in the first set of data buses Data transmission with the memory controller on the DQ signal line and the second DQS signal line, including: the NVM controller is on the DQ signal line in the first group of data buses according to the first DQS signal
  • the memory controller performs transmission of target data, the target data including at least one of data to be written to the NVM and data read from the NVM; in the first group of data buses In the process of transmitting the target data by the DQ signal line, the NVM controller performs data transmission with the memory controller on a second DQS signal line of the first group of data buses according to the first DQS signal.
  • the target data includes first target data read from the NVM
  • the NVM controller is configured according to the first DQS signal Data transmission with the memory controller on a second DQS signal line in the first group of data buses, including: in the process of transmitting the first target data by the DQ signal line in the first group of data buses Transmitting, by the NVM controller, first data according to the first DQS signal on a second DQS signal line in the first group of data buses, where the first data includes the first destination At least one of an identification of the target data and a memory address of the first target data.
  • the first data further includes at least one of the following: an identifier of data that has been written into the NVM; indicating whether data is successfully written Information of the NVM; and information indicating a status of a data cache in the NVM controller.
  • the target data includes second target data to be written to the NVM
  • the NVM controller is in the first according to the first DQS signal Data transmission with the memory controller on a second DQS signal line in the group data bus, including: in the process of transmitting the second target data by the DQ signal line in the first group of data buses, the NVM The controller receives second data on a second DQS signal line of the first set of data buses according to the first DQS signal, the second data including an identifier of the second target data.
  • the NVM includes at least one RANK.
  • the verification information of the data such as an Error Correction Code (ECC) of the data, may also be transmitted on the second DQS signal line of the first group of data buses.
  • ECC Error Correction Code
  • a memory controller in a second aspect, includes: a scheduler, configured to receive a memory access request of the processor; and a memory bus interface connected to the memory device through a double rate DDR bus, the memory bus And transmitting, by the interface, a command for accessing the non-volatile memory NVM in the memory device to the memory device according to the memory access request, and on a part of the DQS signal line in the DDR bus and the memory device Data transfer.
  • the DDR bus includes a plurality of sets of data buses, wherein each set of data buses includes a DQ signal line, a first DQS signal line, and a second DQS signal line
  • the memory bus interface performs data with the memory device on the DQ signal line and the second DQS signal line in the first group of data buses according to the first DQS signal transmitted on the first DQS signal line in the first group of data buses.
  • Transmission, the first set of data buses being any one of the plurality of sets of data buses.
  • the memory bus interface is in the first set of data according to a first DQS signal transmitted on a first DQS signal line in the first set of data buses Data transmission between the DQ signal line and the second DQS signal line in the bus and the memory device, including: the memory bus interface is in the first group according to the first DQS signal Transmitting target data with the memory device according to a DQ signal line in the bus, the target data including at least one of data to be written into the NVM and data read from the NVM; During the transmission of the target data by the DQ signal line in the first group of data buses, the memory bus interface is on the second DQS signal line in the first group of data buses according to the first DQS signal.
  • the memory device performs data transmission.
  • the target data includes first target data read from the NVM, the memory bus interface being in accordance with the first DQS signal Data transmission with the memory device on a second DQS signal line in the first set of data buses, including: in a process of transmitting the first target data by a DQ signal line in the first group of data buses, The memory bus interface receives first data on a second DQS signal line of the first set of data buses according to the first DQS signal, the first data including an identifier of the first target data and the first At least one of the memory addresses of the target data.
  • the first data further includes at least one of the following: an identifier of data that has been written into the NVM; indicating whether data is successfully written Information of the NVM; and information indicating a status of a data cache in the NVM controller.
  • the target data includes second target data to be written to the NVM, the memory bus interface being in the first according to the first DQS signal Performing data transmission with the memory device on the second DQS signal line in the group data bus, including: in the process of transmitting the second target data by the DQ signal line in the first group of data buses, the memory bus The interface transmits second data on the second DQS signal line of the first group of data buses according to the first DQS signal, the second data including an identifier of the second target data.
  • the memory bus interface may determine the type of the storage unit to be accessed. When determining that the storage unit to be accessed is a DRAM, the memory bus interface selects a functional interface corresponding to the DRAM. Access DRAM. In the case that it is determined that the storage unit to be accessed is an NVM, the memory bus interface selects a function interface corresponding to the NVM to access the NVM. Among them, the functional interface can be a logical interface. In practice, two functional interfaces can share the same set of physical interfaces.
  • the NVM includes at least one RANK.
  • a data cache device is provided, wherein the data cache device is located in a memory Between the controller and the memory device, and connected to the memory controller and the memory device through a double rate DDR bus, the memory device includes a non-volatile memory NVM, and the data cache device includes: a memory bus An interface, in a process in which the memory controller sends data to be written to the NVM or receives data read from the NVM from the memory device, the memory bus interface receives the Data transmitted on a portion of the DQS signal line in the DDR bus; a buffer for buffering data received by the memory bus interface.
  • the DDR bus includes a plurality of sets of data buses, wherein each set of data buses includes a DQ signal line, a first DQS signal line, and a second DQS signal line,
  • the memory bus interface receives data transmitted on the DQ signal line and the second DQS signal line in the first group of data buses according to the first DQS signal transmitted on the first DQS signal line in the first group of data buses,
  • the first set of data buses is any one of the plurality of sets of data buses.
  • a fourth aspect a computer system, comprising the memory device according to any one of the first aspect or the first aspect, and the memory of any one of the second aspect or the second aspect Controller.
  • the computer system further comprises the data cache device of any one of the third aspect or the third aspect.
  • the DQS signal on the DQS signal line is used to latch the data on the DQ signal line.
  • the present application utilizes a part of the DQS signal line in the DDR bus to transmit data, thereby solving the problem that the memory controller and the memory device cannot transmit extra. The problem with the data.
  • FIG. 1 is a schematic diagram of a connection relationship between a memory controller and an NVM-based memory device.
  • FIG. 2 is a schematic structural diagram of a memory device according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a shared DDR bus of x4 DRAM and x8 DRAM.
  • Fig. 4 is a read/write timing chart of the ⁇ 4 DRAM.
  • Fig. 5 is a read/write timing chart of the ⁇ 8 DRAM.
  • FIG. 6 is a schematic diagram of a shared DDR bus of x4 DRAM and x8 NVM according to an embodiment of the present invention.
  • FIG. 7 is a timing diagram of reading and writing of a ⁇ 8 NVM according to an embodiment of the present invention.
  • FIG. 8 is a timing diagram of reading and writing of a ⁇ 8 NVM according to another embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a memory controller according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a data buffer device according to an embodiment of the present invention.
  • FIG. 11 is a structural diagram of a memory including a DRAM and an NVM according to an embodiment of the present invention.
  • FIG. 12 is a structural diagram of a memory including a DRAM and an NVM according to another embodiment of the present invention.
  • FIG. 13 is a structural diagram of a memory including a DRAM and an NVM according to still another embodiment of the present invention.
  • Figure 14 is a schematic block diagram of a computer system in accordance with an embodiment of the present invention.
  • the memory controller and the memory device are generally connected through a DDR bus.
  • the DDR bus includes an address bus, a command bus, and a data bus.
  • the data bus in the DDR bus includes a Bi-directional Data Strobe (DQS) signal line and a DQ signal line.
  • DQS Bi-directional Data Strobe
  • the memory controller and the memory device perform data transmission on the DQ signal line based on the DQS signal transmitted on the DQS signal line.
  • the memory controller sends the DQS signal and the data to be written to the memory device through the DQS signal line and the DQ signal line, respectively, and the memory device latches (or samples) the DQ signal line based on the received DQS signal. Transmitted data to be written.
  • the memory device sends the DQS signal and the read data to the memory controller through the DQS signal line and the DQ signal line, respectively, and the memory controller latches the DQ signal line transmission based on the DQS signal. Data that has been read.
  • DQ signal line also referred to as DQ signal
  • DQS signal transmitted on the DQS signal line is mainly used to implement clock synchronization between the memory controller and the memory device.
  • the DQS signal is equivalent to a clock synchronization signal.
  • a DQS signal line refers to a line that can logically form a DQS signal.
  • the DQS signal can be transmitted through a physical DQS line.
  • one DQS signal line corresponds to one physical DQS line.
  • the DQS signal is a differential signal, the DQS signal needs to be transmitted through two physical DQS lines.
  • one DQS signal line corresponds to two physical DQS lines.
  • FIG. 2 is a memory device according to an embodiment of the present invention.
  • the memory device 20 includes:
  • the NVM 24 may include at least one NVM chip, for example, the NVM 24 may be an NVM RANK, or the NVM 24 may be an NVM DIMM.
  • the NVM controller 22 is connected to the memory controller through the DDR bus, and the NVM controller 22 performs a memory access operation on the NVM 24 according to the command of the memory controller, and performs data transmission with the memory controller on a part of the DQS signal line in the DDR bus. .
  • DQS signal lines used for transmitting data may be selected in various manners, which will be described in detail below in conjunction with specific embodiments.
  • the DQS signal line for transmitting the data signal can be selected from a set of data buses of the DDR bus.
  • the packet design method of the existing DDR bus is first introduced. .
  • the data bus in the DDR bus includes a plurality of DQS signal lines and a plurality of DQ signal lines.
  • the DDR data bus is generally grouped. Take the DDR bus compatible with ⁇ 4 DRAM (that is, the bit width of DRAM chip is 4 bits) and ⁇ 8 DRAM (that is, the bit width of DRAM chip is 8 bits) as an example, in the standard dual in-line memory module (Dual Inline Memory Modules) In the design of DIMM), usually a set of DDR data bus includes 8 DQ signal lines and 2 DQS signal lines, which are designed to be of equal length on the circuit board, so that whether it is connected to ⁇ 4 DRAM or connected ⁇ 8DRAM, DDR bus can work normally.
  • the operation of the DDR bus compatible with x4 DRAM and x8 DRAM will be described in detail below with reference to Figs.
  • FIG. 3 is a schematic diagram of a shared DDR bus of x4 DRAM and x8 DRAM.
  • 3 shows a total of two DIMMs, wherein the DRAM chip inside the DIMM 0 is ⁇ 4 DRAM, and the DRAM chip inside the DIMM 1 is ⁇ 8 DRAM.
  • FIG. 3 shows a set of data buses in the DDR bus.
  • the set of data buses includes a total of eight DQ signal lines (DQ[0:7] in FIG. 3) and two DQS signal lines (in FIG. 3). DQS[0] and DQS[1]). It should be understood that for convenience of description, FIG. 3 only shows a set of data buses in the DDR bus.
  • the DDR bus may include multiple sets of data buses, for example, DIMMs supporting Error Correction Code (ECC).
  • ECC Error Correction Code
  • the DDR data bus generally includes 72 DQ signal lines and 18 DQS signal lines.
  • the data buses are divided into 9 groups of data buses, and each group of data buses includes 8 DQ signal lines and 2 DQS signal lines;
  • the DDR data bus generally includes 64 DQ signal lines and 16 DQS signal lines. These data buses are divided into 8 groups of data buses.
  • Each group of data buses includes 8 DQ signal lines and 2 DQS signals. line.
  • DQS[0] and DQS[1] are used to transmit DQS signals, among them, DQS [0]
  • the DQS signal transmitted on the DQS signal is used to latch the data transmitted on DQ[0:3]
  • the DQS signal transmitted on DQS[1] is used to latch the data transmitted on DQ[4:7], ⁇ 4DRAM See Figure 4 for specific read and write timing.
  • DIMM 1 since the internal memory chip is ⁇ 8 DRAM, one DQS signal line needs to latch 8 DQ signal lines, so any DQS signal line in DQS[0] and DQS[1] can be completed.
  • the latch of DQ[0:7], the other DQS signal line has no actual signal function.
  • the specific read and write timing of ⁇ 8 DRAM is shown in Figure 5.
  • the difference between Figure 5 and Figure 4 is that in Figure 5, DQS[0] completes the latching of all DQ lines in a group of DQS data buses, and DQS[1] is responsible for The TDQS pin of DIMM 1 is terminated without the need to pass DQS signals.
  • the result of the packet design is that in some cases, some DQS signal lines in a group of data buses do not need to transmit DQS signals, only provide termination functions, such as DIMM 1 in Figure 5.
  • the TDQS pin is connected to DQS [1].
  • each group of data buses in the DDR bus includes a plurality of DQS signal lines.
  • the plurality of DQSs A DQS signal line that does not transmit a DQS signal and only provides termination is present in the signal line.
  • the DQS signal line for transmitting data can be selected as follows.
  • the DDR bus includes multiple sets of data buses, wherein each set of data buses includes a DQ signal line, a first DQS signal line, and a second DQS signal line, and the NVM controller is configured according to the first set of data buses.
  • the first DQS signal transmitted on the first DQS signal line is at the first Data is transmitted from the DQ signal line and the second DQS signal line in the group data bus to the memory controller, wherein the first group of data buses is any one of a plurality of sets of data buses.
  • each of the plurality of sets of data buses can select a DQS signal line for transmitting data in the same manner as the first set of data buses.
  • the DQS signal on the DQS signal line is used to latch data on the DQ signal line.
  • data is transmitted by using part of the DQS signal line in the DDR bus, thereby solving the problem that the memory controller and the memory device cannot be used.
  • the problem of passing extra data For example, NVM-related information can be passed between the memory controller and the memory device to ensure the accuracy of information interaction between the NVM controller and the memory controller.
  • the NVM controller transmits data on the DQ signal line in the first set of data buses based on the first DQS signal. It is assumed that the DDR bus is designed to be compatible with the first bit wide DRAM and the second bit wide DRAM, wherein the second bit width is larger than the first bit width, and the embodiment of the present invention is equivalent to simulating the second bit width by using the NVM controller.
  • the DRAM chip works by latching the data transmitted on the DQ signal line of the first group of data buses through a DQS signal line, so that a DQS signal line that does not need to transmit a DQS signal appears, and this type of DQS signal can be selected. The line transfers additional data, providing the possibility to interact with NVM-related information between the NVM controller and the memory controller.
  • NVM can simulate ⁇ 8 DRAM through the NVM controller (hereinafter this NVM is called ⁇ 8NVM), so that the NVM controller and memory control In the process of interacting data, each DQS signal line of the DDR bus will not need to transmit a DQS signal line.
  • Figure 6 is a schematic diagram of the shared DDR bus of ⁇ 4 DRAM and ⁇ 8NVM. This DQS does not need to transmit DQS signals.
  • the signal line is the DQS1 connected to the TDQS pin in Figure 6.
  • the DDR bus grouping is designed to be compatible with x4 DRAM and x8 DRAM.
  • the DDR data bus can include 72 DQ signal lines and 18 DQS signal lines, and these data buses are divided into 9 groups.
  • Each group includes 8 DQ signal lines and 2 DQS signal lines, and the first group of data buses may be any one of 9 groups, and the first DQS signal line may be 2 DQS signal lines in the first group of data buses. Any one of the other (the second DQS signal line), the first DQS signal is transmitted on the first DQS signal line, and the NVM controller can latch the other eight DQ signals in the first group of data buses according to the first DQS signal.
  • the data is transmitted on the line and the data transmitted on the second DQS signal line is latched.
  • ECC is not supported
  • the DDR data bus can include 64 DQ signal lines and 16 DQS signal lines.
  • the data buses are divided into 8 groups, each group including 8 DQ signal lines and 2 DQS signal lines, and the first group of data buses.
  • the first DQS signal line may be any one of two DQS signal lines in the first group of data buses (the other is the second data bus), and the first DQS signal line
  • the first DQS signal is transmitted, and the NVM controller can latch the data transmitted on the other eight DQ signal lines in the first group of data buses according to the first DQS signal, and latch the data transmitted on the second DQS signal line.
  • the NVM controller performs data transmission with the memory controller on the DQ signal line and the second DQS signal line in the first group of data buses according to the first DQS signal, including: the NVM controller according to the a DQS signal is transmitted to the memory controller on the DQ signal line in the first group of data buses, and the target data includes at least one of data to be written to the NVM and data read from the NVM; During the transmission of the target data by the DQ signal line in the first group of data buses, the NVM controller performs data transmission with the memory controller on the second DQS signal line in the first group of data buses according to the first DQS signal.
  • the RANK in the memory shares the DDR bus, and each RANK performs time division multiplexing on the DDR bus, and does not affect each other.
  • the data bus of the other RANK is in a terminated state, and no signal is transmitted.
  • the embodiment of the present invention utilizes the characteristics of the time division multiplexed DDR data bus between the RANKs, and specifies that the second DQS signal lines in the first group of data buses transmit data in the process of transmitting the target data by the DQ signal lines of the first group of data buses. Based on the time division multiplexing characteristics of the DDR data bus, in the process of transmitting the target data by the DQ signal line of the first group of data buses, the second DQS signal line is occupied by the NVM, and the data transmission on the second DQS signal line is not for other memory or Other RANK data transmissions have an impact.
  • a DDR bus capable of simultaneously connecting x4 DRAM and x8 DRAM will be described in detail below with reference to FIG. Figure 7 shows the flow of NVM controller emulation ⁇ 8 DRAM for data reading and writing.
  • the NVM controller After receiving the activation command (ACT) and the write command (WR), the NVM controller writes the data into the cache space of the NVM controller according to the write delay indicated by the tWL parameter.
  • the DQS signal needs to be acquired from DQS[0], and after the time interval indicated by the tWPRE parameter, the data transmitted on DQ[0:7] is started to be latched, and the time interval indicated by the tRPST parameter.
  • the device will start latching the data transmitted on DQ[0:7] after the time interval indicated by the tRPRE parameter, and stop latching DQ after the time interval indicated by the tRPST parameter [0:7 ] The data transmitted on.
  • DQS[1] also transmits data at the same time, such as transmitting NVM related information, because each group of data
  • the bus includes 8 DQ signal lines and 2 DQS signal lines. Each 64Q data is transmitted through the DQ signal line, and the additional 9 bytes of data can be transmitted by DQS[1], which provides sufficient support for the transmission of NVM related information.
  • the data signals on the second DQS signal line of the first group of data buses may be combined with the first group of data buses.
  • the DQS signals on the first DQS signal line have the same phase, and may also have the same phase as the signal on the DQ signal line of the first group of data buses.
  • FIG. 7 is an example in which the data signals on the second DQS signal line of the first group of data buses are in phase with the signals on the DQ signal lines of each group of data buses;
  • FIG. 8 is the first group of data buses.
  • An example of the phase of the data signal on the second DQS signal line being in phase with the DQS signal on the first DQS signal line of the first set of data buses.
  • the embodiment of the present invention does not specifically limit the data type transmitted on the second DQS signal line in the first group of data buses.
  • the type of the target data transmitted on the DQ signal line in the first group of data buses may be used. Selections are described in detail below in conjunction with specific embodiments.
  • the target data includes first target data read from the NVM, and the NVM controller controls the second DQS signal line and the memory in the first group of data buses according to the first DQS signal.
  • Data transmission comprising: in the process of transmitting the first target data by the DQ signal line in the first group of data buses, the NVM controller sends the second DQS signal line in the first group of data buses according to the first DQS signal.
  • the first data includes at least one of an identifier of the first target data and a memory address of the first target data.
  • the identifier of the first target data may be used to indicate which read request corresponds to the first target data; further, the identifier of the first target data may correspond to the read address of the read request of the first target data.
  • the first data further includes at least one of the following information: an identifier of the data written in the NVM; information indicating whether the data is successfully written to the NVM; and information indicating a status of the data cache in the NVM controller .
  • the target data includes second target data to be written to the NVM, and the NVM controller performs the second DQS signal line on the second DQS signal line of the first group of data buses according to the first DQS signal.
  • Data transmission including: in the process of transmitting the second target data by the DQ signal line in the first group of data buses, the NVM controller receives the second DQS signal line on the first group of data buses according to the first DQS signal Data, the second data includes an identification of the second target data.
  • the identifier of the second target data may be used to indicate which write request corresponds to the second target data; further, the identifier of the second target data may correspond to the write address of the write request of the second target data.
  • verification information of the data such as ECC
  • ECC error code
  • the DQS signal line for transmitting data may be referred to as an NM bus (ie, NVM Message Bus), and the data on the NM bus may be referred to as an NM packet.
  • the NM packet may include an identifier of the data to be written. WID (Write ID).
  • a RID Read ID, that is, an identifier of the data to be read
  • the RID may be set for the data to be read, and the RID of the read data is returned through the NM packet.
  • the RID may not be set for the data to be read, and the address of the read data may be directly returned through the NM packet.
  • the WID of the data that has been written to the NVM, and the status information of whether the WID is valid or not may be carried in the NM packet.
  • the NM packet can include an ECC bit to protect the correctness of the transmitted data.
  • DDR 4 ECC-capable DIMMs have pins that connect 18 DQS signal lines (each DQS signal line includes two differential signal lines), 9 of which are The DQS signal line can be used as an NM bus, and the correspondence between them is as shown in Table 1:
  • NM[0:8] can carry NVM-related information in the manner shown in Table 2.
  • a clock can include 2 beats, each of which can transmit different information.
  • the NM bus can be used to transmit an identification (WID) of the data to be written, and an ECC field for verifying the NM packet (the NM packet of this transmission).
  • the RFU (Reserved For Future Use) in Table 2 is a reserved field.
  • NM[0:8] can carry NVM-related information in the manner shown in Table 3.
  • RID is the identifier of the read data
  • R-ADDR is the address of the read data. Both can be transmitted at the same time, or only one of them can be transmitted.
  • the memory controller reads data
  • the RID of the data to be read is embedded in the read request (or the memory controller and the NVM controller indicate the RID of the data to be read by other means such as synchronous counting)
  • NVM After the controller obtains the data from the NVM, the RID of the data may be carried in the NM packet, so that the memory controller knows which read request the data corresponds to based on the RID.
  • the memory controller when the memory controller reads data, if the NVM cannot obtain the RID corresponding to the read request, after the NVM controller obtains the data from the NVM, the memory address of the data can be carried in the NM packet, so that the memory controller is based on The memory address knows which read request the data corresponds to.
  • the identifier WID of the data written to the NVM may be returned through the NM packet, which is equivalent to confirming the data written to the NVM, and the Valid in Table 3 may indicate whether the returned WID is a valid WID.
  • the STAU can occupy 1 or more bits, indicating whether the data is successfully written to the NVM, or indicating an error in the data writing process.
  • a WC/PWC (write credit increase/persistent write credit increase) field may be added in Table 3 to indicate the remaining capacity (or idle capacity) of the write cache space in the NVM controller, and the like.
  • the memory controller can be determined based on the remaining capacity Whether to write new data.
  • the memory device of the embodiment of the present invention is described in detail below with reference to FIG. 2 to FIG. 8.
  • the memory controller of the embodiment of the present invention is described in detail below with reference to FIG. 9. It should be understood that the signal processing between the memory controller and the memory device is understood. The method is similar, for the sake of brevity, it will not be detailed here.
  • FIG. 9 is a schematic structural diagram of a memory controller according to an embodiment of the present invention.
  • the memory controller 90 of Figure 9 includes:
  • a scheduler 92 configured to receive a memory access request of the processor
  • the memory bus interface 94 is connected to the memory device through a double rate DDR bus, and the memory bus interface 94 sends, to the memory device, a nonvolatile memory NVM for accessing the memory device according to the memory access request. And transmitting data to the memory device on a portion of the DQS signal line in the DDR bus.
  • the DQS signal line is used to latch data on the DQ signal line.
  • the embodiment of the present invention utilizes a part of the DQS signal line in the DDR bus to transmit data, thereby solving the problem that the memory controller and the memory device cannot transmit additional data. problem.
  • NVM-related information can be passed between the memory controller and the memory device to ensure the accuracy of information interaction between the NVM controller and the memory controller.
  • the memory bus interface 94 may determine the type of the storage unit to be accessed. In the case where the storage unit is a DRAM, the memory bus interface 94 selects a functional interface corresponding to the DRAM to access the DRAM. In the case where the storage unit is NVM, the memory bus interface 94 selects a function interface corresponding to the NVM to access the NVM.
  • the above storage unit may be, for example, RANK.
  • the memory bus interface 94 can determine the type of memory cells to be accessed in various ways.
  • the DIMM has a Serial Presence Detect Electrically Erasable Programmable Read-Only (Serial Presence Detect Electrically Erasable Programmable Read-Only) Memory, SPD EEPROM), the EEPROM can be accessed through a serial interface other than the DDR address/data/command bus, in which type information of the memory unit (such as RANK type information) can be stored, and the memory bus interface 94 can pass Access the EEPROM to know the type of memory unit.
  • type information of the memory unit such as RANK type information
  • the memory bus interface 94 can include two functional interfaces: FUNC1 and FUNC2. It should be understood that the functional interface may be a logical interface. In practice, two functional interfaces may share the same set of physical interfaces. Taking x8 DRAM as an example, two functional interfaces may share eight DQ signal lines and two. DQS signal line. FUNC1 can support the data transmission mode of DRAM. For example, for ⁇ 4 DRAM, each data bus includes two DQS signal lines, and the DQS signal transmitted on one DQS signal line latches data transmitted on four DQ lines; for ⁇ 8 DRAM Each group of data bus includes two DQS signal lines.
  • the DQS signal transmitted on one DQS signal line can latch the data transmitted on the eight DQ signal lines, and the other DQS signal line does not transmit the signal, and only provides the termination function.
  • FUCN2 can be a functional interface that supports DQS signal line transmission data.
  • each group of data packets includes two DQS signal lines, and one DQS signal transmitted on the DQS signal line latches data transmitted on eight DQ signal lines.
  • Another DQS signal line is also used to pass data, for example, to pass NVM related information.
  • the DDR bus includes a plurality of sets of data buses, wherein each set of data buses includes a DQ signal line, a first DQS signal line, and a second DQS signal line, and the memory bus interface 94 is The first DQS signal transmitted on the first DQS signal line in the first group of data buses is data-transmitted with the memory device on the DQ signal line and the second DQS signal line in the first group of data buses.
  • the memory bus interface 94 performs data with the memory device on the DQ signal line and the second DQS signal line in the first group of data buses according to the first DQS signal. Transmitting, comprising: the memory bus interface 94 performing target data transmission with the memory device on a DQ signal line in the first group of data buses according to the first DQS signal, where the target data includes a to-be-written At least one of data of the NVM and data read from the NVM; the memory bus interface 94 is in the process of transmitting the target data by a DQ signal line in the first set of data buses And performing data transmission with the memory device on the second DQS signal line of the first group of data buses according to the first DQS signal.
  • the target data includes first target data read from the NVM
  • the memory bus interface 94 is in the first group of data buses according to the first DQS signal.
  • the memory bus interface 94 is based on The first DQS signal receives first data on a second DQS signal line of the first set of data buses, the first data including an identifier of the first target data and a memory of the first target data At least one of the addresses.
  • the first data further includes at least one of the following information: an identifier of data that has been written in the NVM; indicating whether data is successfully written to the NVM Information; and information indicating a status of a data cache in the NVM controller.
  • the target data includes second target data to be written to the NVM
  • the memory bus interface 94 is in the first set of data buses according to the first DQS signal.
  • Data transmission with the memory device on the second DQS signal line including: in the process of transmitting the second target data by the DQ signal line in the first group of data buses, the memory bus interface 94 is according to the The first DQS signal transmits second data on a second DQS signal line of the first set of data buses, the second data including an identification of the second target data.
  • the NVM includes at least one RANK.
  • the memory device and the memory controller of the embodiment of the present invention are described in detail above with reference to FIG. 2 to FIG. 9.
  • the data cache device of the embodiment of the present invention is described in detail below with reference to FIG. 10.
  • the data cache device is located in the memory controller and the memory. Between devices, in the process of transferring data between the memory controller and the memory device, the data buffer device may first buffer the data exchanged between the two, and after a certain signal processing (such as amplifying the signal), continue to send the data. To the opposite end, this can improve the accuracy of signal transmission. Therefore, if this type of data buffer device is provided between the memory device and the memory controller, the data buffer device also needs to adopt a signal processing method similar to that of the memory controller and the memory device to support data transfer on the DQS signal line.
  • the specific signal processing method can be referred to above, and will not be described in detail here.
  • FIG. 10 is a schematic structural diagram of a data buffer device according to an embodiment of the present invention.
  • the data cache device 100 of FIG. 10 is located between the memory controller and the memory device, and is respectively connected to the memory controller and the memory device through a DDR bus, and the memory device includes an NVM.
  • the data cache device 100 includes:
  • a memory bus interface 102 in a process in which the memory controller sends data to be written to the NVM or receives data read from the NVM from the memory device, the memory bus interface 102 receiving data transmitted on a part of the DQS signal line in the DDR bus;
  • the buffer 104 is configured to cache data received by the memory bus interface 102.
  • the DDR bus includes multiple sets of data buses, where each set of data buses includes a DQ signal line, a first DQS signal line, and a second DQS signal line, and the memory bus interface 102 is according to the first a first DQS signal transmitted on a first DQS signal line in the group data bus receives data transmitted on a DQ signal line and a second DQS signal line in each of the sets of data buses, wherein the first group of data buses is Any of a plurality of sets of data buses.
  • DB Data Buffer
  • Figure 11 shows an organization of the NVM controller in memory with DRAM and NVM.
  • the data line of the NVM controller 110 passes through the DB 111 and the memory slot 112 (the DDR 4 slot in Figure 11) As an example) connected, and then connected to the memory controller 113.
  • NVM controller 110 is coupled to NVM 114 and DRAM 115, DRAM 115 is located after NVM 114, and the data bus of DRAM 115 is coupled to NVM controller 110.
  • the DB 111 needs to cache the data exchanged between the memory controller 113 and the memory device, it is necessary to latch the data exchanged between the two. Therefore, the DB 111 also needs to support the DQS signal line. Data transmission, DB 111 signal processing can refer to Figure 7 or Figure 8.
  • Figure 12 shows another organization of the NVM controller in memory and DRAM and NVM.
  • the data bus of the DRAM 125 and the NVM controller 120 are connected to the DB 121, respectively, and the DB 121 passes through the memory slot 122 (Fig. 12
  • the DDR4 slot is for example connected to the memory controller 123, which is located after the NVM controller 120.
  • the function of the DB 121 needs to support the data transmission of the ordinary DRAM 125 as well as the data transmission of the DQS signal line.
  • FIG. 13 shows an example of the internal structure of the DB in the organization form shown in FIG. 12.
  • the DB 121 internally includes two functional interfaces: FUNC1 and FUNC2.
  • the functional interface may be a logical interface.
  • two functional interfaces may share the same set of physical interfaces. Taking x8 DRAM as an example, two functional interfaces may share eight DQ signal lines and two DQS signal lines.
  • FUNC1 can support the data transmission mode of DRAM. For example, for ⁇ 4 DRAM, each data bus includes two DQS signal lines, and the DQS signal transmitted on one DQS signal line latches data transmitted on four DQ lines; for ⁇ 8 DRAM Each group of data bus includes two DQS signal lines.
  • the DQS signal transmitted on one DQS signal line can latch the data transmitted on the eight DQ signal lines, and the other DQS signal line does not transmit the signal, and only provides the termination function.
  • FUCN2 can be a functional interface that supports DQS signal line transmission data.
  • each group of data packets includes two DQS signal lines, and one DQS signal transmitted on the DQS signal line latches data transmitted on eight DQ signal lines.
  • Another DQS signal line is also used to pass data, for example, to pass NVM related information.
  • the DB 121 also includes a control interface, which is controlled by the control interface. The command can be switched between FUNC1 and FUNC2.
  • Figure 14 is a schematic block diagram of a computer system in accordance with an embodiment of the present invention.
  • Computer system 140 of FIG. 14 includes memory device 20 depicted in FIG. 1, and memory controller 90 depicted in FIG.
  • computer system 140 may also include data cache device 100 as described in FIG.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product. Based on such understanding, the technical solution of the present invention, which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product stored in a storage medium. A number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

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Abstract

一种内存装置、内存控制器、数据缓存装置及计算机系统，该内存装置（20）包括：NVM（24）；NVM控制器（22），通过DDR总线与内存控制器相连，所述NVM控制器（22）根据所述内存控制器的命令对所述NVM（24）进行访存操作，并在所述DDR总线中的部分DQS信号线上与所述内存控制器进行数据传输。所述内存装置（20）利用DDR总线中的部分DQS信号线传输数据，解决了内存控制器和内存装置之间无法传递额外数据的问题。

Description

内存装置、内存控制器、数据缓存装置及计算机系统 技术领域
本发明涉及计算机存储领域，尤其涉及一种内存装置、内存控制器、数据缓存装置及计算机系统。
背景技术
随着技术的发展，如相变存储器(Phase Change Memory，PCM)等非易失性存储器(None Volatile Memory，NVM)的运用越来越广泛。在系统断电之后，NVM仍能保存数据，且NVM具有密度高，可扩展性好等优点，因此，NVM被认为可以替代动态随机存取存储器(Dynamic Random Access Memory，DRAM)，作为新的内存。
但是，与DRAM相比，NVM的性能还存在一些差距，难以完全兼容现有的双倍速率(Double Data Rate，DDR)标准。具体地，内存控制器一般通过DDR总线对DRAM中的数据进行访问，而数据的读写均具有一定的延时，DRAM的读延时和写延时一般为30ns左右的固定值，而PCM等NVM的读延时约为100ns，写延时约为500ns，二者相差较大，由于DDR总线的读写时序是基于DRAM的读写延时而设计的，因此，如果要将NVM运用在DDR总线上，需要解决时序兼容问题。
现有技术中，为了解决NVM与DDR总线的时序兼容问题，NVM通常不与DDR总线直接相连，而是通过NVM控制器与DDR总线相连，并通过NVM控制器内部的缓存空间暂存从NVM中读取出的数据，或者待写入NVM的数据，NVM控制器的结构可以参见图1。
由图1可以看出，无论是待写入NVM的数据，还是从NVM中读取到的数据均需要在NVM控制器内部进行调度和缓存，这样会导致数据读取和写入的延时不固定。由于读写延时不固定，NVM控制器和内存控制器之间就需要交互NVM相关的信息，以保证二者数据传输过程的准确性。例如，NVM控制器在向内存控制器发送读取到的数据时，需要通知内存控制器该读取到的数据与内存控制器发出的读请求的对应关系；又如，当NVM内部的缓存空间被占满时，NVM控制器需要通知内存控制器该内部缓存空间已满，无法继续写入数据。
因此，如何在NVM控制器和内存控制器之间传输额外的数据(如NVM相关的信息)是目前亟待解决的问题。
发明内容
本申请提供一种内存装置、内存控制器、数据缓存装置及计算机系统，以解决NVM控制器和内存控制器之间无法传输额外数据的问题。
第一方面，提供一种内存装置，所述内存装置包括：非易失性存储器NVM；NVM控制器，通过双倍速率DDR总线与内存控制器相连，所述NVM控制器根据所述内存控制器的命令对所述NVM进行访存操作，并在所述DDR总线中的部分DQS信号线上与所述内存控制器进行数据传输。
结合第一方面，在第一方面的某些实现方式中，所述DDR总线包括多组数据总线，其中每组数据总线包括DQ信号线、第一DQS信号线和第二DQS信号线，所述NVM控制器根据第一组数据总线中的第一DQS信号线上传输的第一DQS信号在所述第一组数据总线中的DQ信号线和第二DQS信号线上与所述内存控制器进行数据传输，所述第一组数据总线为所述多组数据总线中的任一组。
结合第一方面，在第一方面的某些实现方式中，所述NVM控制器根据第一组数据总线中的第一DQS信号线上传输的第一DQS信号在所述第一组数据总线中的DQ信号线和第二DQS信号线上与所述内存控制器进行数据传输，包括：所述NVM控制器根据所述第一DQS信号在所述第一组数据总线中的DQ信号线上与所述内存控制器进行目标数据的传输，所述目标数据包括待写入所述NVM的数据以及从所述NVM中读取出的数据中的至少一种；在所述第一组数据总线中的DQ信号线传输所述目标数据的过程中，所述NVM控制器根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上与所述内存控制器进行数据传输。
结合第一方面，在第一方面的某些实现方式中，所述目标数据包括从所述NVM中读取出的第一目标数据，所述NVM控制器根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上与所述内存控制器进行数据传输，包括：在所述第一组数据总线中的DQ信号线传输所述第一目标数据的过程中，所述NVM控制器根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上发送第一数据，所述第一数据包括所述第一目 标数据的标识和所述第一目标数据的内存地址中的至少一个。
结合第一方面，在第一方面的某些实现方式中，所述第一数据还包括以下信息中的至少一种：已写入所述NVM中的数据的标识；指示是否成功将数据写入所述NVM的信息；以及指示所述NVM控制器中的数据缓存的状态的信息。
结合第一方面，在第一方面的某些实现方式中，所述目标数据包括待写入所述NVM的第二目标数据，所述NVM控制器根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上与所述内存控制器进行数据传输，包括：在所述第一组数据总线中的DQ信号线传输所述第二目标数据的过程中，所述NVM控制器根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上接收第二数据，所述第二数据包括所述第二目标数据的标识。
结合第一方面，在第一方面的某些实现方式中，所述NVM包括至少一个RANK。
可选的，还可以在所述第一组数据总线的第二DQS信号线上传递数据的校验信息，如数据的纠错码(Error Correction Code，ECC)。
第二方面，提供一种内存控制器，所述内存控制器包括：调度器，用于接收处理器的访存请求；内存总线接口，通过双倍速率DDR总线与内存装置相连，所述内存总线接口根据所述访存请求，向所述内存装置发送用于访问所述内存装置中的非易失性存储器NVM的命令，并在所述DDR总线中的部分DQS信号线上与所述内存装置进行数据传输。
结合第二方面，在第二方面的某些实现方式中，所述DDR总线包括多组数据总线，其中每组数据总线包括DQ信号线、第一DQS信号线和第二DQS信号线，所述内存总线接口根据第一组数据总线中的第一DQS信号线上传输的第一DQS信号在所述第一组数据总线中的DQ信号线和第二DQS信号线上与所述内存装置进行数据传输，所述第一组数据总线为所述多组数据总线中的任一组。
结合第二方面，在第二方面的某些实现方式中，所述内存总线接口根据所述第一组数据总线中的第一DQS信号线上传输的第一DQS信号在所述第一组数据总线中的DQ信号线和第二DQS信号线上与所述内存装置进行数据传输，包括：所述内存总线接口根据所述第一DQS信号在所述第一组数 据总线中的DQ信号线上与所述内存装置进行目标数据的传输，所述目标数据包括待写入所述NVM的数据以及从所述NVM中读取出的数据中的至少一种；在所述第一组数据总线中的DQ信号线传输所述目标数据的过程中，所述内存总线接口根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上与所述内存装置进行数据传输。
结合第二方面，在第二方面的某些实现方式中，所述目标数据包括从所述NVM中读取出的第一目标数据，所述内存总线接口根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上与所述内存装置进行数据传输，包括：在所述第一组数据总线中的DQ信号线传输所述第一目标数据的过程中，所述内存总线接口根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上接收第一数据，所述第一数据包括所述第一目标数据的标识和所述第一目标数据的内存地址中的至少一个。
结合第二方面，在第二方面的某些实现方式中，所述第一数据还包括以下信息中的至少一种：已写入所述NVM中的数据的标识；指示是否成功将数据写入所述NVM的信息；以及指示所述NVM控制器中的数据缓存的状态的信息。
结合第二方面，在第二方面的某些实现方式中，所述目标数据包括待写入所述NVM的第二目标数据，所述内存总线接口根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上与所述内存装置进行数据传输，包括：在所述第一组数据总线中的DQ信号线传输所述第二目标数据的过程中，所述内存总线接口根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上发送第二数据，所述第二数据包括所述第二目标数据的标识。
可选的，在内存控制器访问内存装置的过程中，内存总线接口可以确定待访问的存储单元的类型，在确定待访问的存储单元为DRAM的情况下，内存总线接口选择DRAM对应的功能接口访问DRAM。在确定待访问的存储单元为NVM的情况下，内存总线接口选择NVM对应的功能接口访问NVM。其中，功能接口可以是逻辑上的接口。实际中，两个功能接口可以共享同一组物理接口。
结合第二方面，在第二方面的某些实现方式中，所述NVM包括至少一个RANK。第三方面，提供一种数据缓存装置，所述数据缓存装置位于内存 控制器和内存装置之间，并通过双倍速率DDR总线分别与所述内存控制器和所述内存装置相连，所述内存装置包括非易失性存储器NVM，所述数据缓存装置包括：内存总线接口，在所述内存控制器向所述内存装置发送待写入所述NVM的数据或从所述内存装置接收从所述NVM读取到的数据的过程中，所述内存总线接口接收所述DDR总线中的部分DQS信号线上传输的数据；缓存器，用于缓存所述内存总线接口接收到的数据。
结合第三方面，在第三方面的某些实现方式中，所述DDR总线包括多组数据总线，其中每组数据总线包括DQ信号线、第一DQS信号线和第二DQS信号线，所述内存总线接口根据第一组数据总线中的第一DQS信号线上传输的第一DQS信号，接收所述第一组数据总线中的DQ信号线和第二DQS信号线上传输的数据，所述第一组数据总线为所述多组数据总线中的任一组。
第四方面，提供一种计算机系统，包括如第一方面或第一方面中的任一种实现方式所述的内存装置，以及第二方面或第二方面的任一种实现方式所述的内存控制器。
结合第四方面，在第四方面的某些实现方式中，所述计算机系统还包括如第三方面或第三方面的任一种实现方式所述的数据缓存装置。
现有技术中，DQS信号线上的DQS信号用来锁存DQ信号线上的数据，本申请利用DDR总线中的部分DQS信号线传输数据，解决了内存控制器和内存装置之间无法传递额外数据的问题。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对本发明实施例中所需要使用的附图作简单地介绍，显而易见地，下面所描述的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是内存控制器与基于NVM的内存装置的连接关系示意图。
图2是本发明实施例提供的内存装置的示意性结构图。
图3是×4DRAM和×8DRAM共享DDR总线的示意图。
图4是×4DRAM的读写时序图。
图5是×8DRAM的读写时序图。
图6是本发明实施例提供的×4DRAM与×8NVM共享DDR总线的示意图。
图7是本发明一个实施例提供的×8NVM的读写时序图。
图8是本发明另一实施例提供的×8NVM的读写时序图。
图9是本发明实施例的内存控制器的示意性结构图。
图10是本发明实施例的数据缓存装置的示意性结构图。
图11是本发明一个实施例提供的包含DRAM和NVM的内存的架构图。
图12是本发明另一实施例提供的包含DRAM和NVM的内存的架构图。
图13是本发明又一实施例提供的包含DRAM和NVM的内存的架构图。
图14是本发明实施例的计算机系统的示意性结构图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。
内存控制器和内存装置之间一般通过DDR总线相连，为了便于理解，先对DDR总线进行简单介绍。DDR总线包括地址总线(address bus)、命令总线(Command bus)和数据总线(data bus)。DDR总线中的数据总线包括双向数据锁存(Bi-directional Data Strobe，DQS)信号线和DQ信号线。在传统的基于DRAM的内存装置中，内存控制器和内存装置基于DQS信号线上传输的DQS信号，在DQ信号线上进行数据传输。以写数据为例，内存控制器分别通过DQS信号线和DQ信号线向内存装置发送DQS信号和待写入数据，内存装置会基于接收到的DQS信号锁存(或称采样)DQ信号线上传输的待写入数据。同理，在数据读取过程中，内存装置分别通过DQS信号线和DQ信号线向内存控制器发送DQS信号和读取出的数据，内存控制器会基于DQS信号锁存DQ信号线上传输的已读出的数据。总之，在现有技术中，DQ信号线上传输的是数据(也可称为DQ信号)，而DQS信号线上传输的DQS信号主要用于实现内存控制器和内存装置之间的时钟同步，DQS信号相当于一种时钟同步信号。
需要说明的是，一条DQS信号线是指逻辑上能够形成DQS信号的线，实际中，一种情况下，DQS信号可以通过一根物理的DQS线进行传输。在 这种情况下，一条DQS信号线对应一根物理的DQS线。另一种情况下，当DQS信号为差分信号时，DQS信号需要通过两根物理的DQS线进行传输。在这种情况下，一条DQS信号线对应两根物理的DQS线。
下面结合图2，详细描述本发明实施例的内存装置。图2是本发明实施例提供的内存装置。内存装置20包括：
NVM 24，该NVM 24可以包括至少一个NVM芯片，例如，NVM 24可以是一个NVM RANK，或者，NVM 24可以是NVM DIMM。
NVM控制器22，通过DDR总线与内存控制器相连，NVM控制器22根据内存控制器的命令对NVM 24进行访存操作，并在DDR总线中的部分DQS信号线上与内存控制器进行数据传输。
需要说明的是，用于传输数据的部分DQS信号线的选取方式可以有多种，下面结合具体的实施例进行详细描述。
首先，可以基于现有的DDR总线的分组设计方式，从DDR总线的一组数据总线中选取用于传递数据信号的DQS信号线，为了便于理解，先介绍一下现有的DDR总线的分组设计方式。
DDR总线中的数据总线包括多条DQS信号线和多条DQ信号线，实际中，为了使不同位宽的DRAM可以在同一DDR总线上工作，一般会对DDR数据总线进行分组设计。以兼容×4DRAM(即DRAM芯片的位宽为4位)和×8DRAM(即DRAM芯片的位宽为8位)的DDR总线为例，在标准的双列直插式存储模块(Dual Inline Memory Modules，DIMM)的设计中，通常一组DDR数据总线包括8个DQ信号线和2个DQS信号线，这些信号线在电路板上做等长设计，这样一来，无论是接×4DRAM还是接×8DRAM，DDR总线都可以正常工作。下面结合图3-图5，详细描述兼容×4DRAM和×8DRAM的DDR总线的工作方式。
图3是×4DRAM和×8DRAM共享DDR总线的示意图。图3共示出2个DIMM，其中，DIMM 0内部的DRAM芯片为×4DRAM，DIMM 1内部的DRAM芯片为×8DRAM。进一步地，图3示出了DDR总线中的一组数据总线，这组数据总线共包括8条DQ信号线(图3中的DQ[0:7])和2条DQS信号线(图3中的DQS[0]和DQS[1])。应理解，为了描述方便，图3仅示出了DDR总线中的一组数据总线，实际中，DDR总线可以包括多组数据总线，例如，对于支持纠错码(Error Correction Code，ECC)的DIMM 而言，DDR数据总线一般包括72条DQ信号线和18条DQS信号线，这些数据总线共分为9组数据总线，每组数据总线包括8条DQ信号线和2条DQS信号线；对于不支持ECC的DIMM而言，DDR数据总线一般包括64条DQ信号线和16条DQS信号线，这些数据总线共分为8组数据总线，每组数据总线包括8条DQ信号线和2条DQS信号线。
对于DIMM 0而言，由于其内部的存储芯片为×4DRAM，一条DQS信号线需要锁存4条DQ信号线，因此，DQS[0]和DQS[1]均用于传输DQS信号，其中，DQS[0]上传输的DQS信号用于锁存DQ[0:3]上传输的数据，DQS[1]上传输的DQS信号用于锁存DQ[4:7]上传输的数据，×4DRAM的具体读写时序参见图4。
对于DIMM 1而言，由于其内部的存储芯片为×8DRAM，一条DQS信号线需要锁存8条DQ信号线，因此，DQS[0]和DQS[1]中的任意一条DQS信号线就能够完成DQ[0:7]的锁存，另一条DQS信号线没有实际的信号功能。×8DRAM的具体读写时序参见图5，图5与图4的区别在于图5中，DQS[0]完成了一组DQS数据总线中的所有DQ线的锁存，而DQS[1]负责与DIMM 1的TDQS管脚端接，无需传递DQS信号。
由图5可以看出，分组设计带来的结果是在某些情况下，一组数据总线中的某些DQS信号线无需传递DQS信号，仅提供端接功能，如图5中的与DIMM 1的TDQS管脚相连的DQS[1]。
需要说明的是，以上仅是以×4DRAM和×8DRAM共享DDR总线为例对DDR数据总线的分组设计方式进行描述，本发明实施例不限于此，其他不同位宽的DRAM共享DDR总线的分组设计方式类似，此处不再详述。总之，不同位宽的DRAM共享DDR总线时，DDR总线中的每组数据总线包括多条DQS信号线，当不同位宽的DRAM中的较高位宽的DRAM与DDR总线相连时，该多条DQS信号线中就会出现不传输DQS信号、仅提供端接的DQS信号线。
在DDR总线的分组设计的基础上，可以按照如下方式选取用于传输数据的DQS信号线。
可选地，作为一个实施例，DDR总线包括多组数据总线，其中每组数据总线包括DQ信号线、第一DQS信号线和第二DQS信号线，NVM控制器根据第一组数据总线中的第一DQS信号线上传输的第一DQS信号在第一 组数据总线中的DQ信号线和第二DQS信号线上与内存控制器进行数据传输，其中，所述第一组数据总线为多组数据总线中的任一组。进一步地，在一些实施例中，多组数据总线中的每组数据总线均可以按照与第一组数据总线相同的方式选取用于传输数据的DQS信号线。
现有技术中，DQS信号线上的DQS信号用来锁存DQ信号线上的数据，本发明实施例利用DDR总线中的部分DQS信号线传输数据，解决了内存控制器和内存装置之间无法传递额外数据的问题。例如，可以在内存控制器和内存装置之间传递NVM相关的信息，以保证NVM控制器和内存控制器之间信息交互的准确性。
进一步地，NVM控制器基于第一DQS信号在第一组数据总线中的DQ信号线上传输数据。假设DDR总线是为了兼容第一位宽的DRAM和第二位宽的DRAM而设计的，其中，第二位宽大于第一位宽，本发明实施例相当于利用NVM控制器模拟第二位宽的DRAM芯片的工作方式，通过一条DQS信号线锁存第一组数据总线中的DQ信号线上传输的数据，这样就会出现无需传递DQS信号的DQS信号线，可以选取这种类型的DQS信号线传输额外数据，从而为NVM控制器与内存控制器之间交互NVM相关的信息提供可能。
以第一位宽为4位，第二位宽为8位为例，NVM通过NVM控制器可以模拟×8DRAM(下面将这种NVM称为×8NVM)，这样一来，NVM控制器与内存控制器交互数据的过程中，DDR总线中的每组数据总线会出现无需传递DQS信号的一条DQS信号线，图6是×4DRAM与×8NVM共享DDR总线的示意图，这条现无需传递DQS信号的DQS信号线即为图6中的与TDQS管脚相连的DQS1。
假设DDR总线的分组是为了兼容×4DRAM和×8DRAM而设计的，在支持ECC的情况下，DDR数据总线可以包括72条DQ信号线和18条DQS信号线，这些数据总线共分为9组，每组包括8条DQ信号线和2条DQS信号线，第一组数据总线可以是9组中的任一组，第一DQS信号线可以是第一组数据总线中的2条DQS信号线中的任意一条(另一条即为第二DQS信号线)，第一DQS信号线上传输第一DQS信号，NVM控制器可以根据第一DQS信号锁存第一组数据总线中的其他8条DQ信号线上传输的数据，并锁存第二DQS信号线上传输的数据。在另一些实施例中，在不支持ECC 的情况下，DDR数据总线可以包括64条DQ信号线和16条DQS信号线，这些数据总线共分为8组，每组包括8条DQ信号线和2条DQS信号线，第一组数据总线可以是8组中的任一组，第一DQS信号线可以是第一组数据总线中的2条DQS信号线中的任意一条(另一条即为第二数据总线)，第一DQS信号线上传输第一DQS信号，NVM控制器可以根据第一DQS信号，锁存第一组数据总线中的其他8条DQ信号线上传输的数据，并锁存第二DQS信号线上传输的数据。
可选地，作为一个实施例，NVM控制器根据第一DQS信号在第一组数据总线中的DQ信号线和第二DQS信号线上与内存控制器进行数据传输，包括：NVM控制器根据第一DQS信号在第一组数据总线中的DQ信号线上与内存控制器进行目标数据的传输，目标数据包括待写入NVM的数据以及从NVM中读取出的数据中的至少一种；在第一组数据总线中的DQ信号线传输目标数据的过程中，NVM控制器根据第一DQS信号在第一组数据总线中的第二DQS信号线上与内存控制器进行数据传输。
现有技术中，内存中的RANK共享DDR总线，各个RANK对DDR总线进行时分复用，不会相互影响，当一个RANK传递数据时，其他RANK的数据总线处于端接状态，不传递信号。
本发明实施例利用了RANK之间时分复用DDR数据总线的特性，规定第一组数据总线中的第二DQS信号线在第一组数据总线的DQ信号线传输目标数据的过程中传输数据。基于DDR数据总线的时分复用特性，第一组数据总线的DQ信号线传输目标数据的过程中，第二DQS信号线被NVM占用，第二DQS信号线上的数据传输不会对其他内存或其他RANK的数据传输造成影响。
下面结合图7，以能够同时连接×4DRAM和×8DRAM的DDR总线为例进行详细说明。图7示出了NVM控制器模拟×8DRAM进行数据读写的流程。具体地，在写场景中，NVM控制器在接收到激活命令(ACT)和写命令(WR)之后，按照tWL参数指示的写延时，将数据写入NVM控制器的缓存空间中。在写入数据前，需要先从DQS[0]上获取DQS信号，并在tWPRE参数指示的时间间隔之后，开始锁存DQ[0:7]上传输的数据，并在tRPST参数指示的时间间隔之后，停止锁存DQ[0:7]上传输的数据；在读场景中，内存控制器发送激活命令和读命令之后，受到NVM介质的性能的限 制，无法按照DRAM的时序读取数据，当NVM控制器获知有数据从NVM读取到NVM控制器的缓存空间之后，NVM控制器会通过某些管脚通知内存控制器读取数据，接着，内存控制器会向NVM控制器发送TB命令(读命令和TB命令之间的延时是非固定延时，这是由NVM介质本身特性决定的)，NVM收到该命令之后，按照tRL参数指示的读延时，将数据放到DQ[0:7]上，在将数据放到DQ[0:7]之前，需要先通过DQS[0]向内存控制器发送DQS信号，这样一来，内存控制器接收到DQS信号之后，就会在tRPRE参数指示的时间间隔之后，开始锁存DQ[0:7]上传输的数据，并在tRPST参数指示的时间间隔之后，停止锁存DQ[0:7]上传输的数据。从图7可以看出，在基于DQS[0]锁存DQ[0:7]上传输的数据的过程中，DQS[1]上也同时传递数据，如传递NVM相关的信息，由于每组数据总线包括8条DQ信号线和2条DQS信号线，每通过DQ信号线传递64Byte的数据，就可以利用DQS[1]传递额外的9Byte数据，为NVM相关信息的传递提供了充分的支持。
需要说明的是，本发明实施例中，在第一组数据总线的第二DQS信号线上传递数据时，第一组数据总线的第二DQS信号线上的数据信号可以与第一组数据总线的第一DQS信号线上的DQS信号相位相同，也可以与第一组数据总线的DQ信号线上的信号相位相同。以×8NVM为例，图7为第一组数据总线的第二DQS信号线上的数据信号与每组数据总线的DQ信号线上的信号同相位的示例；图8为第一组数据总线的第二DQS信号线上的数据信号与第一组数据总线的第一DQS信号线上的DQS信号同相位的示例。
本发明实施例对第一组数据总线中的第二DQS信号线上传输的数据类型不做具体限定，实际中，可以根据第一组数据总线中的DQ信号线上传输的目标数据的类型而选择，下面结合具体的实施例进行详细描述。
可选地，在一些实施例中，目标数据包括从NVM中读取出的第一目标数据，NVM控制器根据第一DQS信号在第一组数据总线中的第二DQS信号线上与内存控制器进行数据传输，包括：在第一组数据总线中的DQ信号线传输第一目标数据的过程中，NVM控制器根据第一DQS信号在第一组数据总线中的第二DQS信号线上发送第一数据，第一数据包括第一目标数据的标识和第一目标数据的内存地址中的至少一个。第一目标数据的标识可用于指示该第一目标数据为哪个读请求对应的数据；此外，第一目标数据的标识可以与第一目标数据的读请求的读地址相对应。
进一步地，第一数据还包括以下信息中的至少一种：已写入NVM中的数据的标识；指示是否成功将数据写入NVM的信息；以及指示NVM控制器中的数据缓存的状态的信息。
可选地，在一些实施例中，目标数据包括待写入NVM的第二目标数据，NVM控制器根据第一DQS信号在第一组数据总线中的第二DQS信号线上与内存控制器进行数据传输，包括：在第一组数据总线中的DQ信号线传输第二目标数据的过程中，NVM控制器根据第一DQS信号在第一组数据总线中的第二DQS信号线上接收第二数据，第二数据包括第二目标数据的标识。第二目标数据的标识可用于指示该第二目标数据为哪个写请求对应的数据；此外，第二目标数据的标识可以与第二目标数据的写请求的写地址相对应。
进一步地，还可以在第一组数据总线的第二DQS信号线上传递数据的校验信息，如ECC。
本申请中，可以将用于传输数据的DQS信号线称为NM总线(即NVM Message Bus)，NM总线上的数据可以称为NM包，对于写场景，NM包可以包含待写入数据的标识WID(Write ID)。对于读场景，可以为待读取的数据设置RID(Read ID，即待读取的数据的标识)，并通过NM包返回读取到的数据的RID。或者，可以不为待读取的数据设置RID，直接通过NM包返回读取到的数据的地址。
进一步地，如果需要确认数据是否写入NVM中(即进行写完成确认)，那么可以在NM包中承载已经写入NVM的数据的WID，以及该WID是否有效、是否出错等状态信息。
进一步地，无论是读场景，还是写场景，NM包均可包含ECC位，用来保护传输的数据的正确性。
下面以DDR 4为例进行说明，在DDR 4中，DDR 4的具有ECC功能的DIMM具有连接18条DQS信号线(每条DQS信号线包括两条差分信号线)的管脚，其中的9条DQS信号线可用作为NM总线，它们之间的对应关系如表一所示：
表一：DQS信号线与NM总线的对应关系
DDR 4的DIMM管脚 NM总线
DQS1#/DQS1 NM[0]
DQS3#/DQS3 NM[1]
DQS5#/DQS5 NM[2]
DQS7#/DQS7 NM[3]
DQS9#/DQS9 NM[4]
DQS11#/DQS11 NM[5]
DQS13#/DQS13 NM[6]
DQS15#/DQS15 NM[7]
DQS17#/DQS17 NM[8]
针对写场景，NM[0:8]可以按照表二所示的方式携带NVM相关的信息。
表二：针对写场景的NM包的定义方式
Figure PCTCN2016097130-appb-000001
如表二所示，一个时钟(clock)可以包括2个节拍(beat)，每个节拍可以传输不同的信息。对于写场景，NM总线可以用来传输待写入数据的标识(WID)，还可以传输用于校验NM包(本次传输的NM包)的ECC字段。表二中的RFU(Reserved For Future Use)为保留字段。
针对读场景，NM[0:8]可以按照表三所示的方式携带NVM相关的信息。
表三：针对读场景的NM包的定义方式
Figure PCTCN2016097130-appb-000002
Figure PCTCN2016097130-appb-000003
表三中，RID为读取到的数据的标识，R-ADDR为读取到的数据的地址，二者可以同时传递，也可以仅传输其中之一。例如，内存控制器读取数据时，如果读请求中嵌入了待读取数据的RID(或者，内存控制器与NVM控制器通过如同步计数等其他方式指示了待读取数据的RID)，NVM控制器从NVM中获取到数据之后，可以在NM包中携带该数据的RID，以便内存控制器基于该RID获知该数据对应哪个读请求。又如，内存控制器读取数据时，如果NVM无法获取到读请求对应的RID，NVM控制器从NVM中获取到数据之后，可以在NM包中携带该数据的内存地址，以便内存控制器基于该内存地址获知该数据对应哪个读请求。此外，在一些实施例中，可以通过NM包返回已写入NVM的数据的标识WID，相当于对写入NVM的数据进行确认，表三中的Valid可以指示返回的WID是否为有效的WID，STAU可以占用1位或者多位，指示数据是否成功写入NVM，或者指示数据写入过程发生错误。进一步地，在一些实施例中，可以在表3中增加WC/PWC(write credit increase/persistent write credit increase)字段，以表示NVM控制器内的写缓存空间的剩余容量(或空闲容量)等，内存控制器可以基于该剩余容量确定 是否写入新的数据。
上文结合图2至图8，详细描述了本发明实施例的内存装置，下文结合图9，详细描述本发明实施例的内存控制器，应理解，内存控制器与内存装置之间的信号处理方式类似，为了简洁，此处不再详述。
图9是本发明实施例的内存控制器的示意性结构图。图9的内存控制器90包括：
调度器92，用于接收处理器的访存请求；
内存总线接口94，通过双倍速率DDR总线与内存装置相连，所述内存总线接口94根据所述访存请求，向所述内存装置发送用于访问所述内存装置中的非易失性存储器NVM的命令，并在所述DDR总线中的部分DQS信号线上与所述内存装置进行数据传输。
现有技术中，DQS信号线用来锁存DQ信号线上的数据，本发明实施例利用DDR总线中的部分DQS信号线传输数据，解决了内存控制器和内存装置之间无法传递额外数据的问题。例如，可以在内存控制器和内存装置之间传递NVM相关的信息，以保证NVM控制器和内存控制器之间信息交互的准确性。
可选地，在一些实施例中，内存总线接口94可以确定待访问的存储单元的类型，在所述存储单元为DRAM的情况下，内存总线接口94选择DRAM对应的功能接口访问DRAM，在所述存储单元为NVM的情况下，内存总线接口94选择NVM对应的功能接口访问NVM。上述存储单元例如可以是RANK。
内存总线接口94确定待访问的存储单元的类型的方式可以有多种，例如，在DIMM标准中，DIMM具有串行存在检查电可擦可编程只读存储器(Serial Presence Detect Electrically Erasable Programmable Read-Only Memory，SPD EEPROM)，该EEPROM可以通过DDR地址/数据/命令总线之外的串行接口访问，可以在该EEPROM中存储存储单元的类型信息(如RANK的类型信息)，内存总线接口94可以通过访问该EEPROM获知存储单元的类型。
内存总线接口94可以包括两个功能接口：FUNC1和FUNC2。应理解，功能接口可以是逻辑上的接口，实际中，两个功能接口可以共享同一组物理接口，以×8DRAM为例，两个功能接口可以共享8条DQ信号线和2条 DQS信号线。FUNC1可以支持DRAM的数据传输方式，例如，对于×4DRAM，每组数据总线包括2条DQS信号线，1条DQS信号线上传输的DQS信号锁存4条DQ线上传输的数据；对于×8DRAM，每组数据总线包括2条DQS信号线，1条DQS信号线上传输的DQS信号可以锁存8条DQ信号线上传输的数据，另1条DQS信号线不传递信号，仅提供端接功能。FUCN2可以是支持DQS信号线传递数据的功能接口，对于×8NVM，每组数据包包括2条DQS信号线，1条DQS信号线上传输的DQS信号锁存8条DQ信号线上传输的数据，另1条DQS信号线也用于传递数据，例如，传递NVM相关的信息。
可选地，在一些实施例中，所述DDR总线包括多组数据总线，其中每组数据总线包括DQ信号线、第一DQS信号线和第二DQS信号线，所述内存总线接口94根据所述第一组数据总线中的第一DQS信号线上传输的第一DQS信号在所述第一组数据总线中的DQ信号线和第二DQS信号线上与所述内存装置进行数据传输。
可选地，在一些实施例中，所述内存总线接口94根据所述第一DQS信号在所述第一组数据总线中的DQ信号线和第二DQS信号线上与所述内存装置进行数据传输，包括：所述内存总线接口94根据所述第一DQS信号在所述第一组数据总线中的DQ信号线上与所述内存装置进行目标数据的传输，所述目标数据包括待写入所述NVM的数据以及从所述NVM中读取出的数据中的至少一种；在所述第一组数据总线中的DQ信号线传输所述目标数据的过程中，所述内存总线接口94根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上与所述内存装置进行数据传输。
可选地，在一些实施例中，所述目标数据包括从所述NVM中读取出的第一目标数据，所述内存总线接口94根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上与所述内存装置进行数据传输，包括：在所述第一组数据总线中的DQ信号线传输所述第一目标数据的过程中，所述内存总线接口94根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上接收第一数据，所述第一数据包括所述第一目标数据的标识和所述第一目标数据的内存地址中的至少一个。
可选地，在一些实施例中，所述第一数据还包括以下信息中的至少一种：已写入所述NVM中的数据的标识；指示是否成功将数据写入所述NVM的 信息；以及指示所述NVM控制器中的数据缓存的状态的信息。
可选地，在一些实施例中，所述目标数据包括待写入所述NVM的第二目标数据，所述内存总线接口94根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上与所述内存装置进行数据传输，包括：在所述第一组数据总线中的DQ信号线传输所述第二目标数据的过程中，所述内存总线接口94根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上发送第二数据，所述第二数据包括所述第二目标数据的标识。
可选地，在一些实施例中，所述NVM包括至少一个RANK。
上文结合图2至图9，详细描述了本发明实施例的内存装置和内存控制器，下文结合图10，详细描述本发明实施例的数据缓存装置，该数据缓存装置位于内存控制器和内存装置之间，在内存控制器与内存装置传输数据的过程中，数据缓存装置可以将二者之间交互的数据先缓存下来，经过一定的信号处理(如对信号进行放大处理)，再继续发送至对端，这样可以提高信号传递的准确性。因此，如果内存装置和内存控制器之间设置了这种类型的数据缓存装置，该数据缓存装置也需要采用与内存控制器和内存装置类似的信号处理方式，以支持在DQS信号线上传递数据，具体的信号处理方式可以参见上文，此处不再详述。
图10是本发明实施例的数据缓存装置的示意性结构图。图10的数据缓存装置100位于内存控制器和内存装置之间，并通过DDR总线分别与所述内存控制器和所述内存装置相连，所述内存装置包括NVM，
所述数据缓存装置100包括：
内存总线接口102，在所述内存控制器向所述内存装置发送待写入所述NVM的数据或从所述内存装置接收从所述NVM读取到的数据的过程中，所述内存总线接口102接收所述DDR总线中的部分DQS信号线上传输的数据；
缓存器104，用于缓存所述内存总线接口102接收到的数据。
可选地，作为一个实施例，所述DDR总线包括多组数据总线，其中每组数据总线包括DQ信号线、第一DQS信号线和第二DQS信号线，所述内存总线接口102根据第一组数据总线中的第一DQS信号线上传输的第一DQS信号，接收所述每组数据总线中的DQ信号线和第二DQS信号线上传输的数据，所述第一组数据总线为所述多组数据总线中的任一组。
有些内存既包含NVM，又包含DRAM，而且NVM和DRAM在内存中的组织形式可以有多种，针对不同类型的组织形式，数据缓存装置(下文简称DB(Data Buffer))的具体实现方式也可以有所不同，下面结合图11至图13进行详细描述。
图11示出了内存中的NVM控制器与DRAM和NVM的一种组织形式，在图11中，NVM控制器110的数据线通过DB 111和内存插槽112(图11中以DDR 4插槽为例)相连，然后连接到内存控制器113。NVM控制器110和NVM 114和DRAM 115相连，DRAM 115位于NVM 114之后，且DRAM 115的数据总线和NVM控制器110相连。在这种组织形式中，由于DB 111需要缓存内存控制器113和内存装置之间交互的数据，就需要对二者之间交互的数据进行锁存，因此，DB 111也需要支持DQS信号线的数据传输，DB 111信号处理方式可以参考图7或图8。
图12示出了内存中的NVM控制器与DRAM和NVM的另一种组织形式，DRAM 125和NVM控制器120的数据总线分别接DB 121，DB 121再通过内存插槽122(图12中以DDR4插槽为例)连接至内存控制器123，NVM 124位于NVM控制器120之后。对于这种组织形式，DB 121的功能既需要支持普通的DRAM 125的数据传输，也需要支持DQS信号线传输数据。
图13示出了图12所示的组织形式下的DB的内部结构的一种示例，从图13可以看出，DB 121内部包括两个功能接口：FUNC1和FUNC2。应理解，功能接口可以是逻辑上的接口，实际中，两个功能接口可以共享同一组物理接口，以×8DRAM为例，两个功能接口可以共享8条DQ信号线和2条DQS信号线。FUNC1可以支持DRAM的数据传输方式，例如，对于×4DRAM，每组数据总线包括2条DQS信号线，1条DQS信号线上传输的DQS信号锁存4条DQ线上传输的数据；对于×8DRAM，每组数据总线包括2条DQS信号线，1条DQS信号线上传输的DQS信号可以锁存8条DQ信号线上传输的数据，另1条DQS信号线不传递信号，仅提供端接功能。FUCN2可以是支持DQS信号线传递数据的功能接口，对于×8NVM，每组数据包包括2条DQS信号线，1条DQS信号线上传输的DQS信号锁存8条DQ信号线上传输的数据，另1条DQS信号线也用于传递数据，例如，传递NVM相关的信息。此外，DB 121还包括一个控制接口，通过控制接口输入的控 制命令，DB 121可以在FUNC1和FUNC2之间进行切换。
图14是本发明实施例的计算机系统的示意性结构图。图14的计算机系统140包括图1描述的内存装置20，以及图9描述的内存控制器90。
可选地，在一些实施例中，计算机系统140还可以包括图10描述的数据缓存装置100。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质 中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。

Claims (18)

  1. 一种内存装置，其特征在于，所述内存装置包括：
    非易失性存储器NVM；
    NVM控制器，通过双倍速率DDR总线与内存控制器相连，所述NVM控制器根据所述内存控制器的命令对所述NVM进行访存操作，并在所述DDR总线中的部分DQS信号线上与所述内存控制器进行数据传输。
  2. 如权利要求1所述的内存装置，其特征在于，所述DDR总线包括多组数据总线，每组数据总线包括DQ信号线、第一DQS信号线和第二DQS信号线，所述NVM控制器根据第一组数据总线中的第一DQS信号线上传输的第一DQS信号在所述第一组数据总线中的DQ信号线和第二DQS信号线上与所述内存控制器进行数据传输，所述第一组数据总线为所述多组数据总线中的任一组。
  3. 如权利要求2所述的内存装置，其特征在于，所述NVM控制器根据第一组数据总线中的第一DQS信号线上传输的第一DQS信号在所述第一组数据总线中的DQ信号线和第二DQS信号线上与所述内存控制器进行数据传输，包括：
    所述NVM控制器根据所述第一DQS信号在所述第一组数据总线中的DQ信号线上与所述内存控制器进行目标数据的传输，所述目标数据包括待写入所述NVM的数据以及从所述NVM中读取出的数据中的至少一种；
    在所述第一组数据总线中的DQ信号线传输所述目标数据的过程中，所述NVM控制器根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上与所述内存控制器进行数据传输。
  4. 如权利要求3所述的内存装置，其特征在于，所述目标数据包括从所述NVM中读取出的第一目标数据，
    所述NVM控制器根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上与所述内存控制器进行数据传输，包括：
    在所述第一组数据总线中的DQ信号线传输所述第一目标数据的过程中，所述NVM控制器根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上发送第一数据，所述第一数据包括所述第一目标数据的标识和所述第一目标数据的内存地址中的至少一个。
  5. 如权利要求4所述的内存装置，其特征在于，所述第一数据还包括以下信息中的至少一种：
    已写入所述NVM中的数据的标识；
    指示是否成功将数据写入所述NVM的信息；以及
    指示所述NVM控制器中的数据缓存的状态的信息。
  6. 如权利要求3-5中任一项所述的内存装置，其特征在于，所述目标数据包括待写入所述NVM的第二目标数据，
    所述NVM控制器根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上与所述内存控制器进行数据传输，包括：
    在所述第一组数据总线中的DQ信号线传输所述第二目标数据的过程中，所述NVM控制器根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上接收第二数据，所述第二数据包括所述第二目标数据的标识。
  7. 如权利要求1-6中任一项所述的内存装置，其特征在于，所述NVM包括至少一个RANK。
  8. 一种内存控制器，其特征在于，所述内存控制器包括：
    调度器，用于接收处理器的访存请求；
    内存总线接口，通过双倍速率DDR总线与内存装置相连，所述内存总线接口根据所述访存请求，向所述内存装置发送用于访问所述内存装置中的非易失性存储器NVM的命令，并在所述DDR总线中的部分DQS信号线上与所述内存装置进行数据传输。
  9. 如权利要求8所述的内存控制器，其特征在于，所述DDR总线包括多组数据总线，其中每组数据总线包括DQ信号线、第一DQS信号线和第二DQS信号线，所述内存总线接口根据第一组数据总线中的第一DQS信号线上传输的第一DQS信号在所述第一组数据总线中的DQ信号线和第二DQS信号线上与所述内存装置进行数据传输，所述第一组数据总线为所述多组数据总线中的任一组。
  10. 如权利要求9所述的内存控制器，其特征在于，所述内存总线接口根据所述第一组数据总线中的第一DQS信号线上传输的第一DQS信号在所述第一组数据总线中的DQ信号线和第二DQS信号线上与所述内存装置进行数据传输，包括：
    所述内存总线接口根据所述第一DQS信号在所述第一组数据总线中的DQ信号线上与所述内存装置进行目标数据的传输，所述目标数据包括待写入所述NVM的数据以及从所述NVM中读取出的数据中的至少一种；
    在所述第一组数据总线中的DQ信号线传输所述目标数据的过程中，所述内存总线接口根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上与所述内存装置进行数据传输。
  11. 如权利要求10所述的内存控制器，其特征在于，所述目标数据包括从所述NVM中读取出的第一目标数据，
    所述内存总线接口根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上与所述内存装置进行数据传输，包括：
    在所述第一组数据总线中的DQ信号线传输所述第一目标数据的过程中，所述内存总线接口根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上接收第一数据，所述第一数据包括所述第一目标数据的标识和所述第一目标数据的内存地址中的至少一个。
  12. 如权利要求11所述的内存控制器，其特征在于，所述第一数据还包括以下信息中的至少一种：
    已写入所述NVM中的数据的标识；
    指示是否成功将数据写入所述NVM的信息；以及
    指示所述NVM控制器中的数据缓存的状态的信息。
  13. 如权利要求10-12中任一项所述的内存控制器，其特征在于，所述目标数据包括待写入所述NVM的第二目标数据，
    所述内存总线接口根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上与所述内存装置进行数据传输，包括：
    在所述第一组数据总线中的DQ信号线传输所述第二目标数据的过程中，所述内存总线接口根据所述第一DQS信号在所述第一组数据总线中的第二DQS信号线上发送第二数据，所述第二数据包括所述第二目标数据的标识。
  14. 如权利要求8-13中任一项所述的内存控制器，其特征在于，所述NVM包括至少一个RANK。
  15. 一种数据缓存装置，其特征在于，所述数据缓存装置位于内存控制器和内存装置之间，并通过双倍速率DDR总线分别与所述内存控制器和所 述内存装置相连，所述内存装置包括非易失性存储器NVM，
    所述数据缓存装置包括：
    内存总线接口，在所述内存控制器向所述内存装置发送待写入所述NVM的数据或从所述内存装置接收从所述NVM读取到的数据的过程中，所述内存总线接口接收所述DDR总线中的部分DQS信号线上传输的数据；
    缓存器，用于缓存所述内存总线接口接收到的数据。
  16. 如权利要求15所述的数据缓存装置，其特征在于，所述DDR总线包括多组数据总线，其中每组数据总线包括DQ信号线、第一DQS信号线和第二DQS信号线，所述内存总线接口根据第一组数据总线中的第一DQS信号线上传输的第一DQS信号，接收所述第一组数据总线中的DQ信号线和第二DQS信号线上传输的数据，所述第一组数据总线为所述多组数据总线中的任一组。
  17. 一种计算机系统，其特征在于，包括如权利要求1-7中任一项所述的内存装置，以及如权利要求8-14中任一项所述的内存控制器。
  18. 如权利要求17所述的计算机系统，其特征在于，所述计算机系统还包括如权利要求15或16所述的数据缓存装置。
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