TWI628508B - 形成圖案的方法 - Google Patents
形成圖案的方法 Download PDFInfo
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- TWI628508B TWI628508B TW105107708A TW105107708A TWI628508B TW I628508 B TWI628508 B TW I628508B TW 105107708 A TW105107708 A TW 105107708A TW 105107708 A TW105107708 A TW 105107708A TW I628508 B TWI628508 B TW I628508B
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- 238000000034 method Methods 0.000 title claims abstract description 71
- 229920001400 block copolymer Polymers 0.000 claims abstract description 53
- 239000000463 material Substances 0.000 claims abstract description 44
- 230000008569 process Effects 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000001338 self-assembly Methods 0.000 claims abstract description 24
- 238000005468 ion implantation Methods 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 230000009477 glass transition Effects 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 3
- 150000004767 nitrides Chemical class 0.000 claims 3
- 229910052719 titanium Inorganic materials 0.000 claims 3
- 239000010936 titanium Substances 0.000 claims 3
- PPBRXRYQALVLMV-UHFFFAOYSA-N Styrene Chemical compound C=CC1=CC=CC=C1 PPBRXRYQALVLMV-UHFFFAOYSA-N 0.000 claims 2
- VVQNEPGJFQJSBK-UHFFFAOYSA-N Methyl methacrylate Chemical compound COC(=O)C(C)=C VVQNEPGJFQJSBK-UHFFFAOYSA-N 0.000 claims 1
- 238000002408 directed self-assembly Methods 0.000 abstract description 26
- 238000012546 transfer Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 description 25
- 150000001875 compounds Chemical class 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 238000001459 lithography Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229920001577 copolymer Polymers 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- -1 phosphorus ions Chemical class 0.000 description 2
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 239000004926 polymethyl methacrylate Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000004793 Polystyrene Substances 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
- H01L21/31155—Doping the insulating layers by ion implantation
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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Abstract
本發明披露一種形成圖案的方法。提供一基底,於基底上形成目標層及硬遮罩層,再於硬遮罩層上形成複數個第一抗蝕圖案,然後進行斜角離子佈植製程,於相鄰兩個第一抗蝕圖案間的硬遮罩層中形成第一摻雜區及第二摻雜區,之後移除第一抗蝕圖案,再於硬遮罩層上塗佈定向自組裝材料層,然後對定向自組裝材料層進行自組裝過程,於定向自組裝材料層中形成重複排列的嵌段共聚物圖案,再從定向自組裝材料層中移除不需要的部分,於硬遮罩層上形成第二抗蝕圖案,然後將第二抗蝕圖案轉移至硬遮罩層,形成第三抗蝕圖案,最後經由第三抗蝕圖案蝕刻目標層。
Description
本發明係有關於形成圖案的方法的技術領域,更特定言之,本發明係有關於一種在半導體製程中形成定向自組裝材料(directed self-assembly,DSA)圖案的方法。
隨著電子消費性產品蓬勃的發展,在增加可攜性、計算功率、記憶體容量及能量效率上的需求愈大,使此類產品也愈來愈往小尺寸的方向發展。
特徵大小之不斷縮減使得對形成特徵之技術的需求更大,例如,通常使用光微影技術來圖案化該等特徵。由於微影技術通常藉由投射光或輻射至一表面上完成,因此一特定微影技術之最終解析度取決於諸如光學設備及光或輻射波長的因素。然而,由於一般使用的黃光製程波長之限制,現有的光微影技術恐不敷使用。
一種相對新之非微影圖案化技術,稱為定向自組裝(directed self-assembly,DSA),其係透過嵌段共聚物(block copolymers)的自組裝能力形成遮罩圖案。嵌段共聚物係由在化學方面截然不同的兩個或兩個以上之嵌段(block)形成。一般而言,自組裝係基於其中一個嵌段對下層表面及/或空氣介面具有親和力或偏好,因此,塗佈DSA材料之層的表面能的局部變化將指示嵌段共聚物
如何對準。DSA尤其適用於線/間隙頻率倍增技術(line/space frequency multiplication technique)。
儘管DSA材料可用於形成相對小之遮罩特徵,由於積體電路(integrated circuit,IC)的恆定微型化,仍需要進一步減縮遮罩特徵的大小。因此,存在對用於圖案化小特徵之高解析度方法的持續需求。
本發明係有關於提供一種形成圖案的改良方法,該方法能克服現有光微影技術的限制及增加半導體製程中圖案的解析度。
本發明一方面,提出一種形成圖案的方法。首先,提供一基底,於基底上形成一目標層及一硬遮罩層。之後,於硬遮罩層上形成複數個第一抗蝕圖案。然後進行一斜角離子佈植製程,於相鄰兩個第一抗蝕圖案間的硬遮罩層中形成一第一摻雜區及一第二摻雜區。之後,移除第一抗蝕圖案。接著,於硬遮罩層上塗佈一定向自組裝材料層。然後,對定向自組裝材料層進行一自組裝過程,於定向自組裝材料層中形成重複排列的嵌段共聚物圖案。再從定向自組裝材料層中移除不需要的部分,於硬遮罩層上形成第二抗蝕圖案。然後將第二抗蝕圖案轉移至硬遮罩層,形成第三抗蝕圖案。最後,經由第三抗蝕圖案蝕刻目標層。
根據本發明的一實施例,所述第一摻雜區在空間上與所述第二摻雜區分開,其中,第一摻雜區與第二摻雜區具有相同的寬度。
根據本發明的一實施例,所述斜角離子佈植製程改變了所述硬遮罩層上的極性。所述第一摻雜區及第二摻雜區的極性與未摻雜區的極性不同。
根據本發明的一實施例,所述定向自組裝材料層包含嵌段共聚物。所述自組裝過程在低於所述嵌段共聚物的玻璃轉化溫度(Tg)下進行。
為讓本發明之上述目的、特徵及優點能更明顯易懂,下文特舉較佳實施方式,並配合所附圖式,作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用,並非用來對本發明加以限制者。
1‧‧‧基底
2‧‧‧目標層
3‧‧‧硬遮罩層
4‧‧‧光阻層
41‧‧‧第一抗蝕圖案
P1‧‧‧間距
L1‧‧‧寬度
S1‧‧‧間隔
51‧‧‧斜角離子佈植製程
31‧‧‧第一摻雜區
32‧‧‧第二摻雜區
33‧‧‧未摻雜區
S2‧‧‧寬度
L2‧‧‧寬度
L3‧‧‧寬度
6‧‧‧定向自組裝材料層
61‧‧‧第一嵌段共聚物圖案
62‧‧‧第二嵌段共聚物圖案
63‧‧‧第二抗蝕圖案
P2‧‧‧間距
73‧‧‧第三抗蝕圖案
第1圖至第9圖係根據本發明之實施例所繪示的形成圖案的示例性方法,其中:第1圖為根據本發明之實施例所繪示的半導體結構剖面圖;第2圖為根據本發明之實施例所繪示的剖面圖,其係在第1圖的半導體結構上形成複數個第一抗蝕圖案;第3圖為根據本發明之實施例所繪示的剖面圖,其係進行斜角離子佈植製程後的摻雜半導體結構;第4圖為根據本發明之實施例所繪示的剖面圖,其係移除第一抗蝕圖案後的
半導體結構;第5圖為根據本發明之實施例所繪示的剖面圖,其係塗佈定向自組裝材料層的半導體結構;第6圖為根據本發明之實施例所繪示的剖面圖,其係對定向自組裝材料層進行自組裝過程的半導體結構;第7A圖及第7B圖為根據本發明之實施例所繪示的剖面圖,其係從定向自組裝材料層中移除不需要的部分,於硬遮罩層上形成第二抗蝕圖案的半導體結構;第8A圖及第8B圖為根據本發明之實施例所繪示的剖面圖,其係將第7A圖及第7B圖中的第二抗蝕圖案轉移至硬遮罩層後,形成第三抗蝕圖案的半導體結構;第9A圖及第9B圖為根據本發明之實施例所繪示的剖面圖,其係經由第8A圖及第8B圖中的第三抗蝕圖案蝕刻目標層的半導體結構。
於下文中,係加以陳述本發明之具體實施方式,該些具體實施方式可參考相對應的圖式,俾使該些圖式構成實施方式之一部分。同時也藉由說明,揭露本發明可據以施行之方式。該等實施例已被清楚地描述足夠的細節,俾使該技術領域中具有通常技術者可據以實施本發明。其他實施例亦可被加以施行,且對於其結構上所做之改變仍屬本發明所涵蓋之範疇。
因此,下文的細節描述將不被視為一種限定,且本發明所涵蓋之範疇僅被所附之申請專利範圍以及其同意義的涵蓋範圍。
本發明之一或多個實施例將參照附圖描述,其中,相同元件符號始終用以表示相同元件,且其中闡述的結構未必按比例所繪製。
文中所使用的術語「基底」包括任何具有暴露表面之結構,於所述表面上根據本發明沉積一層,例如,形成積體電路(integrated circuit,IC)結構。術語「基底」被理解為包括半導體晶圓。術語「基板」亦可用以指加工過程中之半導體結構,且可包括已被製造在其上之其他層。術語「基板」包括摻雜及未摻雜半導體、由基底半導體或絕緣體支撐的磊晶半導體層(epitaxial semiconductor layers),以及其他本發明所屬領域具有通常知識者所熟知的半導體結構。
文中所使用的術語「水平」是指平行於基底的常規主平面或表面,而不管其方向。術語「垂直」是指垂直所述水平的方向。術語「上」、「上方」及「下」是指相對於水平面。
請參考第1圖至第9圖。第1圖至第9圖係根據本發明之實施例所繪示的形成圖案的示例性方法。
第1圖為根據本發明之實施例所繪示的半導體結構剖面圖。首先,如第1圖所示,提供一基底1。然後,於基底1的水平主表面上依序形成一目標層2、一硬遮罩層3及一光阻層4。例如,基底1可包含一矽基底,但不限於此。所述目
標層2可包含氧化矽、氮化矽、矽或多晶矽,但不限於此。所述硬遮罩層3可包含氮化鈦、氧化矽、氮化矽、碳化矽、矽碳氮化物或多晶矽,但不限於此。
第2圖為根據本發明之實施例所繪示的剖面圖,其係在第1圖的半導體結構上形成複數個第一抗蝕圖案。如第2圖所示,進行一微影製程,包括曝光及顯影,但不限於此,以移除部分光阻層4從而於硬遮罩層3上形成複數個第一抗蝕圖案41。根據本發明一實施例,當從上往下看時,第一抗蝕圖案41係平行且直條紋(或線狀)的圖案。第一抗蝕圖案41具有一間距P1,所述間距P1包含各個第一抗蝕圖案41的寬度L1及相鄰兩個第一抗蝕圖案41間的間隔S1。
第3圖為根據本發明之實施例所繪示的剖面圖,其係進行斜角離子佈植製程後的摻雜半導體結構。如第3圖所示,進行一斜角離子佈植製程51,於相鄰兩個第一抗蝕圖案41間的硬遮罩層3中形成一第一摻雜區31及一第二摻雜區32,其中所述第一摻雜區31在空間上與所述第二摻雜區32分開。經由於硬遮罩層3中形成第一摻雜區31與第二摻雜區32,對應於第一摻雜區31與第二摻雜區32圖案的硬遮罩層3的極性被改變。
斜角離子佈植製程51可包含多個離子佈植步驟,並以不同的方向進行,例如,兩個相反的方向,且不同的植入角度。此外,斜角離子佈植製程51非垂直於基底1的水平主表面。由於斜角離子佈植製程51是以斜角度進行,部分離子會被第一抗蝕圖案41所阻礙,且不會植入相鄰兩個第一抗蝕圖案41間的硬遮罩層3的陰影區。應理解的是,可以調整第一抗蝕圖案41的高度及前述斜角度以形成所欲第一摻雜區31與第二摻雜區32的寬度。
斜角離子佈植製程51所使用的離子可選自由磷離子、砷離子、鈍氣離子及其組合所組成之群。根據本發明一實施例,使用相同的離子摻雜至第一摻雜區31與第二摻雜區32。應理解的是,也可使用不同的離子摻雜至第一摻雜區31與第二摻雜區32。
根據本發明一實施例,第一摻雜區31及第二摻雜區32的極性與未摻雜區33的極性不同。於第一摻雜區31及第二摻雜區32間形成的未摻雜區33具有寬度S2。根據本發明一實施例,第一摻雜區31及第二摻雜區32具有相同寬度(L2=L3)。應理解的是,在某些實例中,可因所需的設計使第一摻雜區31及第二摻雜區32具有不相同的寬度(L2≠L3)。
根據本發明一實施例,相鄰的兩個第一抗蝕圖案41間的間隔(例如,S1)可為第一抗蝕圖案41的寬度L1的三倍寬(S1:L1=3:1)。經由妥善的控制第一抗蝕圖案41的高度及斜角離子佈植製程51的斜角度,可使第一摻雜區31的寬度L2、第二摻雜區32寬度L3、未摻雜區33的寬度S2及第一抗蝕圖案41的寬度L1皆相同(L2=L3=S2=L1)。
第4圖為根據本發明之實施例所繪示的剖面圖,其係移除第一抗蝕圖案41後的半導體結構。之後,完全移除第一抗蝕圖案41以暴露出之前被其所覆蓋的硬遮罩層3的區域。根據本發明一實施例,可利用習知的蝕刻方法移除第一抗蝕圖案41,但不限於此。
隨後,如第5圖所示,可經由旋塗、旋鑄、刷塗或汽相沉積的方法,於硬遮罩層3上塗佈一定向自組裝(directed self-assembly,DSA)材料層6。根據本
發明一實施例,DSA材料層6可包含兩種或兩種以上不混溶之化合物,或包含至少兩種具有不同特徵(諸如官能性、極性、水親和力、抗蝕性等)之成分的自組裝化合物,使得兩種化合物或成分以合理的方式分離及對準,以及選擇性地移除一種化合物或成分。
根據本發明一實施例,DSA材料層6可包含至少兩種不同聚合物的嵌段共聚物(block copolymers)。嵌段共聚物尤其適用於DSA技術,因為其可合成為含有至少兩種獨特的嵌段,使得每一成分可在適當的條件下對準,且在對準之後選擇性地移除。根據本發明一實施例,例如,所述嵌段共聚物可包含苯乙烯(polystyrene,PS)及甲基丙烯酸甲酯(poly(methyl methacrylate),PMMA),但不限於此。應理解的是,可選擇各個嵌段的大小及其組成的嵌段共聚物之比例,以促進一自組裝過程及形成具有期望尺寸之有組織的的嵌段域。具有較長共聚物的嵌段共聚物可用於形成較大的區域,具有較短共聚物的嵌段共聚物可用於形成較小的區域。
如第6圖所示,隨後,對DSA材料層6進行自組裝過程,以於硬遮罩層3上形成第一嵌段共聚物圖案61及第二嵌段共聚物圖案62,其中,所述第一嵌段共聚物圖案61及第二嵌段共聚物圖案62係對應於第一摻雜區31、第二摻雜區32及未摻雜區33重複且交替的排列。硬遮罩層3的第一摻雜區31及第二摻雜區32提供了DSA材料層6進行自組裝過程的界面。自組裝過程可包含退火過程,但不限於此。DSA材料層6的第一嵌段共聚物圖案61係直接形成於硬遮罩層3的未摻雜區33上。DSA材料層6的第二嵌段共聚物圖案62係直接形成於硬遮罩層3的第一摻雜區31及第二摻雜區32上。第一嵌段共聚物圖案61及第二嵌段共聚物圖案62係重複的排列。
應理解的是,第一嵌段共聚物圖案61及第二嵌段共聚物圖案62的寬度係由嵌段共聚物中兩種不同的聚合物之大小(或長度)決定。加熱至足夠的溫度可促進或加速自組裝過程的進行,其中,所述溫度可選擇足夠低以防止對嵌段共聚物或設置在基底1上的半導體裝置產生不利的影響。根據本發明一實施例,所述自組裝過程是在低於嵌段共聚物的玻璃轉化溫度(Tg)下進行。重複且交替排列的第一嵌段共聚物圖案61及第二嵌段共聚物圖案62可做為圖案化下層的遮罩。
第7A圖及第7B圖為根據本發明之實施例所繪示的剖面圖,其係從DSA材料層6中移除不需要的部分,以於硬遮罩層3上形成第二抗蝕圖案的半導體結構。如圖7A所示,從DSA材料層6中移除不需要的部分,例如,直接位於未摻雜區33上的第一嵌段共聚物圖案61,同時留下完整的第二嵌段共聚物圖案62。或者,如圖7B所示,從DSA材料層6中移除不需要的部分,例如,直接位於第一摻雜區31及第二摻雜區32上的第二嵌段共聚物圖案62,同時留下完整的第一嵌段共聚物圖案61。
由於第一嵌段共聚物圖案61及第二嵌段共聚物圖案62具有不同的特性,隨後可選擇性地移除第一嵌段共聚物圖案61或是第二嵌段共聚物圖案62之任一者,以產生第二抗蝕圖案63。例如,第一嵌段共聚物圖案61在濕式或乾式蝕刻劑中具有第一蝕刻速率,而第二嵌段共聚物圖案62在濕式或乾式蝕刻劑中具有第二蝕刻速率,其中,所述第一蝕刻速率與第二蝕刻速率是不相同的。特定言之,視所使用的蝕刻劑而定,第一蝕刻速率可高於第二蝕刻速率。因此,可選擇適合蝕刻劑以選擇性地移除第一嵌段共聚物圖案61或第二嵌段共聚物圖
案62,從而使第一嵌段共聚物圖案61或第二嵌段共聚物圖案62中之另一者完整地留在硬遮罩層3上,以形成第二抗蝕圖案63。第二抗蝕圖案63具有一間距P2,包含硬遮罩層3中的第一摻雜區31的寬度L2、第二摻雜區32的寬度L3及未摻雜區33的寬度S2。值得注意的是,第二抗蝕圖案63的間距P2小於第一抗蝕圖案41的間距P1。
第8A圖及第8B圖為根據本發明之實施例所繪示的剖面圖,其係將第7A圖及第7B圖中的第二抗蝕圖案63轉移至硬遮罩層3後,形成第三抗蝕圖案的半導體結構。如第8A圖及第8B圖所示,以第二抗蝕圖案63作為一蝕刻遮罩,進行一蝕刻製程(諸如乾式蝕刻),使第二抗蝕圖案63轉移至硬遮罩層3,從而形成第三抗蝕圖案73。
第9A圖及第9B圖為根據本發明之實施例所繪示的剖面圖,其係經由第8A圖及第8B圖中的第三抗蝕圖案73蝕刻目標層2的半導體結構。最後,如第9A圖及第9B圖所示,以第三抗蝕圖案73作為一蝕刻遮罩,進行另一蝕刻製程(諸如乾式蝕刻),使第三抗蝕圖案73轉移至目標層2。
經由前述步驟,如第9A圖及第9B圖所示,於目標層2中所形成之圖案的間距比一開始形成於硬遮罩層3上的第一抗蝕圖案41之間距更精細。
綜上所述,本發明提供一種在半導體製程中形成定向自組裝圖案的改良方法,該方法能克服現有光微影技術的限制及增加半導體製程中圖案的解析度。
本發明之形成圖案的方法。首先,提供一基底1,於基底1上形成一
目標層2及一硬遮罩層3。之後,於硬遮罩層3上形成複數個第一抗蝕圖案41。然後進行一斜角離子佈植製程51,於相鄰兩個第一抗蝕圖案41間的硬遮罩層3中形成一第一摻雜區31及一第二摻雜區32。之後,移除第一抗蝕圖案41。接著,於硬遮罩層3上塗佈一定向自組裝材料層6。然後,對定向自組裝材料層6進行一自組裝過程,於定向自組裝材料層6中形成重複排列的嵌段共聚物圖案61及62。再從定向自組裝材料層6中移除不需要的部分,於硬遮罩層3上形成第二抗蝕圖案63。然後將第二抗蝕圖案63轉移至硬遮罩層3,形成第三抗蝕圖案73。最後,經由第三抗蝕圖案73蝕刻目標層2。
第一摻雜區31在空間上與第二摻雜區32分開,其中,第一摻雜區31與第二摻雜區32具有相同的寬度(L2=L3)。
斜角離子佈植製程51改變了硬遮罩層3上的極性。第一摻雜區31及第二摻雜區32的極性與未摻雜區33的極性不同。
定向自組裝材料層6包含嵌段共聚物。自組裝過程在低於所述嵌段共聚物的玻璃轉化溫度(Tg)下進行。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
Claims (13)
- 一種形成圖案的方法,包含:提供一基底,於該基底上形成一目標層及一硬遮罩層,其中該硬遮罩層與該目標層直接接觸,且其中該硬遮罩層包含氮化鈦、氧化矽、氮化矽、碳化矽、矽碳氮化物或多晶矽;於該硬遮罩層上形成第一抗蝕圖案;進行一斜角離子佈植製程以於該硬遮罩層中且介於相鄰之第一抗蝕圖案之間形成一第一摻雜區及一第二摻雜區;移除該等第一抗蝕圖案;於該硬遮罩層上塗佈一定向自組裝(DSA)材料層;對該DSA材料層進行一自組裝過程以於該DSA材料層中形成一重複排列的嵌段(block)共聚物圖案;從該DSA材料層中移除不需要的部分以於該硬遮罩層上形成第二抗蝕圖案;將該等第二抗蝕圖案轉移至該硬遮罩層以形成第三抗蝕圖案;及經由該等第三抗蝕圖案蝕刻該目標層。
- 如申請專利範圍第1項所述的形成圖案的方法,其中該目標層包含氧化矽、氮化矽、矽或多晶矽。
- 如申請專利範圍第1項所述的形成圖案的方法,其中該第一摻雜區在空間上與該第二摻雜區分開且該第一摻雜區及該第二摻雜區介於該等相鄰之第一抗蝕圖案之間。
- 如申請專利範圍第1項所述的形成圖案的方法,其中該第一摻雜區與該第二摻雜區具有相同的寬度。
- 如申請專利範圍第1項所述的形成圖案的方法,其中該第一摻雜區與該第二摻雜區具有不同的寬度。
- 如申請專利範圍第1項所述的形成圖案的方法,其中該斜角離子佈植製程改變了該硬遮罩層上的極性。
- 如申請專利範圍第6項所述的形成圖案的方法,其中該第一摻雜區及該第二摻雜區的極性與該硬遮罩層之未摻雜區的極性不同。
- 如申請專利範圍第1項所述的形成圖案的方法,其中該定向自組裝材料層包含嵌段共聚物。
- 如申請專利範圍第8項所述的形成圖案的方法,其中該嵌段共聚物包含苯乙烯及甲基丙烯酸甲酯。
- 如申請專利範圍第9項所述的形成圖案的方法,其中該自組裝過程在低於該嵌段共聚物的玻璃轉化溫度(Tg)下進行。
- 如申請專利範圍第1項所述的形成圖案的方法,其中該不需要的部分係不直接位於該第一摻雜區及該第二摻雜區的該DSA材料層。
- 一種形成圖案的方法,包含:提供一基底,於該基底上形成一目標層及一硬遮罩層,其中該硬遮罩層與該目標層直接接觸,且其中該硬遮罩層包含氮化鈦、氧化矽、氮化矽、碳化矽、矽碳氮化物或多晶矽;於該硬遮罩層上形成第一抗蝕圖案;進行一斜角離子佈植製程以於該硬遮罩層中且介於相鄰之第一抗蝕圖案之間形成一第一摻雜區及一第二摻雜區;移除該等第一抗蝕圖案;於該硬遮罩層上塗佈一定向自組裝(DSA)材料層;對該DSA材料層進行一自組裝過程以於該DSA材料層中形成一重複排列的嵌段共聚物圖案;從該DSA材料層中移除不需要的部分以於該硬遮罩層上形成第二抗蝕圖案,該不需要的部分包含直接位於該第一摻雜區及該第二摻雜區的該DSA材料層;將該等第二抗蝕圖案轉移至該硬遮罩層以形成第三抗蝕圖案;及經由該等第三抗蝕圖案蝕刻該目標層。
- 一種形成圖案的方法,包含:提供一基底,於該基底上形成一目標層及一硬遮罩層,其中該硬遮罩層與該目標層直接接觸,且其中該硬遮罩層包含氮化鈦、氧化矽、氮化矽、碳化矽、矽碳氮化物或多晶矽;於該硬遮罩層上形成第一抗蝕圖案;進行一斜角離子佈植製程以於該硬遮罩層中且介於相鄰之第一抗蝕圖案之間形成一第一摻雜區及一第二摻雜區;移除該等第一抗蝕圖案;於該硬遮罩層上塗佈一定向自組裝(DSA)材料層;對該DSA材料層進行一自組裝過程以於該DSA材料層中形成一重複排列的嵌段共聚物圖案;從該DSA材料層中移除不需要的部分以於該硬遮罩層上形成第二抗蝕圖案,該等第二抗蝕圖案具有小於該等第一抗蝕圖案之間距之一間距;將該等第二抗蝕圖案轉移至該硬遮罩層以形成第三抗蝕圖案;及經由該等第三抗蝕圖案蝕刻該目標層。
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