TWI626873B - Manufacturing method of printed wiring board - Google Patents

Abstract

The invention provides a method for manufacturing a printed wiring board, which can meaningfully prevent the invasion of the medicinal solution toward the interface between the carrier and the ultra-thin copper layer in the step of forming the additional wiring layer, and can significantly suppress the coreless support. Part of the ultra-thin copper layer in the separation step was cracked and the resulting defects. The method of the present invention includes the steps of preparing a product of the average height Wc of the undulation curve element and the peak count Pc in the surface on the side of the release layer of the carrier, and the product Wc × Pc of the copper foil with the carrier is 20-50 μm. Or the step of forming a build-up wiring layer on the ultra-thin copper layer to prepare a build-up body with the build-up wiring layer, separating the build-up body with the build-up wiring layer from the release layer to obtain a multilayer wiring board containing the build-up wiring layer Steps, and a step of processing a multilayer wiring board to obtain a printed wiring board.

Description

Manufacturing method of printed wiring board

The present invention relates to a method for manufacturing a printed wiring board.

In recent years, in order to increase the mounting density and miniaturization of printed wiring boards, multilayered printed wiring boards have been widely used. Such multilayer printed wiring boards are mostly used in portable electronic devices for the purpose of weight reduction or miniaturization. Therefore, the multilayer printed wiring board is required to further reduce the thickness of the interlayer insulating film and further reduce the thickness and weight of the wiring board.

As a technology meeting these requirements, a manufacturing method of a multilayer printed wiring board using a coreless build-up method is adopted. The so-called coreless build-up method is a method in which an insulating layer and a wiring layer are alternately laminated (build-up) without using a so-called core substrate, and are multilayered. Regarding the coreless build-up method, it is proposed to use a copper foil with a carrier to facilitate peeling of the support from the multilayer printed wiring board. For example, Patent Document 1 (Japanese Patent Application Laid-Open No. 2005-101137) discloses a method for manufacturing a package substrate for mounting a semiconductor element, which includes attaching an insulating resin layer on a carrier surface of a copper foil with a carrier as a support, and attaching the carrier to the carrier. The very thin copper layer side of the copper foil is formed by pattern electrolytic copper plating to form the first wiring conductor. Body, forming an additional wiring layer, peeling off the supporting substrate with the carrier, and removing the extremely thin copper layer.

However, in the method described above, since the copper foil with a carrier and the support are the same size, the interface end between the carrier and the ultra-thin copper layer is exposed to the outside. Therefore, a chemical solution (such as an etching solution or a slag removing solution) used in forming the build-up wiring layer may invade into the interface from the end of the interface between the carrier and the ultra-thin copper layer. If this medicinal solution penetrates into the interface, the adhesion between the carrier and the ultra-thin copper layer is reduced, and during the manufacturing process, the increased wiring layer may peel off from the support, resulting in a decrease in yield.

As a method for manufacturing a printed wiring board as a countermeasure to this problem, it is proposed to provide an extra area on the periphery of the product formation area so that the end of the interface between the carrier and the ultra-thin copper layer is not exposed to the outside. Method. For example, Patent Document 2 (Japanese Unexamined Patent Application Publication No. 2014-130856) discloses a method for manufacturing a printed wiring board, which includes preparing a copper foil with a carrier (a separable metal foil) having an extremely thin copper layer area smaller than a carrier area, and preparing a carrier The prepreg (support substrate) with a large area size, the ultra-thin copper layer is laminated to form a support with the prepreg, and the build-up wiring layer is formed with the same size as the carrier. The laminated body is cut off inside the ultra-thin copper layer and separated. The carrier is subjected to subtractive processing to form the outermost wiring layer. According to this method, the interface between the ultra-thin copper layer and the carrier is blocked from the external environment, and the chemical liquid can be prevented from intruding from the interface when the build-up wiring layer is formed.

[Prior technical literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open No. 2005-101137

[Patent Document 2] Japanese Patent Laid-Open No. 2014-130856

However, the method of Patent Document 2 has the following problems: i) the area-processed copper foil with a carrier must be made in advance so that the area of the ultra-thin copper layer is smaller than the area of the carrier, and ii) the area protruding from the area of the ultra-thin copper layer And the area of the prepreg protruding from the copper foil with the carrier becomes an unnecessary area outside the product object. Iii) Before peeling the support, it is necessary to cut off all sides of the laminate with the release layer exposed on the end face.

The present inventors now have the insight that the use of a copper foil with a carrier that meets specific conditions (the Wc × Pc to be described later is 20 to 50 μm) using a carrier-side surface of the carrier is used to produce a printed wiring board by a coreless build-up method, Without the need for the area processing of copper foil with a carrier or the size control of the prepreg as described in Patent Document 2, it is possible to meaningfully prevent the medicinal solution from moving toward the carrier and the ultra-thin copper layer in the step of forming the additional wiring layer. Interface intrusion, and it can significantly suppress the partial cracking of the ultra-thin copper layer and the defects generated in the separation step of the coreless support (such as a part of the ultra-thin copper layer to the carrier, or pinholes in the ultra-thin copper layer) Occurs and results from overetching).

Therefore, an object of the present invention is to provide a method for manufacturing a printed wiring board, which does not require the processing of the area of the copper foil with a carrier or the size control of the prepreg, and can meaningfully prevent the medicinal solution in the step of forming the wiring layer. Intrusion toward the interface between the carrier and the ultra-thin copper layer, and it is possible to significantly suppress the partial cracking of the ultra-thin copper layer and the resulting defects during the separation step of the coreless support.

According to the aspect of the present invention, a method is provided, which is a method for manufacturing a printed wiring board, and includes the following steps: a step of preparing a copper foil with a carrier in order, the copper foil with a carrier having a carrier, a release layer, and an electrode; A thin copper layer, and in the surface of the aforementioned release layer side of the aforementioned carrier, the average height Wc of the undulating curve requirements measured in accordance with B0601-2001 and the peak count Pc of the product Wc × Pc is 20 to 50 μm. The step of forming a build-up wiring layer with a build-up wiring layer on a thin copper layer, separating the build-up body with the build-up wiring layer from the peeling layer to obtain a multilayer wiring board containing the build-up wiring layer. Steps, and a step of obtaining a printed wiring board by processing the aforementioned multilayer wiring board.

10, 30‧‧‧ copper foil with carrier

12, 32‧‧‧ carrier

14, 34‧‧‧ peeling layer

16, 36‧‧‧ extremely thin copper layer

18‧‧‧ coreless support

20‧‧‧Photoresist Pattern

21‧‧‧ Etching Resistant

22‧‧‧ Pattern plating

24‧‧‧Wiring pattern

26‧‧‧The first wiring layer

28‧‧‧ Insulation

38‧‧‧ 2nd wiring layer

40‧‧‧nth wiring layer

42‧‧‧Additional wiring layer

44‧‧‧Multilayer wiring board

46‧‧‧printed wiring board

FIG. 1A is a diagram showing the first half steps in an example of the embedded circuit forming method in the same state as the coreless build-up method.

FIG. 1B shows an example of the embedded circuit formation method in the same manner as the coreless build-up method, following the steps shown in FIG. 1A after the latter half.

FIG. 2A is a diagram showing the first half steps in another example of the carrier / subtraction processing method of the coreless build-up method.

Figure 2B shows another form of carrier / subtraction processing of the coreless build-up method In one example of the method, the second half of the step shown in FIG. 2A is continued.

definition

The following shows the parameter definitions used to specify the invention.

The "peak count Pc" in this specification refers to the number of mountains per evaluation length (for example, 0.8 mm) in each profile curve of a parameter measured according to B0601-2001 (ISO 4287-1997).

The "average height Wc of the undulating curve element" in this specification is the average value of the height of the undulating curve element in the reference length of the parameter measured according to B0601-2001 (ISO 4287-1997).

The so-called "ten-point average roughness Rz" in this description refers to the average curve from the highest peak to the fifth highest peak in the height order and the deepest valley bottom in the roughness curve based on the reference length of the parameter determined by B0601-1994. The sum of the averages of the 5th valley depth in the depth order.

The "electrode surface" of the carrier in this specification refers to the side of the carrier that comes into contact with the cathode when the carrier is manufactured.

The "precipitating surface" of the carrier in this specification refers to the surface on which the electrolytic copper is precipitated when the carrier is produced, that is, the side (the electrolyte surface) that is not in contact with the cathode.

Manufacturing method of printed wiring board

The present invention relates to a method for manufacturing a printed wiring board. Method package of the present invention It includes (1) a step of preparing a copper foil with a carrier having a specific surface profile, and (2) a manufacturing process of a printed wiring board using a coreless build-up method. In addition, the manufacturing process of the printed wiring board using the coreless build-up method includes (2a) a step of forming a build-up wiring layer on a carrier or an ultra-thin copper layer, (2b) a step of separating the obtained laminated body from the release layer, and ( 2c) a step of processing the obtained multilayer wiring board.

(1) Preparation of copper foil with carrier

The method of the present invention is to prepare a copper foil with a carrier having a specific surface profile. The copper foil with a carrier has a carrier, a release layer, and an ultra-thin copper layer in this order. In particular, in the surface of the copper foil with a carrier used in the present invention on the side of the release layer side of the carrier, the product of the mean height Wc of the undulation curve element and the peak count Pc Wc × Pc is 20 to 50 μm. By using a copper foil with a carrier in the range of Wc × Pc in the range of 20 to 50 μm on the side of the release layer side of the carrier, a printed wiring board is manufactured by a coreless build-up method, and the copper foil with a carrier as described in Patent Document 2 may not be required. The area processing or the size control of the prepreg can meaningfully prevent the medicinal solution from invading the interface between the carrier and the ultra-thin copper layer in the step of forming the additional wiring layer. In addition, it can also significantly inhibit the partial cracking of the ultra-thin copper layer and the resulting defects during the separation step of the coreless support (e.g., the residue of the ultra-thin copper layer on the carrier or the occurrence of pinholes in the ultra-thin copper layer and its cause). The wiring is over-etched here).

The above-mentioned advantageous effect is achieved unexpectedly by using a copper foil with a carrier having Wc × Pc of 20 to 50 μm in the surface on the side of the release layer of the carrier. The mechanism may not be determined, but it is considered as follows. First, due to the undulating curve requirements The average height Wc is the average value of the heights of the undulating curve elements. Therefore, the higher the value, the greater the undulation. It is considered that the barrier for the immersion of the medicinal liquid at the interface between the carrier and the extremely thin copper layer becomes larger. This can be explained as the invasion of the medicinal solution is hindered by the mountain of the undulating curve. In addition, since the peak count Pc is the number of mountains per ping price length in the contour curve, the larger the value is, the more mountains there are. It can be said that there are more barriers for medicinal solution infiltration at the interface between the carrier and the ultra-thin copper layer. In addition, when Wc × Pc is 20 μm or more, it is considered that the multiplication effect of Wc and Pc can effectively prevent the medicinal solution from intruding into the interface between the carrier and the ultra-thin copper layer in the step of forming the additional wiring layer. On the other hand, when Wc × Pc is too large, the ultra-thin copper layer is likely to be partially cracked during the separation step of the coreless support. As a result, the residue of the ultra-thin copper layer on the carrier or the needle of the ultra-thin copper layer is liable to occur. Holes occur and the over-etching that results from them. The reason is that the larger the Wc × Pc (especially the larger Wc), the extremely thin copper layer tends to become thinner in the undulating valley portion (due to the copper precipitation behavior during electrolysis), and the thin portion becomes fragile and easily ruptures. The reason. At this point, by making Wc × Pc less than or equal to 50 μm, it is possible to significantly suppress the partial cracking of the ultra-thin copper layer and the partial residue of the ultra-thin copper layer on the carrier in the separation step of the coreless support. . In short, the above-mentioned effect of setting Wc × Pc to a specific range of 20 to 50 μm cannot be achieved only by the control of surface roughness, but it is the first time that Wc originated from the undulating curve by reflecting the unevenness of the wavelength longer than the contour curve This is achieved by multiplying by the peak count Pc.

From the above viewpoint, Wc × Pc in the surface on the release layer side of the carrier is 20 to 50 μm, preferably 23 to 40 μm, and more preferably 26 to 33 μm. In addition, in the surface on the release layer side of the carrier, Wc is preferably 0.5 to 1.0 μm, and more preferably It is 0.55 to 0.95 μm, and more preferably 0.6 to 0.9 μm. In the surface of the release layer side of the carrier, Pc is preferably 22 to 65, more preferably 30 to 55, and even more preferably 32 to 45. If it is within the above-mentioned preferable range, the above-mentioned chemical liquid can be more effectively prevented from invading the interface and a part of the ultra-thin copper layer from being broken.

Preferably, the ten-point average roughness Rz of the surface on the release layer side of the carrier measured according to JIS B0601-1994 is 1.5 to 6.5 μm, more preferably 2.2 to 6.0 μm, and even more preferably 2.9 to 5.0 μm. If it is within this range, the ease of peeling is ensured, and there is also an advantage that cracking of an extremely thin copper layer can be effectively prevented. In addition, the measurement of the ten-point average roughness Rz on the side of the release layer side of the carrier is typically performed on the surface of the carrier after the ultra-thin copper layer is peeled from the carrier copper foil.

The carrier is a thin layer or layer that supports an ultra-thin copper layer to improve its handleability, and may have a conventional structure except that Wc × Pc in the surface on the side of the release layer is 20 to 50 μm. Examples of the carrier include aluminum foil, copper foil, stainless steel (SUS) foil, resin film, metal-coated resin film, resin plate, glass plate, and the like. A copper foil is preferable because it is easy to control the Wc × Pc value in the surface on the side of the release layer by manufacturing conditions, and to maintain the chemical resistance of the carrier itself. The copper foil may be either a rolled copper foil or an electrolytic copper foil. However, as described above, the carrier is preferably an electrolytic copper foil in terms of easily controlling the Wc × Pc value in the surface on the side of the release layer. The thickness of the carrier is typically 250 μm or less, and preferably 12 μm to 200 μm.

The realization of Wc, Pc, and Rz in the above range on the surface of the carrier is preferably performed as follows: When the carrier is, for example, electrolytic copper foil, the electrolytic solution (such as sulfuric acid and copper sulfate solution) is subjected to activated carbon treatment to remove electricity. After the remaining additives in the solution are decomposed, an electrolytic solution treated with activated carbon is newly added with an additive such as collagen or gelatin and electrolyzed under conventional conditions to produce an electrolytic copper foil having a thickness of about 10 to 35 μm. The precipitation surface (electrolyte surface) is the surface on the release layer side. The formation of the rough surface of the process by this electrical analysis is particularly effective as a method of adjusting the surface of the carrier to various contours. However, the method for forming the rough surface is not limited to the above-mentioned method. In addition, physical etching such as chemical etching formation, spray treatment, and the like may be used.

The ultra-thin copper layer is not particularly limited as long as it has a conventional structure used for a copper foil with a carrier for manufacturing printed wiring boards. For example, the ultra-thin copper layer may be formed by a wet film formation method such as electroless copper plating method and electrolytic copper plating method, a dry film formation method such as sputtering and chemical vapor deposition, or a combination thereof. . The preferred thickness of the ultra-thin copper layer is 0.1 to 10.0. For example, as a wiring layer formed on the surface of a coreless support, in order to form a fine circuit with a line / space = 25 μm or less / 25 μm or less, the thickness of the ultra-thin copper layer is particularly preferably 0.2 to 7.0 μm.

The peeling layer is a layer that weakens the peeling strength of the carrier, ensures the stability of the strength, and further has a function of suppressing mutual diffusion caused between the carrier and the ultra-thin copper layer during high-temperature pressure forming. The release layer is generally formed on one side of the carrier, but may be formed on both sides. The release layer may be any of an organic release layer and an inorganic release layer. Examples of the organic component used in the organic release layer include nitrogen-containing organic compounds, sulfur-containing organic compounds, carboxylic acids, and the like. Examples of the nitrogen-containing organic compound are a triazole compound, an imidazole compound, and the like. Among them, the triazole compound is preferable because it is easy to stabilize the peelability. Make Examples of triazole compounds are 1,2,3-benzotriazole, carboxybenzotriazole, N ', N'-bis (benzotriazolylmethyl) urea, 1H-1,2, 4-triazole and 3-amino-1H-1,2,4-triazole. Examples of the sulfur-containing organic compound are mercaptobenzothiazole, thiocyanuric acid, 2-benzimidazolethiol, and the like. Examples of the carboxylic acid include a monocarboxylic acid and a dicarboxylic acid. On the other hand, examples of the inorganic component used in the inorganic release layer include Ni, Mo, Co, Cr, Fe, Ti, W, P, Zn, and a chromate-treated film. The formation of the release layer may be performed by contacting at least one surface of the carrier with a solution containing a release layer component, and fixing the release layer component to the surface of the carrier. When the carrier is brought into contact with the solution containing the release layer component, the contact may be performed by immersing in the solution containing the release layer component, spraying the solution containing the release layer component, flowing down the solution containing the release layer component, or the like. In addition, a method of forming a film of a peeling layer component such as carbon by a vapor phase method such as vapor deposition or sputtering may also be adopted. Among them, especially based on the point that the peeling layer itself can be made thinner, and the chemical liquid has an excellent invasion effect at the interface between the carrier and the ultra-thin copper layer, the surface profile of the carrier steel after the carrier steel is manufactured on the side surface of the peeling layer of the carrier In terms of advantageous design of the step of minimizing change, etc., the release layer is preferably an organic release layer. In addition, the fixing of the release layer component to the carrier surface may be performed by adsorbing or drying the release layer component-containing solution, plating the release layer component in the release layer component-containing solution, or the like. The thickness of the release layer is typically 1 nm to 1 μm, preferably 5 nm to 500 nm, and more preferably 6 nm to 100 nm.

As desired, other functional layers may be provided between the release layer and the carrier and / or the ultra-thin copper layer. An example of such another functional layer is an auxiliary metal layer. The auxiliary metal layer is preferably made of nickel and / or cobalt. By The formation of such an auxiliary metal layer on the surface side of the carrier and / or the surface side of the ultra-thin copper layer can suppress the mutual diffusion caused between the carrier and the ultra-thin copper layer during high-temperature or long-term hot-press forming, and guarantee the carrier's Stability of peel strength. The thickness of the auxiliary metal layer is preferably 0.001 to 3 μm.

If desired, an anti-rust treatment can also be applied to the very thin copper layer. The antirust treatment preferably includes a plating treatment using zinc. The plating treatment using zinc may be any one of a zinc plating treatment and a zinc alloy plating treatment, and the zinc alloy plating treatment is particularly preferably a zinc-nickel alloy treatment. The zinc-nickel alloy treatment may be a plating treatment containing Ni and Zn, and may further contain other elements such as Sn, Cr, and Co. The Ni / Zn adhesion ratio in zinc-nickel alloy plating, based on mass ratio, is preferably 1.2 to 10, more preferably 2 to 7, and even more preferably 2.7 to 4. In addition, the rust prevention treatment preferably further includes a chromate treatment, which is more preferably performed on a zinc-containing plating surface after a zinc plating treatment. This can further improve rust prevention. A particularly good antirust treatment is a combination of zinc-nickel alloy plating and subsequent chromate treatment.

If desired, the surface of the ultra-thin copper layer may also be treated with a silane coupling agent to form a silane coupling agent layer. This can improve moisture resistance, chemical resistance, adhesion to a resin layer, and the like. The silane coupling agent layer can be formed by appropriately diluting the silane coupling agent, coating, and drying. Examples of the silane coupling agent include epoxy-functional silane coupling agents such as 4-glycidylbutyltrimethoxysilane, γ-glycidoxypropyltrimethoxysilane, and γ-aminopropyltrimethyl Oxysilane, N-β (aminoethyl) γ-aminopropyltrimethoxysilane, N-3- (4- (3-aminopropyloxy) butoxy) propyl-3-amine Propyltrimethoxysilane, N-phenyl-γ-aminopropyltrimethoxysilane, etc. Amine-functional silane coupling agent, or thiol-functional silane coupling agent such as γ-mercaptopropyltrimethoxysilane, or olefin-functional silane coupling agent such as vinyltrimethoxysilane, vinylphenyltrimethoxysilane, etc. Mixtures, or propylene-functional silane coupling agents such as γ-methacryl methoxypropyltrimethoxysilane, or imidazole-functional silane coupling agents such as imidazolium silane, or triazine-functional silanes such as triazine silane Coupling agent, etc.

(2) Manufacturing of printed wiring boards using coreless build-up method

The production of the printed wiring board in the method of the present invention is performed by the coreless build-up method using the above-mentioned copper foil with a carrier. Examples of preferred forms of the coreless build-up method include a buried circuit formation method and a carrier / subtraction processing method. Each method is as follows.

The embedded circuit formation method is performed by: forming a support body by laminating a carrier and a support body (such as a prepreg body), forming a pattern circuit on an ultra-thin copper layer, forming an additional wiring layer, and peeling the support Flush etching on the body and very thin copper layers. The steps of the manufacturing method are shown in FIGS. 1A and 1B. The state shown in FIGS. 1A and 1B is drawn to simplify the description. The copper foil 10 with a carrier is provided on one side of the coreless support 18 to form an additional wiring layer 42. However, it is desirable for the coreless support 18 The two sides of the copper foil 10 with a carrier are provided on both sides to form the build-up wiring layer 42. In the example shown in FIGS. 1A and 1B, firstly, a copper foil 10 with a carrier having a carrier 12, a release layer 14, and an ultra-thin copper layer 16 is prepared in this order. The copper foil 10 with a carrier is laminated on the carrier 12 side to a prepreg, etc. On the coreless support 18. Next, a photoresist pattern 20 is formed on the ultra-thin copper layer 16 The patterning (copper plating) 22 is formed and the resist pattern 20 is peeled off to form a wiring pattern 24. Next, the first wiring layer 26 is formed by performing a pre-lamination treatment such as roughening treatment on the pattern plating. Next, as shown in FIG. 1B, the wiring pattern 24 in which the build-up wiring layer 42 is to be formed is embedded in the insulating layer 28. In this lamination step, the insulating layer 28 and the copper foil 30 with a carrier (including the carrier 32, the peeling layer 34 and the ultra-thin copper layer 36) are laminated, the carrier 32 is peeled off, and the ultra-thin copper layer 36 and The insulating layer 28 directly below is subjected to laser processing. Next, patterning is performed by photoresist processing, electroless copper plating, electrolytic copper plating, photoresist stripping, and submerged etching to form a second wiring layer 38. This patterning is repeated as needed until formation The n-th wiring layer 40 (n is an integer of 2 or more). Next, the coreless support 18 and the carrier 12 are peeled off together, and the ultra-thin copper layer 16 exposed on the surface of the wiring pattern 24 is removed by submerged etching to obtain a specific embedded circuit pattern. A printed wiring board 46 having such a specific embedded circuit pattern can be obtained. In this aspect, since the extremely thin copper layer 16 is not easily broken when the coreless support 18 and the carrier 12 are peeled together, the pinhole formation in the extremely thin copper layer 16 and the wiring pattern during submerged etching can be effectively avoided. The disadvantage of over-etching is 24.

The carrier / subtraction processing method is performed by the following methods: making a support from the laminate of the carrier and the prepreg, making an additional wiring layer on the carrier, peeling the support, and subtracting the carrier (that is, a resist) Formation, etching and resist stripping). The steps of the manufacturing method are shown in FIGS. 2A and 2B (for ease of illustration, the same symbols are used for components with the same name as in FIGS. 1A and 1B). 2A and 2B are shown for simplicity. It is illustrated that the copper foil 10 with a carrier is provided on one side of the coreless support 18 to form an additional wiring layer 42, but it is desirable to provide the copper foil 10 with a carrier on both sides of the coreless support 18 to form a buildup. Wiring layer 42. In the example shown in FIGS. 2A and 2B, first, a copper foil 10 with a carrier having a carrier 12, a release layer 14, and an ultra-thin copper layer 16 in order are prepared, and the copper foil 10 with a carrier is laminated on the side of the ultra-thin copper layer 16 on On a coreless support 18 such as a prepreg. Next, except that the formation of the first wiring layer 26 has not yet been performed, as in the example shown in FIGS. 1A and 1B, the insulating edge layer 28 forms a patterned second wiring layer 38, and the patterning is repeated as necessary. After the (n-1) th wiring layer (n is an integer of 2 or more), panel plating is performed to form the nth wiring layer 40 (n is an integer of 2 or more). Next, the coreless support 18 is peeled off together with the ultra-thin copper layer 16 to obtain a multilayer wiring board 44 including an additional wiring layer at a stage before forming a specific wiring pattern. A pattern of the etching resist 21 is formed on both surfaces of the obtained multilayer wiring board 44 (that is, the surface of the n-th wiring layer 40 and the surface of the carrier 12). In this way, the multilayer wiring board 44 shielded by the etching resist 21 is stripped of the copper etching electrode etching resist 21, and the first wiring layer 26 is formed on the surface of the multilayer wiring board 44 on the side opposite to the n-th wiring layer 40. A printed wiring board 46 having a specific wiring pattern can be obtained. In this aspect, since the ultra-thin copper layer 16 is not easily broken when the coreless support 18 is peeled off together with the ultra-thin copper layer 16, a part of the residue of the ultra-thin copper layer on the carrier can be effectively avoided. Therefore, an additional step such as a cleaning step to remove a part of the residue or a chemical etching can be eliminated, and the manufacturing efficiency can be improved or the thickness accuracy of the first wiring layer 26 can be improved.

In any of the above states, the printing layout using the coreless build-up method The manufacturing of the wire board is performed by the following steps: (2a) forming an additional wiring layer 42 on the carrier 12 or the ultra-thin copper layer 16 to produce a laminate with the additional wiring layer, and (2b) separating the release layer 14 After the multilayer body with the build-up wiring layer is obtained to obtain the multilayer wiring board 44 including the build-up wiring layer 42, (2c) the multilayer wiring board 44 is processed to obtain a printed wiring board 46. In addition, as described above, the method of the present invention may, of course, be included on one or both sides of the support 18 (such as an insulating resin substrate such as a prepreg or a resin sheet) before forming the build-up wiring layer 42. A step of forming a laminated body by supporting the copper foil 10. The so-called prepreg system is a general term for composite materials in which synthetic resins are impregnated into substrates such as synthetic resin plates, glass plates, glass woven fabrics, glass nonwoven fabrics, and paper. Preferred examples of the insulating resin impregnated in the prepreg are epoxy resin, cyanate resin, bismaleimide resin (BT resin), polyphenylene ether resin, phenol resin, and the like. In addition, examples of the insulating resin constituting the resin sheet include insulating resins such as epoxy resin, polyimide resin, and polyester resin. Each step of (2a) to (2c) will be described below.

(2a) Formation of build-up wiring layer

An additional wiring layer 42 is formed on the carrier 12 or the ultra-thin copper layer 16 to produce a laminated body with the additional wiring layer. In the buried circuit formation method as shown in FIGS. 1A and 1B, an additional wiring layer 42 is formed on the ultra-thin copper layer 16. For example, in addition to the first wiring layer 26 already formed on the ultra-thin copper layer 16, an insulating film 28 and a second wiring layer 38 are sequentially formed to form an additional wiring layer 42. The method of forming the additional layers after the second wiring layer 38 is not particularly limited, and the subtractive method and MSAP (modified semi-additive process) can be used. Method, SAP (semi-additive) method, full-additive method, etc. For example, when laminating a resin layer and a metal foil typified by copper foil at the same time by pressure, the formation of interlayer conduction means such as through-hole formation and panel plating is combined, and the panel plating layer and metal foil can be formed by etching. Wiring pattern. In addition, when only the resin layer is bonded to the surface of the ultra-thin copper layer 16 by pressure or lamination, wiring can also be formed on the surface by a semi-additive method. On the other hand, in the carrier / subtraction processing method as shown in FIGS. 2A and 2B, the build-up wiring layer 42 is formed on the carrier 12. For example, the insulating layer 28 and the second wiring layer 38 are sequentially formed on the carrier 12 to form the build-up wiring layer 42.

The step of forming the build-up wiring layer preferably includes a step of removing the dross using at least one of a chromate solution and a permanganate solution as a resin residue at the bottom of the via hole generated when a via hole is formed by laser or the like ( Rubber slag) removal. The slag removal step is a step of sequentially performing a swelling treatment, a chromic acid treatment or a permanganic acid treatment, and a reduction treatment, and adopts a conventional wet process. According to the method of the present invention, the chromate solution or the permanganate solution in the step of removing the slag can be effectively prevented from entering the interface between the carrier and the extremely thin copper layer. An example of a chromate is potassium chromate. Examples of the permanganate include sodium permanganate and potassium permanganate. In particular, permanganate is preferably used in terms of reducing the discharge of environmentally-loaded substances from the sizing treatment liquid, electrolytic reproducibility, and the like.

Repeat the above steps as needed to obtain a laminate with an additional wiring layer. In this step, it is preferable that the resin layer and the wiring layer including the wiring pattern are alternately stacked to form an additional wiring layer, until the n-th wiring layer 40 (n is an integer of 2 or more) is formed to obtain a laminated body with an additional wiring layer. . The It is only necessary to repeat the steps until a build-up wiring layer having a desired number of layers is formed. At this stage, if necessary, bumps for mounting such as solder resists or studs can also be formed on the outer layer. In addition, the outermost layer of the build-up wiring layer can also be used to form an outer layer wiring pattern in the subsequent processing step (2c) of the multilayer wiring board.

(2b) Separation of laminates with additional wiring layers

The multilayer body with the build-up wiring layer is separated from the release layer 14 to obtain a multilayer wiring board 44 including the build-up wiring layer 42. The separation can be performed by peeling off the extremely thin copper layer 16 and / or the carrier 12.

(2c) Processing of multilayer wiring boards

The multilayer wiring board 44 is processed to obtain a printed wiring board 46. In this step, the multilayer wiring board 44 obtained by the above-mentioned separation step is used to process a desired multilayer printed wiring board. As the method for processing the multilayer wiring board 44 into the multilayer printed wiring board 46, various methods may be used. For example, the carrier 12 or the ultra-thin copper layer 16 located on the outer layer of the multilayer wiring board 44 is etched to form outer-layer circuit wiring, and a multilayer printed wiring board can be obtained. Moreover, the carrier 12 or the ultra-thin copper layer 16 located on the outer layer of the multilayer wiring board 44 can be completely etched and removed, and the multilayer printed circuit board 46 can be directly used in this state. In addition, a photoresist layer can be formed on the outer surface of the carrier 12 or the ultra-thin copper layer 16 on the outer layer of the multilayer wiring board 44 for electrolytic copper plating. After the photoresist is peeled off, the semi-additive method such as submerged etching is equal to The carrier 12 or the ultra-thin copper layer 16 directly forms an outer layer circuit or the like, and forms a multilayer printed wiring board. Furthermore, the carrier 12 or the ultra-thin copper layer 16 located on the outer layer of the multilayer wiring board 44 can be completely etched away. Then, the first wiring layer 26 is soft-etched to obtain the first wiring layer 26 having a recessed portion, which is used as a mounting pad.

[Example]

The present invention is specifically explained by the following examples.

Examples 1 ~ 7

A peeling layer and an ultra-thin copper layer were sequentially formed on the precipitation surface side of the carrier, and then subjected to a rust prevention treatment and a silane coupling agent treatment to produce a copper foil with a carrier. Then, various evaluations were performed about the obtained copper foil with a carrier. The specific sequence is as follows.

(1) Production of carrier

The cathode system uses a titanium rotating electrode with an arithmetic mean roughness Ra (according to JIS B0601-2001) of 0.20 μm, the anode system uses DSA (Dimensionally Stable Anode), and the electrolyte system uses sulfuric acid acid sulfuric acid having the composition shown in Table 1 below. The copper solution was electrolytically produced under the conditions shown in Table 1 to obtain an electrolytic copper foil having a thickness shown in Table 1 as a carrier.

(2) Formation of peeling layer

The precipitated surface of the pickled carrier was immersed in a CBTA (carboxybenzobenzotriazole) concentration of 1 g / L, a sulfuric acid concentration of 150 g / L, and a copper concentration of 10 g / L in an aqueous solution of CBTA at a temperature of 30 ° C for 30 seconds to make CBTA The components are adsorbed on the electrode surface of the carrier. In this way, a CBTA layer is formed on the electrode surface of the carrier as an organic release layer. The thickness of the organic release layer was 8 nm after it was measured by an area weight conversion algorithm.

(3) Formation of auxiliary metal layer

The carrier forming the organic peeling layer was immersed in a solution having a nickel concentration of 20 g / L made of nickel sulfate, and adhered to the organic peeling layer at a thickness of 0.01 at a liquid temperature of 45 ° C., a pH of 3, and a current density of 5 A / dm ² . μm adhesion amount of nickel. In this way, a nickel layer was formed on the organic release layer as an auxiliary metal layer.

(4) Formation of extremely thin copper layer

The carrier forming the auxiliary metal layer is immersed in a copper solution of the composition shown below, and is electrolyzed at a solution temperature of 50 ° C. and a current density of 5 to 30 A / dm ² to form an extremely thin copper layer with a thickness of 3 μm on the auxiliary metal layer.

<Solution composition>

-Copper concentration: 60g / L

-Sulfuric acid concentration: 200g / L

(5) Roughening

The surface of the extremely thin copper layer thus formed is roughened. This roughening treatment is constituted by the following steps: a firing step of depositing fine copper particles on the ultra-thin copper layer, and a plating step to prevent the fine copper particles from falling off. The firing step is a roughening treatment using an acidic copper sulfate solution containing a copper concentration of 10 g / L and a sulfuric acid concentration of 120 g / L at a liquid temperature of 25 ° C and a current density of 15 A / dm ² . The subsequent plating step was performed using an acidic copper sulfate solution containing a copper concentration of 70 g / L and a sulfuric acid concentration of 120 g / L under smooth plating conditions at a liquid temperature of 40 ° C and a current density of 15 A / dm ² .

(6) Anti-rust treatment

The surface of the roughened layer of the obtained copper foil with a carrier was subjected to a rust prevention treatment formed by a zinc-nickel alloy plating treatment and a chromate treatment. First, an electrolytic solution having a zinc concentration of 0.2 g / L, a nickel concentration of 2 g / L, and a potassium pyrophosphate concentration of 300 g / L was used to condition the roughened layer and the carrier at a liquid temperature of 40 ° C and a current density of 0.5 A / dm ² . The surface is zinc-nickel alloy plated. Here, a chromate treatment was performed on the surface subjected to the zinc-nickel alloy plating treatment using a 3 g / L aqueous solution of chromic acid under the conditions of pH 10 and a current density of 5 A / dm ² .

(7) Silane coupling agent treatment

An aqueous solution containing 2 g / L of γ-glycidyloxypropyltrimethoxysilane was adsorbed on the surface of the ultra-thin copper layer of the copper foil with a carrier, and the water was evaporated by an electric heater to perform a silane coupling agent treatment. At this time, the silane coupling agent treatment was not performed on the carrier side.

(8) Evaluation

The thus obtained copper foil with a carrier was evaluated for various characteristics as follows.

<Surface properties parameter>

The copper foil was peeled off from the self-supporting carrier, and a surface roughness tester (SE3500, manufactured by Kosaka Research Institute Co., Ltd.) was used to measure the peak count Pc on the surface of the peeling layer side of the carrier and the average height Wc of the undulation curve by the following conditions And ten-point average roughness Rz. The results are summarized in Table 2.

[Peak Count Pc]

-Based on specifications: JIS B0601-2001 (ISO 4287-1997)

-Cut-off value: 0.8mm

-Evaluation length: 0.8mm

[Average height Wc]

-Based on specifications: JIS B0601-2001 (ISO 4287-1997)

-Cut-off value: fh 0.8mm / fl 8.0mm

-Evaluation length: 16mm

[Ten-point average roughness Rz]

-Based on specifications: JIS B0601-1994

-Cut-off value: 0.8mm

-Evaluation length: 0.8mm

<Amount of Chemical Erosion>

A copper-clad laminated board was produced using the copper foil with a carrier, and the amount of chemical solution erosion was investigated for the copper-clad laminated board. First, an ultra-thin copper layer with a copper foil with a carrier was laminated on a prepreg (manufactured by Mitsubishi Gas Chemical Co., Ltd., FR-4) and pressurized at 185 ° C for 90 minutes. The end face of the copper-clad laminated board thus obtained was cut by a Sha cutter. Use the sodium permanganate solution to remove the glue residue on the cut copper-clad laminated board.

This slag removal treatment is performed by using the following processing liquids of Rohm and Haas Electronic Materials Co., Ltd. and sequentially performing the following processes.

[Swelling treatment]

-Treatment liquid: CIRCUPOSIT MLB CONDITIONER 211- 120mL / L and CIRCUPOSIT Z-100mL / L

-Processing conditions: immersion at 75 ° C for 5 minutes

[Permanganic acid treatment]

-Treatment liquid: CIRCUPOSIT MLB PROMOTOR 213A-110mL / L and CIRCUPOSIT MLB PROMOTOR 213B-150mL / L

-Processing conditions: Immersion at 80 ° C for 5 minutes

[Neutralization treatment]

-Treatment liquid: CIRCUPOSIT MLB NEUTRALIZER 216-2-200mL / L

-Processing conditions: immersion at 45 ° C for 5 minutes

Subsequently, the carrier was peeled from the copper-clad laminated board, and the amount of etching on the surface of the ultra-thin copper layer was measured with a microscope observation. Because the area of the surface of the ultra-thin copper layer penetrates into the sodium permanganate solution, the measurement of the above-mentioned erosion amount is performed by measuring the maximum reach distance from the end of the ultra-thin copper layer to the discolored area on the surface of the ultra-thin copper layer. The results are summarized in Table 2.

<Ultra-thin copper layer cracked>

A copper-clad laminated board was produced using a copper foil with a carrier, and the degree of cracking of the ultra-thin copper layer due to carrier peeling was investigated. First, an ultra-thin copper layer with a copper foil with a carrier was laminated on a prepreg (manufactured by Mitsubishi Gas Chemical Co., Ltd., FR-4) and pressurized at 185 ° C for 90 minutes. The carrier was peeled from the copper-clad laminated board thus obtained. The backlight was irradiated to the ultra-thin copper layer in a dark room, and the number of cracks of the ultra-thin copper layer with a length of 5 μm or more was measured and converted into a number per 1 m ² . The results are summarized in Table 2.

<Evaluation of Defects / Dent of Wiring Patterns of Embedded Circuits>

To investigate the over-etching of the wiring pattern on the surface of the coreless support which is caused by the cracking of the above-mentioned extremely thin copper layer (that is, the embedded circuit as the build-up wiring), the embedded circuit formation method was used to make and evaluate the samples as follows.

Carrier copper foil with a carrier was laminated on 4 pieces of prepreg (manufactured by Mitsubishi Gas Chemical Co., Ltd., FR-4), and pressed at 185 ° C for 90 minutes. Subsequently, a 15 μm thick photoresist was used to form a wiring pattern area (size 10 mm x 20 parts) with a line / space (L / S) of 12 μm / 12 μm, and a copper plating was formed with a copper sulfate plating solution to a thickness of 12 μm. . Furthermore, using a photoresist stripping solution, the photoresist was peeled at 45 ° C. for 5 minutes to form a copper plating pattern. Next, a layer of prepreg (FR-4, manufactured by Mitsubishi Gas Chemical Co., Ltd.) was laminated, and pressed at 185 ° C for 90 minutes to form a layer of build-up. Subsequently, the above-mentioned coreless support of glass was obtained as a build-up wiring board. For the ultra-thin copper layer exposed on the surface of the build-up wiring board, the sulfuric acid / hydrogen peroxide aqueous solution was spray-washed, and the ultra-thin copper layer was removed by etching. By observing the circuit thus buried in the build-up layer by a 200-fold microscope, the incidence of defects / depressions in the wiring pattern was calculated. The results are summarized in Table 2.

result

The evaluation results obtained for Examples 1 to 7 are summarized in Table 2.

From the results shown in Table 2, by using a copper foil with a carrier having a Wc × Pc in the range of 20 to 50 μm on the side of the release layer side of the carrier, the amount of chemical solution erosion was significantly reduced and the ultra-thin copper layer was reduced. This also significantly reduces the bad wiring pattern of the embedded circuit.

Claims (7)

A method, which is a method for manufacturing a printed wiring board, which includes the following steps: preparing a copper foil with a carrier, the copper foil with a carrier having a carrier, a release layer, and an ultra-thin copper layer in this order; and the carrier On the surface of the aforementioned peeling layer side, where the average height Wc of the undulating curve requirements measured in accordance with B0601-2001 and the product Wc × Pc of the peak count Pc is 20 to 50 μm, an increase is formed on the aforementioned carrier or an extremely thin copper layer Steps of forming a multilayer body with an additional wiring layer by separating the wiring layers, separating the multilayer body with the additional wiring layer from the release layer to obtain a multilayer wiring board including the additional wiring layer, and processing the multilayer A step of obtaining a printed wiring board from the wiring board. The method according to claim 1, further comprising the step of forming the laminated body by laminating the copper foil with a carrier on one or both sides of the support before forming the additional wiring layer. The method according to claim 1 or 2, wherein in the surface of the release layer side of the carrier, the Wc is 0.5 to 1.0 μm. The method according to claim 1 or 2, wherein in the surface of the release layer side of the carrier, the Pc is 22 to 65. The method according to claim 1 or 2, wherein the ten-point average roughness Rz measured in accordance with JIS B0601-1994 in the surface of the aforementioned release layer side of the aforementioned carrier is 1.5 to 6.5 μm. The method according to claim 1 or 2, wherein in the surface of the release layer side of the carrier, the Wc × Pc is 26 to 30 μm. The method as claimed in claim 1 or 2, wherein the step of forming the aforementioned build-up wiring layer includes a step of removing slag using at least one of a chromate solution and a permanganate solution.