TWI623109B - Crystalline solar silicon wafer with low gloss and low reflectivity - Google Patents

Abstract

A crystalline silicon solar silicon wafer with low gloss and low reflectivity includes a wafer body and a micro-scale structure. A plurality of micro-scale holes are distributed in a row shape by a roughening process. The surface of the wafer body constitutes the micro-scale structure; and a nano-scale structure is formed by uniformly dispersing a plurality of nano-scale holes in the micro-scale structure and a local surface of the wafer body through a roughening process. Multi-scale roughening and forming a composite structure with the micro-scale structure. In this way, the present invention uses a micro-scale hole-shaped structure as a substrate to reduce the surface gloss of the wafer (85 ° <50 GU), and then etches a nano-scale hole-like surface structure on the substrate to form a multi-scale roughening to form a composite. Structure to reduce wafer surface reflectivity.

Description

Crystalline solar silicon wafer with low gloss and low reflectivity

The present invention relates to a crystalline silicon solar silicon wafer with low gloss and low reflectivity, and more particularly to a method for reducing the surface gloss of a wafer by using a micro-scale hole-shaped arrangement as a substrate, and then etching the substrate Nano-scale hole-like surface structure to form multi-scale roughening, forming a composite structure to reduce wafer surface reflectivity.

At present, the mainstream of commercial solar cells is crystalline silicon solar cells, which are divided into monocrystalline silicon (c-Si), mono-like c-Si, and polycrystalline (m-Si) crystalline silicon solar cells. Polycrystalline silicon solar cells made from round materials have fast wafer and cell manufacturing procedures and are cheaper than monocrystalline crystalline silicon solar cells. They are currently the highest market share for commercial solar cells. Although monocrystalline crystalline silicon solar cells have been proven to have higher photoelectric conversion efficiency than polycrystalline solar cells, uneven surface appearance has been one of the main reasons limiting their development.

Polycrystalline silicon solar cells are currently commercially used in large-scale production of wet acid etching (mixed acid of nitric acid and hydrofluoric acid) to produce a surface texture structure, which has a very high competitive advantage in terms of process time cost; however, the use of wet acid When the surface woven texture structure is produced by etching, the texture surface is disordered, showing small white-gray grains. Moreover, for some wafers whose surface is too flat (low surface roughness), such as: For diamond wire cutting, the wet acid etching method cannot effectively reduce the light reflectance, which is the most important reason to limit its further improvement.

Diamond wire cut has lower manufacturing cost than traditional slurry cut. In the past few years, the solar industry has continuously tried diamond wire cutting to reduce manufacturing costs. However, traditional wet acid etching cannot be used effectively. Diamond wire-cut solar silicon wafers have low-reflection and low-gloss morphologies. Therefore, considering efficiency and appearance, they have not been accepted by most customers.

As shown in Figure 5, it is a comparison of silicon wafers with different slicing methods. Figure (B) shows the appearance of a commercial diamond wire slice. Figure (A) shows a traditional silicon carbide mortar slice with a relatively high average gloss and reflectance. There are many, the comparison of the average reflectance and the average gloss value is shown in Table 6 below.

Table 6

The commercial wet acid etching process is shown in Figure 6. Its etching weight is about 0.32 to 0.42 g. From Table 7 below, we can understand that the traditional wet acid etching cannot effectively reduce the average reflectance and gloss of polycrystalline silicon wafers with diamond wire slicing. Degree, which limits the improvement of battery efficiency.

                            Table seven

In recent years, in order to get rid of the traditional wet acid etching that cannot effectively reduce the reflectance, many researches have been directed to the use of dry etching methods such as reactive ion etching (Ractive Ion Etching, RIE) to produce nano-scale (roughness less than 900nm) surface structures To get lower reflectivity. However, using different process conditions to form a nanostructure on the surface of the diamond wire slice separately, it can be seen from Table 8 and Table 7 that although the average reflectance of the surface can be effectively reduced, the surface still has an excessively high average gloss; Therefore, the existence of a nanostructure alone cannot obtain a low gloss and low reflection surface appearance.

                           Table eight

In view of the two major issues currently encountered in the commercial use of silicon wafer silicon wafers:

1. Traditional wet acid etching cannot increase the amount of incident light more effectively, which leads to the limitation of the space for efficiency improvement.

2. With high surface gloss.

Therefore, ordinary users cannot meet the needs of users in actual use.

The main purpose of the present invention is to overcome the problems encountered in the conventional art and provide a micrometer-scale hole-shaped structure as a substrate to reduce the surface gloss of the wafer, and then etch a nano-scale hole-like surface structure on the substrate to form it. Multi-scale roughening to form a composite structure to reduce wafer surface reflectance with low gloss and low reflectivity crystalline silicon solar silicon wafers.

In order to achieve the above object, the present invention is a crystalline silicon solar silicon wafer with low gloss and low reflectivity, which includes: a wafer body; a micron-scale structure; a plurality of micron-sized holes are arranged by a roughening process; Holes are distributed on the surface of the wafer body to form the micro-scale structure; and a nano-scale structure is formed by uniformly dispersing a plurality of nano-scale holes in the micro-scale structure and a partial surface of the wafer body through a roughening process. Multi-scale roughening and forming a composite structure with the micro-scale structure.

In the above embodiments of the present invention, the wafer system is made of polycrystalline silicon (m-Si) or mono-like c-Si material.

In the above embodiments of the present invention, the roughening treatment of the micron-scale structure is performed by physical etching or chemical etching of the surface of the wafer body; the physical etching is laser, sandblasting, sputtering, or ion beam Ion Beam Etching, the chemical etching is a wet chemical acid or alkali etching with an etching mask, and the wet chemical used is a combination of multiple acids or alkalis, and the acid wet chemical is The nitric acid, acetic acid, hydrofluoric acid, sulfuric acid, or any combination of mixed acids, and the alkali wet chemical is potassium hydroxide or sodium hydroxide.

In the above embodiment of the present invention, the roughening treatment of the nano-scale structure is performed by plasma etching (Reactive Ion Etching, Plasma Etching) or reactive ion etching (Reactive Ion Etching, RIE). .

In the above embodiment of the present invention, the nano-scale structure is formed by dry etching with a gas containing chlorine-based gas, fluorine-based gas, oxygen-based gas, and hydrogen gas.

In the above embodiments of the present invention, the fluorine-containing gas system may be sulfur hexafluoride (SF ₆ ), carbon tetrafluoride (CF ₄ ), nitrogen trifluoride (NF ₃ ), and fluorine gas (F ₂ At least one kind of gas of), and the chlorine-containing gas system may be at least one kind of gas of chlorine (Cl ₂ ), carbon tetrachloride (CCl ₄ ), and trichloromethane (CHCl ₃ ), and the The oxygen-containing gas system may be at least one gas of at least one of nitrous oxide (N ₂ O), oxygen (O ₂ ), and ozone (O ₃ ).

In the above embodiments of the present invention, the shape of the micron-sized holes in the micron-scale structure may be circular, polygonal, concentric circles, geometrical shapes, or a combination of different shapes.

In the above embodiment of the present invention, the average distance between the geometric centers of the plurality of micron-sized holes adjacent to the micron-sized holes in each column is less than 200 micrometers (μm).

In the above embodiment of the present invention, the plurality of micron-sized holes are arranged in a straight line, a regular repeating arrangement, a staggered arrangement, or a uniform plum-like arrangement between the columns.

In the above embodiments of the present invention, the diameter of each micron-sized hole in the micron-sized structure is between 5 and 200 μm, and the vertical depth of each micron-sized hole is between 3 and 30 μm.

In the above embodiments of the present invention, the micron-scale structure formed by the plurality of micron-sized hole arrays accounts for more than 50% of the surface area of the wafer body.

In the above embodiments of the present invention, the average roughness of the nano-scale structure is between 5 and 900 nm.

In the above embodiments of the present invention, the diameter of each nano-scale hole in the nano-scale structure is between 300 and 500 nm, and the vertical depth of each nano-scale hole is less than 900 nm.

In the above embodiments of the present invention, the surface gloss is below 50 G.U. at a light incident angle of 85 °.

In the above embodiments of the present invention, the reflectance between the 300-1100 nm band of the solar spectrum can be reduced.

In addition to the above implementation form, the crystalline silicon solar silicon wafer with low gloss and low reflectivity provided by the present invention may also be another implementation form, which includes: a wafer body; a micron-scale structure, which is formed by a rough The chemical treatment enables a plurality of micron-sized holes to be arranged in rows on the surface of the wafer body to form the micron-level structure; and a plurality of anti-reflection layers are formed on the surface of the wafer body and cover the micron-sized holes in the micron-level structure. .

In the above embodiments of the present invention, the multilayer anti-reflection layer is silicon oxide (SiO _x ), silicon nitride (SiN _x ), or titanium dioxide (TiO ₂ ).

In the above embodiment of the present invention, the average distance between the geometric centers of the plurality of micron-sized holes in each row of adjacent micron-sized holes is less than 200 μm.

In the above embodiments of the present invention, the diameter of each micron-sized hole in the micron-sized structure is between 5 and 200 μm, and the vertical depth of each micron-sized hole is between 3 and 30 μm.

In the above embodiments of the present invention, the micron-scale structure formed by the plurality of micron-sized hole arrays accounts for more than 50% of the surface area of the wafer body.

‧‧‧Chip body

2‧‧‧ micron structure

21‧‧‧micron class holes

‧‧‧ nanometer structure

31‧‧‧ Nano Class Holes

4‧‧‧ anti-reflective layer

FIG. 1 is a partially enlarged schematic diagram of the structure of the first embodiment of the present invention.

Figure 2A is a SEM (a) image of the nano-scale structure of the present invention.

Figure 2B is a SEM (II) image of the nano-scale structure of the present invention.

FIG. 3 is a schematic diagram of a manufacturing process of the first embodiment of the present invention.

Fig. 4 is a schematic cross-sectional view showing a structure of a second embodiment of the present invention.

Figure 5 is a diagram of a silicon wafer using different slicing methods.

Figure 6 is a schematic diagram of the traditional polycrystalline crystalline silicon solar cell manufacturing process.

Please refer to "Figures 1 to 4", which are respectively a partially enlarged schematic diagram of the structure of the first embodiment of the present invention, a SEM (a) diagram of the nano-level structure of the present invention, and a SEM of the nano-level structure of the present invention. (2) A schematic diagram of a manufacturing process of the first embodiment of the present invention, and a structural cross-sectional diagram of the second embodiment of the present invention. As shown in the figure, the present invention is a crystalline silicon solar silicon wafer with low gloss and low reflectivity, which includes a wafer body 1, a micro-scale structure 2, and a nano-scale ) Structure 3.

The above mentioned chip body 1 may be polycrystalline silicon (m-Si) or mono-like c-Si material.

The micron-level structure 2 is subjected to a roughening treatment, such as physical etching or chemical etching (with an etching mask), so that a plurality of micron-sized holes 21 are distributed in a row-like shape on the surface of the wafer body 1 between the columns. It is straight, regularly repeated, staggered, or even plum-shaped (as shown in Figure 1), and the average distance between the geometric centers of adjacent micron-sized holes 21 in each column is less than 200 microns (μm) Thus, a micron-scale structure 2 that accounts for more than 50% of the surface area of the wafer body 1 is formed. The plurality of micron-sized holes 21 are semi-concave holes, and the shape can be circular, polygonal, concentric circles, geometric figures, or a combination of various different figures. The diameter of each micron-sized hole 21 is between 5 and 200. μm, and the vertical depth of each micron-level hole 21 is between 3 and 30 μm. Wherein, the physical etching is laser, sandblasting, sputter etching, or ion beam etching (Ion Beam Etching). The chemical etching is a wet chemical acid or alkali etching with an etching mask. The wet chemical is a combination of multiple acids or bases, and the acid wet chemical is nitric acid, acetic acid, hydrofluoric acid, sulfuric acid, or a mixed acid of any combination. The wet chemical of alkali is hydrogen Potassium oxide, or sodium hydroxide.

The nano-scale structure 3 is subjected to a roughening treatment, such as plasma etching (Plasma Etching) or reactive ion etching (Reactive Ion Etching, RIE), so that the plurality of nano-scale holes 31 are uniformly dispersed in the micro-scale structure. 2 forms a multi-scale roughening with a partial surface of the wafer body 1 and forms a composite structure with the micro-scale structure 2. The nanoscale structure 3 can be clearly seen through a scanning electron microscope (Scanning Electron Microscope, SEM). The nanoscale pore-like surface (as shown in Figures 2A and 2B) has an average roughness (Roughness) of 5 ～ 900 nm, the diameter of each nano-scale hole 31 is between 300-500 nm, and the vertical depth of each nano-scale hole 31 is less than 900 nm. Among them, the nano-scale structure 3 is formed by dry etching with a gas containing chlorine-based gas, a fluorine-based gas, an oxygen-based gas, and a hydrogen gas. The fluorine-containing gas system can be six At least one kind of gas of sulfur fluoride (SF ₆ ), carbon tetrafluoride (CF ₄ ), nitrogen trifluoride (NF ₃ ), and fluorine gas (F ₂ ), and the chlorine-containing gas system can be: At least one gas of chlorine gas (Cl ₂ ), carbon tetrachloride (CCl ₄ ), and trichloromethane (CHCl ₃ ), and the oxygen-containing gas system may be nitrous oxide (N ₂ O), At least one gas of oxygen (O ₂ ) and ozone (O ₃ ). If so, a completely new crystalline silicon solar silicon wafer with low gloss and low reflectance is formed by the above disclosed device.

In a specific embodiment, the fabrication process of the micrometer and nanometer composite structure of the solar silicon wafer of the present invention is shown in Fig. 3. Compared with the conventional technology, as can be seen from Table 1 below, the present invention can obtain a low average reflection at the same time. Rate and gloss.

Table I

In addition to the composite structure type mentioned in the first embodiment, the present invention can also be the structure type of the second embodiment. As shown in FIG. 4, the invention includes a wafer body 1 and a micron-scale structure 2. And a multilayer anti-reflection layer 4.

The wafer body 1 and the micro-scale structure 2 mentioned above are as described above.

The multilayer anti-reflection layer 4 is formed on the surface of the wafer body 1 and covers a plurality of micron-sized holes 21 in the micron-sized structure 2. The multilayer anti-reflection layer is silicon oxide (SiO _x ), silicon nitride (SiN _x ), or titanium dioxide (TiO ₂ ).

Even if the present invention only has a microstructure, the existence of the microstructure can effectively make a low surface gloss solar cell; the microstructures are summarized in the following Tables 2 and 3 as the structure depth and the distance between the structures reflect the reflectivity and the surface. The effect of gloss can be seen from the results presented in Tables 2 and 3. Under the fixed microstructure width of 20 μm and 50 μm, respectively, as the depth of the microstructure increases, the surface gloss and reflectance can be reduced simultaneously; instead Ground, as the distance between microstructures increases, so does the gloss and reflectivity. Compared with the existence of the aforementioned single surface micron structure, Tables 4 and 5 below show the existence of composite structures, which can more effectively reduce the surface gloss and surface reflectance. Table 4 is based on Table 2 to form the surface composite size on the wafer. The structure forms its optical data. Table 5 is based on Table 3 to form its optical data on the wafer to form a composite size structure on the surface.

                        Table II

                           Table three

                          Table four

                          Table five

From the above, it can be known that the composite size surface structure of the present invention can effectively reduce the reflectance and gloss of incident light (below 50 GU at a light incident angle of 85 °), so as to solve the current commercial use of silicon wafer silicon wafers. There are two main problems that cannot increase the amount of incident light more effectively, which leads to the limitation of the space for efficiency improvement, and high surface gloss.

In this way, the present invention uses a micro-scale hole-like arrangement as a substrate to reduce the surface gloss of the wafer, and a nano-scale structure to reduce the wafer surface reflectance; wherein the nano-scale hole-like surface is etched on the substrate to form multi-scale roughness To form a solar cell structure with a composite structure, which has the following characteristics:

1. Effectively reduce surface gloss (85 ° <50 G.U.).

2. Effectively reduce the reflectivity of the solar spectrum from 300 to 1100 nm.

3. Increase the contact area between the electrode and the silicon wafer and reduce the battery contact resistance.

To sum up, the present invention is a crystalline silicon solar silicon wafer with low gloss and low reflectivity, which can effectively improve various shortcomings of conventional use. The micro-scale hole-shaped structure is used as a substrate to reduce the surface gloss of the wafer. Nano-scale hole-like surface structure is etched on the substrate to form a multi-scale roughening, and a composite structure is formed to reduce the surface reflectance of the wafer, thereby further reducing the surface reflectivity of the wafer. The invention of invention can be more advanced, more practical, and more in line with the needs of users. It has indeed met the requirements for invention patent applications, and filed patent applications according to law.

However, the above are only the preferred embodiments of the present invention, and the scope of implementation of the present invention cannot be limited by this; therefore, any simple equivalent changes and modifications made in accordance with the scope of the patent application and the contents of the invention specification of the present invention , All should still fall within the scope of the invention patent.

Claims (19)

A crystalline silicon solar silicon wafer with low gloss and low reflectivity. The system includes: a wafer body, which is made of polycrystalline silicon (m-Si) or mono-like c-Si material; A scale structure is formed by a roughening process to distribute a plurality of micron-sized holes in a row on the surface of the wafer body to form the micron structure; and a nano-scale structure is formed by a roughening The treatment enables a plurality of nano-scale holes to be uniformly dispersed in the micro-scale structure and a local surface of the wafer body to form a multi-scale roughening, and forms a composite structure with the micro-scale structure. The crystalline silicon solar silicon wafer with low gloss and low reflectivity according to item 1 of the scope of the patent application, wherein the roughening treatment of the micron structure is physical etching or chemical etching of the surface of the wafer body; the physical etching It is laser, sandblasting, sputter etching, or ion beam etching (Ion Beam Etching). The chemical etching is a wet chemical acid or alkali etching with an etching mask, and the wet chemicals used It is a combination of multiple acids or bases, and the wet chemical of acid is nitric acid, acetic acid, hydrofluoric acid, sulfuric acid, or a mixed acid of any combination. The wet chemical of alkali is potassium hydroxide or hydrogen Sodium oxide. The crystalline silicon solar silicon wafer with low gloss and low reflectance according to item 1 of the scope of the patent application, wherein the roughening treatment of the nano-scale structure is performed by plasma etching (Plasma Etching) or reactive ions Etching (Reactive Ion Etching, RIE) the micro-scale structure and a partial surface of the wafer body. The crystalline silicon solar silicon wafer with low gloss and low reflectance according to item 3 of the scope of the patent application, wherein the nano-scale structure is obtained by using a chlorine-based gas, a fluorine-based gas, and an oxygen-based gas. And hydrogen gas dry etching. The crystalline silicon solar silicon wafer with low gloss and low reflectance according to item 4 of the scope of the patent application, wherein the fluorine-containing gas system may be sulfur hexafluoride (SF ₆ ), carbon tetrafluoride (CF ₄ ), at least one kind of gas of nitrogen trifluoride (NF ₃ ), and fluorine gas (F ₂ ), and the chlorine-containing gas system may be chlorine (Cl ₂ ), carbon tetrachloride (CCl ₄ ) And at least one gas of trichloromethane (CHCl ₃ ), and the oxygen-containing gas system may be at least one of nitrous oxide (N ₂ O), oxygen (O ₂ ), and ozone (O ₃ ) The above gases. The crystalline silicon solar silicon wafer with low gloss and low reflectance according to item 1 of the scope of the patent application, wherein the micron-sized holes in the micron-sized structure may be circular, polygonal, concentric circles, geometric figures , Or a combination of different graphics above. The crystalline silicon solar silicon wafer with low gloss and low reflectance according to item 1 of the scope of the patent application, wherein the average distance between the plurality of micron-sized holes in the geometric centers of adjacent micron-sized holes in each row is less than 200 microns (μm). The crystalline silicon solar silicon wafer with low gloss and low reflectance according to item 1 of the scope of the patent application, wherein the plurality of micron-sized holes are arranged in rows, regularly repeated arrangements, staggered arrangements, or between columns Arranged in a uniform plum shape. The crystalline silicon solar silicon wafer with low gloss and low reflectance according to item 1 of the scope of the patent application, wherein the diameter of each micron-level hole in the micron-level structure is between 5 and 200 μm, and each micron-level The vertical depth of the holes is between 3 ~ 30μm. According to the crystalline silicon solar silicon wafer with low gloss and low reflectivity described in item 1 of the scope of the patent application, the micron-scale structure formed by the plurality of micron-sized hole arrays accounts for more than 50% of the surface area of the wafer body. According to the crystalline silicon solar silicon wafer with low gloss and low reflectivity described in item 1 of the scope of the patent application, the average roughness of the nano-scale structure is between 5 and 900 nm. The crystalline silicon solar silicon wafer with low gloss and low reflectance according to item 1 of the scope of the patent application, wherein the diameter of each nano-level hole in the nano-level structure is between 300 and 500 nm, and each The vertical depth of nano-scale holes is less than 900nm. According to the crystalline silicon solar silicon wafer with low gloss and low reflectivity described in item 1 of the scope of the patent application, its surface gloss is below 50 G.U. at a light incident angle of 85 °. The crystalline silicon solar silicon wafer with low gloss and low reflectance as described in item 1 of the scope of the patent application can reduce the reflectance between 300 and 1100 nm of the solar spectrum. A crystalline silicon solar silicon wafer with low gloss and low reflectivity, comprising: a wafer body, which is polycrystalline silicon (m-Si) or mono-like c-Si material; a micron-scale structure, A plurality of micron-sized holes are distributed in a row shape on the surface of the wafer body by a roughening process to form the micron-sized structure; a nanometer-level structure is formed by uniformly dispersing the plurality of nanometer-sized holes in the surface by a roughening process. The micro-scale structure forms a multi-scale roughening with a partial surface of the wafer body and forms a composite structure with the micro-scale structure; and a multilayer anti-reflection layer is formed on the surface of the wafer body and covers the surface of the composite structure. on. The crystalline silicon solar silicon wafer with low gloss and low reflectance according to item 15 of the scope of the patent application, wherein the multilayer anti-reflection layer is silicon oxide (SiO _x ), silicon nitride (SiN _x ), or titanium dioxide (TiO ₂ ). According to the crystalline silicon solar silicon wafer with low gloss and low reflectivity described in item 15 of the scope of the patent application, wherein the average distance between the plurality of micron-sized holes in the geometric centers of adjacent micron-sized holes in each column is less than 200 μm. The crystalline silicon solar silicon wafer with low gloss and low reflectance according to item 15 of the scope of the patent application, wherein the diameter of each micron-level hole in the micron-level structure is between 5 and 200 μm, and each micron-level The vertical depth of the holes is between 3 ~ 30μm. According to the crystalline silicon solar silicon wafer with low gloss and low reflectivity described in item 16 of the scope of the patent application, the micron-scale structure formed by the array of multiple micron-sized holes occupies more than 50% of the surface area of the wafer body.