TWI611520B - Package structure and manufacturing method thereof - Google Patents

Abstract

A package structure and a method of fabricating the same. The package structure includes a germanium substrate having a recess, a wafer, a reconfigurable layer structure, and solder balls. A wafer is disposed in the recess. The reconfiguration layer structure is disposed on the germanium substrate and the wafer, and is electrically connected to the wafer. The solder ball is disposed on the reconfiguration layer structure and electrically connected to the reconfiguration layer structure.

Description

Package structure and manufacturing method thereof

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a package structure and a method of fabricating the same.

In the current fan-out wafer level packaging (FOWLP) technology, a moiding compound is usually used to coat and fix the wafer. For example, a fan-out wafer level packaging process includes the steps of forming a package-coated encapsulant on a carrier substrate after attaching the wafer to be packaged to the carrier substrate. Next, a portion of the encapsulant is removed until a Cu pillar that is attached to the pad of the wafer is exposed. Thereafter, a re-distribution layer (RDL) structure is formed on the encapsulant, and a solder ball electrically connected to the re-configuration layer structure is formed.

In the above step of exposing the copper pillar, the encapsulation colloid above the wafer is usually removed by grinding to expose the top surface of the copper pillar. However, during the grinding process, it is difficult to control the degree of grinding, which often leads to insufficient grinding or excessive damage of the copper column due to excessive grinding.

In addition, after forming the encapsulant of the wafer on the carrier substrate, the resulting package structure has a warpage problem due to the difference in material between the carrier substrate and the encapsulant.

The present invention provides a package structure in which a wafer is disposed in a recess in a ruthenium substrate.

The present invention provides a method of fabricating a package structure in which a wafer is formed in a recess in a germanium substrate.

The package structure of the present invention includes a germanium substrate having a recess, a wafer, a reconfigurable layer structure, and solder balls. A wafer is disposed in the recess. The reconfiguration layer structure is disposed on the germanium substrate and the wafer, and is electrically connected to the wafer. The solder ball is disposed on the reconfiguration layer structure and electrically connected to the reconfiguration layer structure.

In an embodiment of the package structure of the present invention, the reconfiguration layer structure includes a dielectric layer and a wiring layer in the dielectric layer, and the dielectric layer fills the recess.

In an embodiment of the package structure of the present invention, the top surface of the wafer and the surface of the crucible substrate located around the recess are, for example, coplanar.

In an embodiment of the package structure of the present invention, a warpage adjustment layer is further disposed on the surface of the germanium substrate and the sidewalls and the bottom surface of the recess.

In an embodiment of the package structure of the present invention, an adhesive layer is further disposed between the wafer and a bottom surface of the recess.

The manufacturing method of the package structure of the present invention comprises the steps of: forming a recess in the germanium substrate; disposing the wafer in the recess; forming a reconfiguration layer structure on the germanium substrate and the wafer, the reconfiguring a layer structure electrically connected to the wafer; and forming a solder ball on the reconfigured layer structure.

In an embodiment of the method of fabricating the package structure of the present invention, after forming the solder ball, further comprising removing a portion of the germanium substrate under the recess.

In an embodiment of the method of fabricating a package structure of the present invention, the reconfiguration layer structure includes a dielectric layer and a wiring layer in the dielectric layer, and the dielectric layer fills the recess.

In an embodiment of the method for fabricating a package structure of the present invention, after forming the recess and before setting the wafer, further comprising forming on a surface of the germanium substrate and sidewalls and a bottom surface of the recess Warp adjustment layer.

In an embodiment of the method of fabricating the package structure of the present invention, an adhesive layer is further formed on the bottom surface of the wafer after forming the recess and before setting the wafer.

Based on the above, the present invention places the wafer in the recess of the ruthenium substrate, and omits the formation of the encapsulant, thereby avoiding the problem that the encapsulation colloid is ground to cause damage or insufficient degree of polishing of the copper pillar. In addition, since there is no encapsulant in the package structure, the problem of warpage of the package structure due to material difference between the encapsulant and the wafer can be avoided.

The above described features and advantages of the invention will be apparent from the following description.

1A to 1D are schematic cross-sectional views showing a manufacturing process of a package structure according to an embodiment of the invention. First, referring to FIG. 1A, a groove 102 is formed in the ruthenium substrate 100. The germanium substrate is, for example, a germanium wafer. The recess 102 is for receiving a wafer to be packaged. The method of forming the recess 102 is, for example, sequentially performing a lithography process and an etching process on the germanium substrate 100. Further, in the present embodiment, in the process of forming the groove 102, the groove as the alignment mark 104 may be simultaneously formed in the ruthenium substrate 100. The alignment mark 104 may be formed at a scribe line of the ruthenium substrate 100. In the subsequent placement of the wafer in the recess 102, the wafer can be accurately placed in the desired position by the alignment mark 104. Further, in the present embodiment, the depth of the groove 102 is not particularly limited as long as the groove 102 can properly accommodate the wafer, which will be described later.

Next, in the present embodiment, the warpage adjustment layer 106 can be selectively formed on the tantalum substrate 100. The warpage adjusting layer 106 is, for example, an oxide layer formed by, for example, depositing an oxide material on the germanium substrate 100 by a chemical vapor deposition process, that is, the warpage adjusting layer 106 is formed on the surface of the germanium substrate 100 and recessed. The side wall and the bottom surface of the groove 102. In the present embodiment, since the size of the alignment mark 104 is much smaller than the size of the groove 102, the warp adjustment layer 106 formed is filled with the groove as the alignment mark 104. The warp adjustment layer 106 can be used to adjust the warpage of the resulting package structure. When it is foreseen that the finally formed package structure has a positive warpage, the chemical vapor deposition process conditions that can cause the germanium substrate 100 to have a negative warpage are selected to form the warpage adjustment layer 106 to improve the final formed shape. The warpage of the package structure. On the other hand, when it is foreseen that the finally formed package structure has a negative warpage, the warpage adjustment layer 106 is formed by selecting a chemical vapor deposition process condition which allows the tantalum substrate 100 to have a positive warpage.

Then, referring to FIG. 1B, an adhesive layer 108 can be formed on the back surface 110b of the wafer 110 to be packaged. The material of the adhesive layer 108 may be a general die attach film (DAF) which is a double-sided bonding material. The method of forming the adhesive layer 108 on the back surface 110b of the wafer 110 to be packaged is to polish the wafer to a desired thickness, attach the DAF and then perform dicing to form a plurality of wafers 110 to which the DAF is attached. The adhesive layer 108 is used to fix the wafer 110 to be packaged in the recess 102. Next, the wafer 110 to be packaged is placed in the recess 102. At this time, the wafer 110 can be positioned at the correct position in the recess 102 by the alignment mark 104 and fixed in the recess 102 by the adhesive layer 108. In the present embodiment, the wafer 110 has a front surface 110a and a back surface 110b which are opposed to each other. The front surface 110a of the wafer 110 has been formed with a desired component and wiring structure (not shown), and the uppermost end has a pad 112 electrically connected to the component and the wiring structure, that is, the front surface 110a is the active of the wafer 110. An adhesive layer 108 is attached to the back surface 110b of the wafer 110. The wafer 110 can be electrically connected to external components by pads 112. After alignment by the alignment mark 104, the wafer 110 is placed in the groove 102 with the back surface 110b facing the bottom surface of the groove 102. In FIG. 1B, two wafers 100 are illustrated, but are merely exemplary and are not intended to limit the invention in any way.

In the present embodiment, after the wafer 110 is placed in the recess 102, the top surface of the wafer 110 (which may be considered herein as the top surface of the pad 112) is lower than the surface of the tantalum substrate 100 around the recess 102 ( Hereinafter referred to as the surface of the ruthenium substrate 100, for example, the present invention is not limited thereto. In other embodiments, the top surface of the wafer 110 may also be higher than the surface of the germanium substrate 100, or the top surface of the wafer 110 may be coplanar with the surface of the germanium substrate 100, as the case may be. In the case where the top surface of the wafer 110 is higher than the surface of the ruthenium substrate 100, the wafer 110 may be subjected to a pressure treatment after the wafer 110 is placed in the recess 102. Since the adhesive layer 108 has a certain thickness and plasticity, the wafer 110 is slightly trapped in the adhesive layer 108 by the pressure treatment so that the top surface of the wafer 110 is coplanar with the surface of the ruthenium substrate 100.

Next, referring to FIG. 1C, a relocation layer structure 114 is formed on the germanium substrate 100 and the wafer 110. The reconfiguration layer structure 114 includes a dielectric layer 114a and a wiring layer 114b located in the dielectric layer 114a. The wiring layer 114b is electrically connected to the pads 112 of the wafer 110, and the dielectric layer 114a exposes a portion of the wiring layer 114b. The exposed portion of the wiring layer 114b is used to connect the subsequently formed solder balls. The method of forming the reconfiguration layer structure 114 is well known to those skilled in the art and will not be described herein. In particular, in the present embodiment, when the reconfiguration layer structure 114 is formed, the dielectric layer 114a is formed on the germanium substrate 100 and the wafer 110, and the recess 102 is sealed, that is, the dielectric layer 114a is not The groove 102 is filled, but the invention is not limited thereto. In other embodiments, depending on the material of the dielectric layer 114a, the dielectric layer 114a may also fill the recess 102 when the reconfigured layer structure 114 is formed, that is, the dielectric layer 114a fills the wafer 110 and the recess. The sidewalls of 102 are between and filled between adjacent wafers 110. In the present embodiment, the reconfiguration layer structure 114 has only one wiring layer, but the present invention is not limited thereto. In other embodiments, the reconfiguration layer structure 114 can have multiple layers of layers, depending on actual needs.

As previously mentioned, the top surface of the wafer 110 can be lower than the surface of the germanium substrate 100, can be higher than the surface of the germanium substrate 100, or be coplanar with the surface of the germanium substrate 100. However, after the reconfiguration layer structure 114 is formed, since the dielectric layer 114a having a certain thickness covers the germanium substrate 100 and the wafer 110, the difference in height between the top surface of the wafer 110 and the surface of the germanium substrate 100 does not A problem is caused to the flatness of the resulting package structure.

Then, referring to FIG. 1D, solder balls 116 are formed on the dielectric layer 114a. Solder balls 116 are coupled to exposed portions of wiring layer 114b to serve as contacts for connecting the package structure to external components. Thereafter, a portion of the germanium substrate 100 under the recess 102 (i.e., adjacent to the back surface 110b of the wafer 110) is removed to complete the fabrication of the package structure 10 of the present embodiment. The above method of removing a portion of the germanium substrate 100 is, for example, grinding the germanium substrate 100. In one embodiment, a protective adhesive layer for protecting the solder balls 116 may be formed on the reconfiguration layer structure 114, and then a carrier substrate is formed on the protective adhesive layer. Thereafter, the structure to be polished is transferred to the polishing machine table by the carrier substrate to perform grinding to remove a portion of the germanium substrate 100 under the recess 102 such that the formed package structure 10 has a desired thickness. After the polishing is completed, the protective adhesive layer and the carrier substrate are removed to obtain the package structure 10.

In the manufacturing method of the package structure of the present invention, the formation of the encapsulant is omitted, so that the process steps can be effectively simplified, and the problem that the copper column is damaged or the degree of grinding is insufficient due to the grinding of the encapsulant in the prior art is avoided. . In addition, in the package structure of the present invention, since there is no encapsulant, the problem of warpage of the package structure due to material difference between the encapsulant and the wafer is avoided.

While the present invention has been described above with reference to the embodiments of the present invention, it is not intended to limit the present invention, and it is possible to make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Package structure

100‧‧‧矽 substrate

102‧‧‧ Groove

104‧‧‧Alignment marks

106‧‧‧ warpage adjustment layer

108‧‧‧Adhesive layer

110‧‧‧ wafer

110a‧‧‧ positive

110b‧‧‧Back

112‧‧‧ pads

114‧‧‧Reconfiguration layer structure

114a‧‧‧Dielectric layer

114b‧‧‧Line layer

116‧‧‧ solder balls

1A to 1D are schematic cross-sectional views showing a manufacturing process of a package structure according to an embodiment of the invention.

10‧‧‧Package structure

100‧‧‧矽 substrate

102‧‧‧ Groove

104‧‧‧Alignment marks

106‧‧‧ warpage adjustment layer

108‧‧‧Adhesive layer

110‧‧‧ wafer

110a‧‧‧ positive

110b‧‧‧Back

112‧‧‧ pads

114‧‧‧Reconfiguration layer structure

114a‧‧‧Dielectric layer

114b‧‧‧Line layer

116‧‧‧ solder balls

Claims (10)

A package structure comprising: a germanium substrate having a recess; a wafer disposed in the recess; a reconfigurable layer structure disposed on the germanium substrate and the wafer, and electrically connected to the wafer; Solder balls are disposed on the reconfiguration layer structure and electrically connected to the reconfiguration layer structure, wherein a gap between the bottom surface of the groove and the reconfiguration layer structure is provided. The package structure of claim 1, wherein the reconfiguration layer structure comprises a dielectric layer and a circuit layer in the dielectric layer, and the dielectric layer fills the groove and the Said gap. The package structure of claim 1, wherein a top surface of the wafer is coplanar with a surface of the crucible substrate located around the recess. The package structure according to claim 1, further comprising a warpage adjusting layer disposed on a surface of the germanium substrate and sidewalls and a bottom surface of the groove. The package structure of claim 1, further comprising an adhesive layer disposed between the wafer and a bottom surface of the groove. A method for fabricating a package structure, comprising: forming a recess in a germanium substrate; disposing a wafer in the recess; forming a reconfiguration layer structure on the germanium substrate and the wafer, to Forming a gap between the layer structure and the bottom surface of the recess, and the reconfigurable layer structure is electrically connected to the wafer; and forming a solder ball on the reconfigured layer structure. The method of fabricating a package structure according to claim 1, wherein after forming the solder ball, further comprising removing a portion of the germanium substrate under the recess. The method of fabricating a package structure according to claim 1, wherein the reconfiguration layer structure comprises a dielectric layer and a circuit layer in the dielectric layer, and the dielectric layer fills the recess Slot and the gap. The method of fabricating a package structure according to claim 1, wherein the surface of the ruthenium substrate and the sidewalls and the bottom surface of the groove are further included after the groove is formed and before the wafer is disposed. A warpage adjustment layer is formed thereon. The method of fabricating a package structure according to claim 1, wherein an adhesive layer is further formed on the bottom surface of the wafer after the groove is formed and before the wafer is disposed.