TWI627687B - Ultra-thin flip chip package and its fabricating method - Google Patents

Abstract

A final thin flip chip package structure is disclosed, comprising a dummy wafer, a flip chip, and an underfill. The dummy wafer includes a semiconductor substrate layer and a reconfigurable wiring structure. The semiconductor substrate layer has a flat surface and a cavity hole recessed by the flat surface, and the reconfiguration wiring structure includes a plurality of pads exposed to the cavity. The flip chip is disposed on the dummy wafer, and the bump of the flip chip is bonded to the corresponding pad, and the active surface sinks and sinks into the cavity. An underfill is formed in the cavity to seal the bump and the active surface. Wherein, the back surface of the flip chip is coplanar to a flat surface by planarization, and the underfill does not overflow on the back surface of the flip chip, nor does it overflow on the flat surface of the dummy wafer. Thereby, the ultimate thin state of flip chip in the dummy wafer is achieved.

Description

Ultimate thin flip chip package structure and manufacturing method thereof

The present invention relates to the field of semiconductor chip packaging, and more particularly to a final thin flip chip package structure and a method of fabricating the same.

Semiconductor chip packaging technology continues to grow in miniaturization, one of which is the "Chip-On-Wafer (COW) process, which is used to grow solder shots, copper bumps or gold bumps on the wafer. The block contacts are then mounted on the wafer upside down and sealed, and the wafer is referred to as a flip chip. The carrier wafer used in the "Crystal Wafer on Wafer" process can replace the printed circuit board of the substrate strip type, thereby achieving a fine pitch of the wafer carrier and a large number of batch packages.

However, in the "flip-chip on-wafer" packaging process, a plurality of flip-chip wafers are protruding as protrusions on the wafer, which leads to difficulties in subsequent wafer processing. Especially in the packaging process that requires wafer flipping and replacement of the carrier, such as the polishing process on the back side of the wafer, the ball bonding process on the back side of the wafer, the flip chip attached to the transfer fixture, the flip chip and its bump contacts. Suffering from mechanical stress. Therefore, the flip chip package structure fabricated on the current "flip-on-wafer" packaging process suffers from chip cracking of the flip chip and bump non-contact problems of the flip chip. In addition, the underfill that is spotted after flip chip bonding can easily overflow the surface of the wafer, resulting in underfill contamination.

In order to solve the above problems, the main object of the present invention is to provide Providing a final thin flip chip package structure and a manufacturing method thereof, achieving the ultimate thin state of flip chip in a dummy wafer, and improving the problem of poor bump bonding in a "Crystal Wafer on Wafer" (COW) process, It can achieve the prevention of cracking, warping and overfilling of the flip chip.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses a final thin flip chip package structure comprising a dummy wafer, a flip chip and an underfill. The dummy wafer includes a semiconductor substrate layer and a reconfigurable wiring structure, the semiconductor substrate layer having a first flat surface, a second flat surface, and a cavity formed by the first flat surface. The circuit structure includes a plurality of first pads exposed to the cavity. The flip chip is disposed on the dummy wafer, the flip chip has an active surface, a back surface, and a plurality of bumps protruding from the active surface, the bumps are coupled to the corresponding first pads, The active surface sinks and sinks into the cavity. The underfill is formed in the cavity, and the underfill seals the bumps and the active surface. Wherein, the back surface of the flip chip is coplanar with the first flat surface in a first planarization polishing manner, and the underfill does not overflow on the back surface of the flip chip, nor does it overflow the virtual The first flat surface of the wafer. The present invention further discloses a method of fabricating the final thin flip chip package structure.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the foregoing final thin flip chip package construction, one of the underfill revealing surfaces is also specifically coplanar with the first flat surface.

In the foregoing final thin flip chip package structure, the exposed surface of the underfill preferably surrounds the back surface of the flip chip and covers the flip chip A plurality of sides are applied to reduce the mechanical stress on the "Crystal Wafer on Wafer" (COW) process directly applied to the flip chip.

In the above-mentioned ultimate thin flip chip package structure, the cavity is preferably provided with an inclined guide wall to facilitate the introduction of the underfill to fill the cavity.

In the foregoing ultra-thin flip-chip package structure, the first pads may be convex pillars protruding from the bottom of the cavity, so that the underfill is filled into the flip chip and the hole. bottom.

In the foregoing ultra-thin flip-chip package structure, the re-distribution line structure specifically includes a plurality of second pads embedded in the semiconductor substrate layer and a plurality of connecting the first pads and the second connections The pads are routed and the second pads are coplanarly exposed on the second flat surface in a second planarization manner to facilitate bonding a plurality of solder balls to the second pads.

In the foregoing ultra-thin flip-chip package structure, the re-distribution line structure specifically includes a plurality of third pads embedded in the semiconductor substrate layer, the semiconductor substrate layer further having a plurality of first flat surfaces The recessed terminal receiving holes expose the third pads for use in a thin package stack.

By the above technical means, the present invention improves the "Crystal on Wafer" (COW) packaging technology, and can be applied to a next-generation wafer assembly process, thereby producing the ultimate thin flip chip package structure, and has the following effects:

First, the probability of fracture of the flip chip in the COW process can be reduced.

Second, it can reduce the problem of thin warping and bump bonding of flip chip in COW process.

Third, it can improve the flip chip in the package structure fabricated according to the COW process. The bump is a non-contact problem.

Fourth, it can reduce the problem of overflow contamination of the underfill on the virtual wafer (wafer type in the process).

10‧‧‧Semiconductor wafer

20‧‧‧ Wafer Support System

30‧‧‧Flating grinder

40‧‧‧First photoresist layer

41‧‧‧ first hole pattern

51‧‧‧First mask

52‧‧‧second mask

53‧‧‧ Third mask

54‧‧‧Four mask

55‧‧‧ Fifth mask

60‧‧‧second photoresist layer

61‧‧‧second hole pattern

70‧‧‧ Third photoresist layer

71‧‧‧ third hole pattern

80‧‧‧fourth photoresist layer

81‧‧‧ fourth hole pattern

90‧‧‧ Fifth photoresist layer

91‧‧‧First mask pattern

92‧‧‧Second mask pattern

100‧‧‧The ultimate thin flip chip package structure

110‧‧‧Virtual Wafer

111‧‧‧Semiconductor substrate layer

111A, 111B‧‧‧ recessed holes

111C‧‧‧ thickened parts

112‧‧‧First flat surface

113‧‧‧Second flat surface

114‧‧‧容晶穴

115‧‧‧Guide wall

116‧‧‧Terminal receiving hole

120‧‧‧Flip chip

121‧‧‧Active surface

122‧‧‧Back

122A‧‧‧Unground crystal back

123‧‧‧Bumps

130‧‧‧ underfill

131‧‧‧ exposed surface

140‧‧‧Reconfigure line structure

141‧‧‧First mat

142‧‧‧second mat

143‧‧‧ lines

144‧‧‧3rd pad

144A‧‧‧Development Department

145‧‧‧fourth pad

150‧‧‧ solder balls

200‧‧‧Top package construction

210‧‧‧ wafer

220‧‧‧Terminal solder balls

230‧‧·Mold sealant

240‧‧‧Substrate

250‧‧‧welding line

1 is a cross-sectional view showing a final thin flip chip package structure in accordance with an embodiment of the present invention.

2A to 2F are schematic cross-sectional views showing the main steps of the manufacturing method of the final thin flip chip package structure according to an embodiment of the present invention.

FIG. 3 is a perspective view showing a substrate corresponding to FIG. 2A in a manufacturing method of the final thin flip chip package structure according to an embodiment of the present invention.

4 is a perspective view showing a planarizing polishing step corresponding to the 2D drawing in the manufacturing method of the final thin flip chip package structure according to an embodiment of the present invention.

Figure 5: A cross-sectional view of a final thin-film flip-chip package applied to a package stack structure (POP) in accordance with an embodiment of the present invention.

6A to 6W are schematic cross-sectional views showing the steps of the steps in the method for fabricating the dummy wafer of the final thin flip chip package structure according to an embodiment of the present invention.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related dimensions or are exaggerated or Simplify the process to provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

According to an embodiment of the present invention, a final thin flip chip package structure is illustrated in a cross-sectional view of FIG. 1 , and FIGS. 2A to 2F are diagrams showing components of each main step in the manufacturing method of the final thin flip chip package structure. FIG. 3 is a schematic perspective view showing one of the substrates provided in FIG. 2A in the manufacturing method of the final thin flip chip package structure, and FIG. 4 is a view showing the manufacturing method of the final thin flip chip package structure. A perspective view of a planarization polishing step is performed corresponding to the 2D image. FIG. 5 is a schematic cross-sectional view showing the application of the ultimate thin flip chip package structure to a package stack structure (POP). A final thin flip chip package structure 100 includes a dummy wafer 110, a flip chip 120, and an underfill 130.

Referring to FIG. 1 , the dummy wafer 110 includes a semiconductor substrate layer 111 and a reconfigured wiring structure 140 having a first flat surface 112 , a second flat surface 113 , and a first The flat surface 112 is recessed into the cavity 114, and the reconfiguration circuit structure 140 includes a plurality of first pads 141 exposed to the cavity 114. The main material of the semiconductor substrate layer 111 is a semiconductor, such as germanium (Si), which is formed by dicing a wafer; thereby, the thermal expansion coefficient of the dummy wafer 110 is close to or equal to that of the flip chip 120. Thermal expansion coefficient. The size and thickness of the dummy wafer 110 are specifically larger than the size and thickness of the flip chip 120. Therefore, the dummy wafer 110 can serve as a carrier for carrying the flip chip 120. The virtual wafer 110 itself may not have an integrated circuit such as a memory, a controller or a logic device. In the present embodiment, the cavity 114 preferably has an inclined guide wall 115 to facilitate the introduction of the underfill 130 to fill the cavity 114.

In this embodiment, the first pads 141 may be convex and protruding. For the bottom of the cavity 114, the underfill 130 is filled into the bottom of the flip chip 120 and the hole 114. More specifically, the reconfiguration line structure 140 specifically includes a plurality of second pads 142 embedded in the semiconductor substrate layer 111 and a plurality of connecting the first pads 141 and the second pads 142. The second lands 142 are coplanarly exposed on the second flat surface 113 in a second planarization manner to facilitate bonding the plurality of solder balls 150 to the second pads 142.

In a specific application, the reconfiguration line structure 140 specifically includes a plurality of third pads 144 embedded in the semiconductor substrate layer 111, and the semiconductor substrate layer 111 further has a plurality of first flat surfaces. 112 recessed terminal receiving holes 116, which expose the third pads 144 for use in a thin package stack. The third pads 144 can have a T-shaped cross section. In addition, the reconfiguration line structure 140 specifically includes a plurality of fourth pads 145 that are connected to the third pads 144. The fourth pads 145 can also be coplanarly exposed on the second flat surface 113 to engage the portions of the solder balls 150.

The flip chip 120 is disposed on the dummy wafer 110. The flip chip 120 has an active surface 121, a back surface 122, and a plurality of bumps 123 protruding from the active surface 121. The bumps 123 are bonded to each other. The first pads 141, the active surface 121 sinks and sinks into the cavity 114. The flip chip 120 is an integrated circuit having an active function, which is formed on the active surface 121, and uses the bumps 123 as an electrical transmission end point of the integrated circuit. The main structure of the bumps 123 may be selected from one of a solder ball, a copper pillar, and a gold pillar.

The underfill 130 is formed in the cavity 114, and the underfill 130 seals the bumps 123 and the active surface 121. Usually, the underfill 130 is a thermosetting colloid, which has high fluidity with pore filling before curing, and is cured. Then, the function of fixing the flip chip 120, protecting the bumps 123 and electrically insulating is provided.

In addition, the back surface 122 of the flip chip 120 is coplanar with the first flat surface 112 of the semiconductor substrate layer 111 in a first planarization manner, and the underfill 130 does not overflow the flip chip 120. The back surface 122 does not overflow the first flat surface 112 of the dummy wafer 110. In the present embodiment, one of the exposed surfaces 131 of the underfill 130 is specifically coplanar with the first flat surface 112. In this embodiment, the exposed surface 131 of the underfill 130 preferably surrounds the back surface 122 of the flip chip 120 and covers a plurality of sides of the flip chip 120 to reduce "overlay". Mechanical stress is applied directly to the flip chip 120 in the "round on" (COW) process. The side is between the active surface 121 of the flip chip 120 and the back surface 122.

Therefore, the present invention provides a final thin flip chip package structure 100, which achieves the ultimate thin state of the flip chip 120 in the dummy wafer 110, thereby preventing breakage, warpage and underfill of the flip chip 120. The glue 130 is contaminated by the glue, and the problem of poor bonding of the bumps 123 can be improved.

Referring to Figures 2A through 2F, the method of fabricating the above-described ultimate thin flip chip package structure 100 is further described below.

Referring to FIG. 2A, a dummy wafer 110 is provided. The dummy wafer 110 includes a semiconductor substrate layer 111 and a reconfigured wiring structure 140. The semiconductor substrate layer 111 has a cavity 114 and the reconfigurable circuit structure 140. A plurality of first pads 141 exposed in the cavity 114 are included. The reconfiguration line structure 140 further includes a plurality of second pads 142 embedded in the semiconductor substrate layer 111 and a plurality of lines 143 connecting the first pads 141 and the second pads 142. The reconfiguration line structure 140 further includes a plurality of third pads embedded in the semiconductor substrate layer 111. 144. The semiconductor substrate layer 111 further includes a plurality of terminal receiving holes 116 recessed by the first flat surface 112, and the third pads 144 are exposed. In one embodiment, as shown in FIG. 3, a plurality of the dummy wafers 110 may be integrally formed on a semiconductor wafer 10.

Referring to FIG. 2B, a flip chip 120 is disposed to the dummy wafer 110. The flip chip 120 has an active surface 121, an unpolished crystal back 122A, and a plurality of bumps 123 protruding from the active surface 121. The bumps 123 are engaged with the corresponding first pads 141 , and the active surface 121 sinks and sinks into the cavity 114 . The unpolished crystal back 122A can protrude from the dummy wafer 110.

Referring to FIG. 2C, an underfill 130 is formed in the cavity 114, and the underfill 130 seals the bumps 123 and the active surface 121.

Referring to FIG. 2D, a first planarization polishing step is performed, starting from the unpolished crystal back 122A to reduce the thickness of the flip chip 120 and forming a back surface 122 of the flip chip 120; The thickness of the dummy wafer 110 is formed to form one of the first flat faces 112 of the semiconductor substrate layer 111. The cavity 114 is still recessed by the first flat surface 112. The first planarization polishing step is performed until the back surface 122 of the flip chip 120 is coplanar with the first planar surface 112. The underfill 130 does not overflow the back surface 122 of the flip chip 120 and does not overflow the first flat surface 112 of the dummy wafer 110. In a specific form, as shown in FIG. 4, the wafer 10 including the dummy wafer 110 is mounted on a wafer support system 20, and the wafer 10 is polished by a planarizing grinder 30. The wafer support system 20 can be a wafer-shaped and viscous glass sheet or an electrostatic chuck. The planarizing grinder 30 can comprise a chemical polishing head.

Preferably, in the first planarization grinding step, the bottom filling One of the exposed surfaces 131 of the filling 130 is also coplanar with the first flat surface 112 (as shown in FIG. 2D). More specifically, the exposed surface 131 of the underfill 130 surrounds the back surface 122 of the flip chip 120 and covers a plurality of sides of the flip chip 120.

Referring to FIG. 2E, the manufacturing method may further include performing a second planarization polishing step to expose the second pads 142 to the second flat surface 113 of the semiconductor substrate layer 111 in a coplanar manner. The second flat surface 113 is opposite to the first flat surface 112 of the semiconductor substrate layer 111. The step between the first planarization polishing step and the second planarization polishing step may include an operation of wafer flipping and replacing the carrier.

Referring to FIG. 2F, the manufacturing method may further include performing a ball implantation step of bonding a plurality of solder balls 150 to the second pads 142 of the dummy wafer 110. A portion of the solder balls 150 can be bonded to a plurality of fourth pads 145 of the dummy wafer 110. Thereafter, the wafer singulation of the wafer is performed to obtain the final thin flip chip package structure 100 as shown in FIG.

Referring to FIG. 5, the ultimate thin flip chip package structure 100 can be used as a package package structure (POP) bottom package structure. A top package structure 200 is stackable bonded to the final thin flip chip package construction 100. The top package structure 200 includes a hermetically protected wafer 210 and a plurality of terminal solder balls 220. The terminal solder balls 220 are bonded to the third pads 144 of the dummy wafer 110 through the terminal receiving holes 116 of the final thin flip chip package structure 100. The top package structure 200 can further include a mold encapsulation 230 sealing the wafer 210 and a substrate 240 carrying the wafer 210. The plurality of bonding wires 250 or internal electrical connection components are electrically connected to the wafer 210 and the substrate. 240. Preferably, the underfill 130 of the final thin flip chip package structure 100 does not have an overfill protruding from the first flat surface 112 of the dummy wafer 110. The substrate 240 or the bottom surface of the top package structure 200 can be attached to the back surface 122 of the flip chip 120 to gain heat dissipation performance to the flip chip 120 and reduce the thickness of the package stack structure. .

Referring to FIGS. 6A to 6W, the manufacturing method of the dummy wafer 110 in the above-described ultimate thin flip chip package structure 100 is further described below.

Referring to FIG. 6A, a semiconductor substrate layer 111 is provided. The material of the semiconductor substrate layer 111 may include germanium (Si). In this step, the semiconductor substrate layer 111 can be a wafer. Thereafter, referring to FIG. 6B, the semiconductor substrate layer 111 is brought to a thickness that can be processed by the wafer by grinding.

Referring to FIG. 6C, a first photoresist layer 40 is coated on the semiconductor substrate layer 111. Referring to FIG. 6D, the first photoresist layer 40 is patterned and exposed by a first mask 51, and the first photoresist layer 40 may include a positive photoresist. Referring to FIG. 6E, the first photoresist layer 40 is developed. The first photoresist layer 40 has a first hole pattern 41. The position and size of the first hole pattern 41 correspond to the position and size of the second pad 142 and the fourth pad 145.

Referring to FIG. 6F, the semiconductor substrate layer 111 is in a plurality of recessed holes 111A and 111B by dry etching. The recessed holes 111A correspond to the second pads 142, and the recessed holes 111B correspond to the above. The fourth pad 145. Referring to FIG. 6G, the first photoresist layer 40 on the semiconductor substrate layer 111 is removed by photoresist removal. Referring to FIG. 6H, the second pads 142 and the fourth pads 145 are formed in the recesses 111A and 111B of the semiconductor substrate layer 111 by electroplating.

Referring to FIG. 6I, a second photoresist layer 60 is coated on the semiconductor substrate layer 111. The second photoresist layer 60 covers the second pads 142 and the fourth pads 145 . Referring to FIG. 6J, the second photoresist layer 60 is inserted into the second photoresist layer 60. The row of patterned exposures, the second photoresist layer 60 can comprise a positive photoresist. Referring to FIG. 6K, the second photoresist layer 60 is developed, and the second photoresist layer 60 has a second hole pattern 61. The position and size of the second hole pattern 61 correspond to the position and size of the above-mentioned line 143.

Referring to FIG. 6L, the above-mentioned line 143 is formed in the second hole pattern 61 of the second photoresist layer 60 by electroplating. Referring to FIG. 6M, the second photoresist layer 60 on the semiconductor substrate layer 111 is removed by photoresist removal.

Referring to FIG. 6N, a third photoresist layer 70 is coated on the semiconductor substrate layer 111. The third photoresist layer 70 covers the lines 143. Moreover, the third photoresist layer 70 is patterned and exposed by a third photomask 53 which may include a positive photoresist. Referring to FIG. 60, the third photoresist layer 70 is developed. The third photoresist layer 70 has a third hole pattern 71. The position of the third hole pattern 71 corresponds to the positions of the first pad 141 and the third pad 144. Referring to FIG. 6P, the first pad 141 and the third pad 144 are formed in the third hole pattern 71 of the third photoresist layer 70 by electroplating to form the above-described reconfiguration line structure 140. Referring to FIG. 6Q, the third photoresist layer 70 on the semiconductor substrate layer 111 is removed by photoresist removal. Further, the thickness of the semiconductor substrate layer 111 can be increased by chemical vapor deposition.

Referring to FIG. 6R, a fourth photoresist layer 80 is coated on the semiconductor substrate layer 111. The fourth photoresist layer 80 covers the reconfiguration line structure 140. Moreover, the fourth photoresist layer 80 is patterned and exposed by a fourth mask 54 which may include a positive photoresist. Referring to FIG. 6S, the fourth photoresist layer 80 is developed, and the fourth photoresist layer 80 has a fourth hole pattern 81. The position of the fourth hole pattern 81 corresponds to the position of the third pad 144. Please refer to Figure 6T for electroplating The pad enlarged portion 144A of the third pads 144 is formed in the fourth hole pattern 81 of the fourth photoresist layer 80 such that the third pads 144 have a T-shaped cross section. Thereafter, the fourth photoresist layer 80 on the semiconductor substrate layer 111 is removed by photoresist removal.

Referring to FIG. 6U, a fifth photoresist layer 90 is coated on the semiconductor substrate layer 111. The fifth photoresist layer 90 covers the reconfigured wiring structure 140. Moreover, the fifth photoresist layer 90 is patterned and lightly exposed by a fifth mask 55, which may include a negative photoresist. Referring to FIG. 6V, the fifth photoresist layer 90 is developed to form the fifth photoresist layer 90 into a first mask pattern 91 and a plurality of second mask patterns 92. The size and position of the first mask pattern 91 correspond to the size and position of the cavity 114. The size and position of the second mask patterns 92 correspond to the size and position of the terminal receiving holes 116. Referring to FIG. 6W, a thickened layer portion 111C is formed on the semiconductor substrate layer 111 by chemical vapor deposition (CVD) to increase the thickness of the semiconductor substrate layer 111. Meanwhile, the semiconductor substrate layer 111 is formed. The cavity 114 and the terminal receiving hole 116 are received. Thereafter, the first mask pattern 91 and the second mask patterns 92 are removed by photoresist removal to form the dummy wafer 110 as shown in FIG. 2A. A plurality of the above dummy wafers 110 are formed on a wafer.

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, and thus equivalent changes made in the claims of the present invention are still within the scope of the present invention.

Claims (12)

A final thin flip chip package structure comprising: a dummy wafer comprising a semiconductor substrate layer and a reconfigured wiring structure, the semiconductor substrate layer having a first flat surface, a second flat surface, and a first flat surface a recessed cavity, the reconfigured circuit structure comprising a plurality of first pads exposed to the cavity; a flip chip is disposed to the dummy die, the flip chip having an active surface a back surface and a plurality of bumps protruding from the active surface, the bumps are engaged with the corresponding first pads, the active surface sinks and sinks into the cavity; and an underfill, Formed in the cavity, the underfill seals the bumps and the active surface; wherein the back surface of the flip chip is coplanar with the first flat surface in a first planarization manner And the underfill does not overflow on the back surface of the flip chip, nor does it overflow on the first flat surface of the dummy wafer. The ultimate thin flip chip package structure of claim 1, wherein the exposed surface layer of the underfill is also coplanar to the first flat surface. The ultimate thin flip chip package structure of claim 2, wherein the exposed surface of the underfill surrounds the back side of the flip chip and covers a plurality of sides of the flip chip. The ultimate thin flip chip package structure of claim 3, wherein the cavity has an inclined guide wall. The ultimate thin flip chip package structure according to claim 1, wherein the first pads are convex pillars and protrude from the bottom of the cavity. The ultimate thin flip chip package structure according to any one of claims 1 to 5, wherein the reconfigured line structure further comprises a plurality of second pads embedded in the semiconductor substrate layer and a plurality of connections The first pads and the second pads are routed in a second planarization manner such that the second pads are coplanarly exposed on the second flat surface. The final thin-film flip-chip package structure according to claim 6, wherein the re-distribution circuit structure further comprises a plurality of third pads embedded in the semiconductor substrate layer, the semiconductor substrate layer further having a plurality of The terminal receiving hole recessed by the first flat surface exposes the third pads. A method for fabricating a final thin flip chip package structure includes: providing a dummy wafer comprising a semiconductor substrate layer and a reconfigured wiring structure, the semiconductor substrate layer having a cavity, the reconfigurable circuit structure a plurality of first pads exposed on the cavity; a flip chip is disposed on the dummy wafer, the flip chip has an active surface, an unpolished crystal back, and a plurality of protrusions protruding from the active surface Blocks, the bumps are joined to the corresponding first pads, the active surface sinks and sinks into the cavity; an underfill is formed in the cavity, the underfill is dense Sealing the bumps and the active surface; and performing a first planarization polishing step such that a back surface of one of the flip chip is coplanar with a first flat surface of the semiconductor substrate layer, and the cavity is formed by the The first flat surface is recessed, and the underfill does not overflow on the back surface of the flip chip, nor does it overflow on the first flat surface of the dummy wafer. The manufacturing method of the ultimate thin flip chip package structure according to claim 8, wherein in the first planarization polishing step, one of the underfill layers reveals that the surface system is also coplanar with the first flat surface. The method of manufacturing the ultimate thin flip chip package structure of claim 8, wherein the exposed surface of the underfill surrounds the back side of the flip chip and covers a plurality of sides of the flip chip. The manufacturing method of the ultimate thin flip chip package structure according to claim 8, wherein the reconfigured circuit structure further comprises a plurality of second pads embedded in the semiconductor substrate layer and a plurality of Connecting the first pads and the second pads, the manufacturing method further comprises: performing a second planarization polishing step, so that the second pads are coplanarly exposed on the semiconductor substrate layer One of the second flat faces. The method of manufacturing the ultimate thin flip chip package structure according to claim 11, wherein the reconfigurable circuit structure further comprises a plurality of third pads embedded in the semiconductor substrate layer, the semiconductor substrate layer further The terminal has a plurality of terminal receiving holes recessed by the first flat surface, and the third pads are exposed.