TWI608597B - Non-volatile semiconductor memory device - Google Patents

Description

Non-volatile semiconductor memory device

This invention relates to non-volatile semiconductor memory devices.

Japanese Patent Laid-Open Publication No. 2011-129816 (Patent Document 1) discloses a memory cell in which a memory gate structure is disposed between two selected gate structures (see Patent Document 1, FIG. 15). In fact, in the memory cell, there is: a drain region connected to a bit line; and a source region connected to the source line; and in the well between the drain region and the source region, The sequence configuration forms a selective gate structure, a memory gate structure, and another selected gate structure. In the memory cell configured as described above, a charge accumulation layer is provided in the memory gate structure, and data can be written by injecting a charge into the charge accumulation layer, or by extracting a charge accumulation layer. Delete the data with charge. Here, FIG. 9 is a schematic view showing an example of a circuit configuration of the conventional nonvolatile semiconductor memory device 100. In this case, the non-volatile semiconductor memory device 100 arranges, for example, a plurality of memory cells 102a, 102b, 102c, 102d, 102e, 102f, 102g, 102h in a matrix, and for each memory cell 102a arranged in the column direction, 102b; 102c, 102d; 102e, 102f; 102g, 102h constitute memory cell forming portions 101a, 101b, 101c, 101d. Further, the nonvolatile semiconductor memory device 100 is a memory cell 102a, 102c, 102e, 102g (102b, 102d, 102f) arranged in the row direction among the memory cells 102a, 102b, 102c, 102d, 102e, 102f, 102g, 102h. 102h) A bit line BL1 (BL2) is shared, and a specific bit voltage can be uniformly applied to each of the bit lines BL1 and BL2. Furthermore, the non-volatile semiconductor memory device 100 shares the memory gate lines MGL1, MGL2, MGL3, MGL4 and the drain side selection gate lines DGL1, DGL2, for example, in each memory cell forming portion 101a, 101b, 101c, 101d. DGL3 and DGL4 can respectively apply a specific voltage to each of the memory gate lines MGL1, MGL2, MGL3, and MGL4 and each of the drain side selection gate lines DGL1, DGL2, DGL3, and DGL4. Further, in the nonvolatile semiconductor memory device 100, one source side selection gate line SGL and one source line are shared by all of the memory cells 102a, 102b, 102c, 102d, 102e, 102f, 102g, and 102h. SL, and a specific source gate voltage can be applied to the source side selection gate line SGL, and a specific source voltage is applied to the source line SL. Each of the memory cells 102a, 102b, 102c, 102d, 102e, 102f, 102g, and 102h has the same configuration. For example, the memory unit 102a has a memory gate electrode MG connected to the memory gate line MGL1 and a drain side selected. The gate electrode DG is connected to the drain side selection gate line DGL1; and the source side selection gate electrode SG is connected to the source side selection gate line SGL. Moreover, in each of the memory cells 102a, 102b, 102c, 102d, 102e, 102f, 102g, 102h, a charge can be injected into the memory by a quantum tunneling effect generated by a voltage difference between the memory gate electrode MG and the channel layer. In the charge accumulation layer EC, a state in which data is written is obtained. Here, in the conventional nonvolatile semiconductor memory device 100, for example, when reading data read from the data of the memory cell 102a in the first row of the first column, the data can be read and read. The bit line BL1 connected to the memory cell (hereinafter, also referred to as the data read cell) 102a is applied with a read voltage of 1.5 [V], and only the memory cells 102b, 102d, 102f, 102h to which no data is read are connected. The bit line BL2 applies a read inhibit voltage of 0 [V]. Further, at this time, in the nonvolatile semiconductor memory device 100, 0 [V] can be applied to the memory gate lines MGL1, MGL2, MGL3, and MGL4, and 1.5 [V] can be applied to the source side selection gate line SGL. 0 [V] is applied to the source line SL. Further, at this time, in the nonvolatile semiconductor memory device 100, a read gate voltage of 1.5 [V] can be applied to the drain side selective gate line DGL1 connected to the data read cell 102a, and only the connection is performed. The gate-side selection gate lines DGL2, DGL3, and DGL4 of the memory cells 102c, 102d, 102e, 102f, 102g, and 102h that do not read data apply a read inhibit gate voltage of 0 [V]. As a result, in the data readout cell 102a, the well directly below the drain side selective gate electrode DG connected to the bit line BL1 is turned on, but when the charge is accumulated in the charge storage layer EC (when data is written) The well directly under the memory gate electrode MG becomes non-conductive, so that the electrical connection between the source line SL and the bit line BL1 can be blocked, and the read voltage of 1.5 [V] of the bit line BL1 is maintained. change. On the other hand, when the charge is not accumulated in the charge storage layer EC of the data readout cell 102a (in the case where data is not written), the well immediately below the memory gate electrode MG is turned on, and is read out via the data. The cell 102a electrically connects the source line SL of 0 [V] to the bit line BL1 of 1.5 [V], and applies 1.5 to the bit line BL1 by the source line SL of 0 [V]. The read voltage of V] is lowered. Furthermore, at this time, in the other memory cells 102c, 102e, and 102g of the shared data readout cell 102a and the bit line BL1, the voltages of the gate lines DGL2, DGL3, DGL4 and the bit line BL1 are selected by the drain side. The well below the gate electrode DG is selected to be in a non-conducting state, so that the read voltage of 1.5 [V] of the bit line BL1 is not affected. As described above, in the nonvolatile semiconductor memory device 100, it is possible to detect whether or not the charge accumulation layer EC of the data readout cell 102a accumulates electric charge by detecting whether or not the read voltage of the bit line BL1 changes. Next, a plan layout of, for example, the memory cell forming portion 101a provided in the memory cell forming portions 101a, 101b, 101c, and 101d of the nonvolatile semiconductor memory device 100 will be described. Here, a planar layout as shown in FIG. 10 is considered as a planar layout of the memory cell forming portion 101a. FIG. 10 is a schematic view showing an example of a planar layout when the memory cell forming portion 101a is viewed from above the semiconductor substrate. Here, the memory cell forming portion 101a in which three memory cells 102a, 102b, and 102c are provided will be described. In this case, the memory cell forming portion 101a has a memory cell region ER3 in which the memory cells 102a, 102b, and 102c are disposed, and at one end of the memory cell region ER3, a selective gate contact region ER6 is disposed at the memory cell. The other end of the region ER3 is provided with another selective gate contact region ER7. Further, at the end of the gate contact region ER6 (ER7), the solid cut region ER1 (ER5) is disposed via the electrical cut region ER2 (ER4). In this case, the memory cell forming portion 101a cuts off the region ER1 from a solid, cuts off an electrical cut-off region ER2, selects a gate contact region ER6, a memory cell region ER3, another select gate contact region ER7, and another A strip-shaped memory gate electrode MG is extended from the one electrically cut region ER4 and the other solid cut region ER5. For example, the memory gate electrode MG of the solid cut regions ER1 and ER5 is provided with a memory. Body gate contact MGC. In the memory cell region ER3, a well W having a specific shape is formed on the surface of the semiconductor substrate, for example, a memory arrangement region W1, W2, W3 formed in a strip shape in the well W, and the memory gate electrode MG is disposed in an intersecting manner. . Here, the memory arrangement regions W1, W2, and W3 are divided into the source region WS side and the drain region WD side with the memory gate electrode MG as a boundary. In the memory cell forming portion 101a, the source regions WS of the respective memory arrangement regions W1, W2, and W3 are connected to each other, and can be connected to each other via the columnar source contact SC connected to the source line SL (FIG. 9). The source region WS uniformly applies a specific source voltage. Further, in the memory cell forming portion 101a, the respective drain regions WD of the memory arrangement regions W1, W2, and W3 are separated from each other, and are different from each other via the bit contact BC provided in each of the drain regions WD. The bit lines BL1, BL2, ... individually apply a specific bit voltage to each of the drain regions WD. In the memory cell region ER3 of the memory cell forming portion 101a, one side wall 112 of the memory gate electrode MG is disposed on the drain region WD side of the well W, and a drain side selective gate electrode DG is formed along the sidewall 112. On the other hand, the other side wall 111 of the memory gate electrode MG is disposed on the source region WS side of the well W, and the source-side selective gate electrode SG is formed along the sidewall 111. In this case, the drain side selection gate electrode DG and the source side selection gate electrode SG are shared by the plurality of memory cells 102a, 102b, and 102c arranged in the column direction together with the memory gate electrode MG. Further, the drain side selection gate electrode DG and the source side selection gate electrode SG are insulated from the memory gate electrode MG by a sidewall spacer (not shown) made of an insulating material. The gate electrode DG is selected on the drain side, and the wide selective gate contact forming portion Ca provided with the drain side selective gate contact DGC is formed in a selective gate contact region ER6, which can be selected via the drain side. The gate contact DGC and the gate contact forming portion Ca are applied to apply a specific voltage from the drain side selective gate line DGL2 (FIG. 9). Further, the gate electrode SG is selected on the source side, and the wide selective gate contact forming portion Cb on which the source side selective gate contact SGC is provided is formed in the other selected gate contact region ER7 via the source. The gate side selects the gate contact SGC and the selected gate contact forming portion Cb to apply a specific voltage from the source side selection gate line SGL (FIG. 9). In addition, in the electrical cut regions ER2 and ER4, the memory gate electrode MG is extended from the memory cell region ER3, but unlike the memory cell region ER3, the drain side selective gate electrode DG and the source are not extended. The gate electrode SG is selected on the pole side, and the electrode cut electrodes 103a and 103b forming the pin junction are formed instead of the drain side selection gate electrode DG and the source side selection gate electrode SG. Actually, the electrical cut-off portions 103a and 103b have intrinsic semiconductor layers Ia and Ib made of i-type and conductive types different from the drain-side selective gate electrode DG and the source-side selective gate electrode SG ( In this case, the opposite conductivity type semiconductor layer OC of the p-type), the intrinsic semiconductor layers Ia, Ib and the opposite conductivity type semiconductor layer OC, according to the intrinsic semiconductor layer Ia, the opposite conductivity type semiconductor layer OC, and the intrinsic semiconductor The layers Ib are arranged in the order and formed along the respective side walls 111, 112 of the memory gate electrode MG. In the electrical cut-off regions ER2 and ER4 of the memory cell forming portion 101a, the n-type drain electrode DG and the source side selective gate electrode SG are used as the starting point, and the i-type intrinsic semiconductor layer is used. Since the opposite conductivity type semiconductor layer OC and the i-type intrinsic semiconductor layer Ib of the Ia and P types are arranged in this order, a pin can be formed at the end of the n-type drain side selection gate electrode DG and the source side selection gate electrode SG. In the junction, the drain-side selection gate electrode DG and the source-side selection gate electrode SG can be electrically disconnected at two locations of the electrical cutoff portions 103a and 103b. Further, in addition to the physical cut regions ER1 and ER5 at the ends of the electrical cut regions ER2 and ER4, semiconductor materials or the like are not formed along the side walls 111 and 112 and the end walls 113 of the memory gate electrode MG. The conductive layer is formed with a solid-cut portion 104 in which the drain-side selection gate electrode DG and the source-side selection gate electrode SG are in a non-contact state. Thereby, in the memory cell forming portion 101a, the gate electrode is selected not only by the two electrical cutting portions 103a and 103b but also by the solid cutting portions 104 of the solid cutting regions ER1 and ER5. DG and the source side selection gate electrode SG are electrically connected to each other, and a specific voltage can be individually applied to the drain side selection gate electrode DG and the source side selection gate electrode SG. [Prior Art Document] [Patent Document] [Patent Document 1] Japanese Patent Laid-Open Publication No. 2011-129816

[Problems to be Solved by the Invention] Further, in the memory cell forming portion 101a, the gate electrode side selective gate electrode is prevented by the two electrical cutting portions 103a and 103b and one solid cutting portion 104. The DG is electrically connected to the source side selection gate electrode SG. However, it is also considered that the electrical disconnection portions 103a and 103b and the solid cutting portion 104 are defective due to a number of reasons, so that the drain side selection gate is provided. The electrode DG is electrically connected to the source side selection gate electrode SG. Here, for example, as shown in FIG. 9, when the data reading operation of the data of the memory cell 102a in the first row of the first column is read, the drain side is selected in the memory cell forming portion 101b where the data is not read. When the gate electrode DG is electrically connected to the source side selection gate electrode SG to cause a short circuit defect, the source of the gate line DGL2 and the source of 1.5 [V] is selected on the drain side of 0 [V] in the memory cell forming portion 101b. The pole side selection gate line SGL is electrically connected (in FIG. 9, indicated by the wiring L). As a result, in the nonvolatile semiconductor memory device 100, there is a concern that the 0 [V] voltage of the drain side selection gate line DGL2 rises, or the source side shared by all the memory cells 102a, 102b, ... The voltage of 1.5 [V] of the gate line SGL is selected to be lowered, and the readout malfunction is caused by the voltage variation of the drain side selection gate line DGL2 or the source side selection gate line SGL. Therefore, in such a non-volatile semiconductor memory device 100, it is desirable to take further countermeasures in such a manner that the gate-side selection gate electrode DG and the source-side selection gate electrode SG are not electrically connected, and it is more preventable than before. The readout malfunction caused by the voltage fluctuation during the data read operation. Accordingly, the present invention has been made in view of the above aspects, and an object thereof is to provide a nonvolatile semiconductor memory device which is prevented from being erroneously read due to voltage fluctuations during data reading operation. [Means for Solving the Problems] In order to solve the above problems, the nonvolatile semiconductor memory device according to the first aspect of the invention is characterized in that the nonvolatile semiconductor memory device is provided with a plurality of memory cell forming portions, and the memory cell forming portion The first selection gate structure includes a first selection gate electrode on a well of a semiconductor substrate via a first selection gate insulating film, and a second selection gate structure in which a second selection gate is interposed Selecting a gate insulating film to have a second selection gate electrode; and a memory gate structure provided between the first selection gate structure and the second selection gate structure via a sidewall spacer; And pressing the gate insulating film, the charge storage layer, the upper gate insulating film, and the memory gate electrode in the order of the well; and extending the electrode portion, wherein the first selection gate structure is disposed from the opposite direction And extending the memory gate electrode of the selected gate formation region of the second selection gate structure; and providing three or more conductivity types on the sidewall of the extension electrode portion Said first selection gate electrode and the second selection gate electrodes different from conductive type semiconductor layer, an intrinsic semiconductor layer or either one of the opposite. Further, the nonvolatile semiconductor memory device according to claim 2 is characterized in that: the memory cell forming portion is provided with a plurality of memory cell forming portions, and the memory cell forming portion includes: a first selective gate structure; The first selection gate electrode is provided on the well of the semiconductor substrate via the first selection gate insulating film, and the second selection gate structure has the second selection on the well via the second selection gate insulating film. a gate electrode; and a memory gate structure, which is provided between the first selective gate structure and the second selected gate structure via a sidewall spacer, and has a gate insulating film and a charge The storage layer, the upper gate insulating film, and the memory gate electrode are sequentially stacked on the well; and the memory cell forming portion and the other memory cell forming portion are connected by extending the electrode, The extension electrode is extended from the memory gate electrode in which the first gate structure and the selected gate formation region of the second selection gate structure are disposed opposite to each other The electrode portion of the side wall is provided with three or more of the first conductivity type and the selection gate electrode and the second selection gate electrode is different from an opposite conductivity type semiconductor layer, intrinsic semiconductor layer, or of any one. [Effect of the Invention] In the nonvolatile semiconductor memory device according to the first aspect of the present invention, the first selection gate electrode and the second selection gate electrode are provided along three or more sidewalls of the extending electrode portion. The portion of the opposite-conducting-type semiconductor layer or the intrinsic semiconductor layer that is cut off can be prevented from being read out earlier than the portion where the first selection gate electrode and the second selection gate electrode are cut. Malfunction caused by voltage fluctuation during operation. Further, in the nonvolatile semiconductor memory device according to the second aspect of the present invention, three or more first selection gate electrodes for cutting one memory cell forming portion are provided along the side wall of the extending electrode portion, and the other Any one of the opposite conductivity type semiconductor layer or the intrinsic semiconductor layer electrically connected to the first selection gate electrode or the second selection gate electrode of the memory cell formation portion is increased by a memory cell formation portion (1) Selecting a gate electrode and a portion where the first selection gate electrode or the second selection gate electrode of the other memory cell formation portion is cut can be prevented from malfunctioning due to voltage fluctuation during the read operation. .

Hereinafter, embodiments for carrying out the invention will be described. In addition, the description is set to the order shown below. <1. First Embodiment> 1-1. Configuration of Memory Cell 1-2. Circuit Configuration of Nonvolatile Semiconductor Memory Device of the Present Invention 1-3. Voltage Correlation in Various Operation of Nonvolatile Semiconductor Memory Device 1 -4. Planar layout of a nonvolatile semiconductor memory device 1-5. Action and effect <2. Planar layout of the nonvolatile semiconductor memory device of the second embodiment><3. Nonvolatile semiconductor memory of the third embodiment Planar layout of the device><4. Planar layout of the nonvolatile semiconductor memory device according to the fourth embodiment><5. Other embodiments><6. Positional relationship between the electrically cut region and the solid cut region> (1) First Embodiment (1-1) Configuration of Memory Cell First, the configuration of a memory cell arranged in a matrix in the nonvolatile semiconductor memory device of the present invention will be described below. As shown in FIG. 1, the memory cell 2a is formed, for example, on a well W made of P-type Si or the like: a memory gate structure 4a which forms an N-type transistor structure; and a drain-side selection gate structure 5a. It forms an N-type MOS (Metal-Oxide-Semiconductor) transistor structure; and a source-side selection gate structure 6a, which also forms an N-type MOS transistor structure. A drain region WD at one end of the drain side selective gate structure 5a and a source region WS at one end of the source side selective gate structure 6a are formed on the surface of the well W at a predetermined distance. A bit line BL1 is connected to the drain region WD, and the source line SL is connected to the source region WS. Further, on the surface of the well W, a low-concentration drain region WDA is formed adjacent to the drain region WD, and a sidewall SW formed by selecting a sidewall of the gate structure 5a along the drain side is disposed at the low side. Concentration in the drain region WDA. Further, on the surface of the well W, a low-concentration source region WSa is formed adjacent to the source region WS, and a sidewall SW formed along the source-side selection gate sidewall of the gate structure 6a is disposed at the low concentration. On the source area WSa. The memory gate structure 4a is on the well W between the low concentration drain region WDA and the low concentration source region WSa, and contains SiO ₂ a gate insulating film Bo under the insulating material, such as tantalum nitride (Si) ₃ N ₄ ), cerium oxynitride (SiON), aluminum oxide (Al2O3), cerium oxide (HfO) ₂ The charge storage layer EC is formed in the charge storage layer EC, and the memory gate electrode MG is provided on the charge storage layer EC via the upper gate insulating film Tp made of the same insulating material. Thereby, the memory gate structure 4a has a structure in which the charge storage layer EC is insulated from the well W and the memory gate electrode MG by the lower gate insulating film Bo and the upper gate insulating film Tp. In addition to the above configuration, in the memory gate structure 4a, a film CP formed of an insulating material is formed on the memory gate electrode MG, and the film is separated from the upper surface of the memory gate electrode MG. In the manner of the film thickness of the CP, the vaporized layer S1 on the upper surface of the drain-side selective gate structure 5a and the vaporized layer S2 on the upper surface of the source-side selective gate structure 6a are formed. The memory gate electrode MG in the region of the memory cell 2a is configured such that the vaporized layer is not formed on the upper surface and the coating film CP is covered. Further, in the case of this embodiment, the film CP has a laminated structure as follows, that is, contains, for example, SiO ₂ On the lower cladding film CPa of the insulating material, the upper cladding film CPb is formed of an insulating material such as SiN which is different from the lower cladding film CPa. Here, the memory gate electrode MG of the memory gate structure 4a is provided with a wall-shaped first side wall 11 and a wall-shaped second side wall 12 disposed to face the first side wall 11. The memory gate structure 4a is formed with a lower gate insulating film Bo, a charge storage layer EC, an upper gate insulating film Tp, and a film along the first sidewall 11 and the second sidewall 12 of the memory gate electrode MG. The lower sidewall insulating film Bo, the charge storage layer EC, the upper gate insulating film Tp, and the coating film CP are formed on the first side wall 11 and the second side wall 12 of the memory gate electrode MG. The area between the two. In the memory gate structure 4a, along the sidewalls of the second sidewall 12 of the memory gate electrode MG, or the lower gate insulating film Bo, the charge accumulation layer EC, the upper gate insulating film Tp, and the film CP Further, a sidewall spacer 28a made of an insulating material is formed, and a drain-side selective gate structure 5a is adjacent to the sidewall spacer 28a. The sidewall spacer 28a formed between the memory gate structure 4a and the drain-side selection gate structure 5a is formed by a specific film thickness, and the memory gate structure 4a and the drain side can be formed. The gate structure 5a is selected to be insulated. Further, the film thickness of the sidewall spacers 28a between the memory gate structure 4a and the drain-side selection gate structure 5a is preferably such that the withstand voltage of the sidewall spacers 28a is poor, or the memory gate is used. The read current between the polar structure 4a and the drain side selective gate structure 5a is selected to be 5 [nm] or more and 40 [nm] or less. The drain-side selection gate structure 5a has a structure in which the film thickness is 9 [nm] or less, preferably 3 [nm] or less in the well W between the sidewall spacer 28a and the drain region WD. Further, a gate insulating film 30 is selected from the drain side of the insulating material, and a drain side selective gate electrode DG is formed on the drain side selective gate insulating film 30. Further, a gate electrode DG is selected as a drain electrode of the second selection gate electrode, a vaporized layer S1 is formed on the upper surface, and a drain side as a second selected gate line is connected to the germanide layer S1. Select the gate line DGL1. Further, the memory gate structure 4a is along the first side wall 11 of the memory gate electrode MG, or the lower gate insulating film Bo, the charge storage layer EC, the upper gate insulating film Tp, and the film CP. A sidewall spacer 28b made of an insulating material is formed on each of the side walls, and the source-side selective gate structure 6a is adjacent to the sidewall spacer 28b. The side wall spacer 28b formed between the memory gate structure 4a and the source side selective gate structure 6a is also selected to have a film thickness of 5 [nm] or more and 40 [nm] or less as a side wall spacer 28a. The memory gate structure 4a is insulated from the source side selection gate structure 6a. The source side selective gate structure 6a has a structure in which the film thickness is 9 [nm] or less, preferably 3 [nm] or less in the well W between the sidewall spacer 28b and the source region WS. Further, a gate insulating film 33 is selected from the source side of the insulating material, and a source-side selective gate electrode SG is formed on the source-side selective gate insulating film 33. Further, the gate electrode SG is selected as the source side of the first selection gate electrode, the vaporization layer S2 is formed on the upper surface, and the source side as the first selection gate line is connected to the vaporization layer S2. Select the gate line SGL. In addition, in the case of this embodiment, the source side selective gate electrode SG is formed along the first side wall 11 and the second side wall 12 of the memory gate electrode MG via the side wall spacers 28a and 28b. And the drain side selection gate electrode DG is formed in a side wall shape which is lowered toward the well W as it goes away from the memory gate electrode MG. In the memory cell 2a, the source side selective gate structure 6a and the drain side selective gate structure 5a are formed as side walls along the side walls (the first side wall 11 and the second side wall 12) of the memory gate structure 4a, respectively. And even if the source side selection gate structure 6a and the drain side selection gate structure 5a are close to the memory gate structure 4a, respectively, by being formed on the memory gate electrode MG The film CP separates the germanide layer S1 on the drain side selection gate electrode DG and the vaporization layer S2 on the source side selection gate electrode SG from the memory gate electrode MG, respectively, so that the film can be prevented accordingly. The short circuit of the silicide layers S1, S2 and the memory gate electrode MG. (1-2) Circuit Configuration of Nonvolatile Semiconductor Memory Device of the Present Invention Next, the circuit configuration of the nonvolatile semiconductor memory device of the present invention will be described. As shown in FIG. 2, the nonvolatile semiconductor memory device 1 is provided with a plurality of memory cells 2a, 2b, 2d, 2e, 2g, 2h, 2i, and 2j, for example, in a matrix. Further, each of the memory cells 2b, 2d, 2e, 2g, 2h, 2i, 2j has the same configuration as the memory cell 2a described with reference to Fig. 1, and has a memory gate electrode MG connected to the memory gate Line MGL; the drain side selects the gate electrode DG, which is connected with the drain side select gate line DGL1 (DGL2, DGL3, DGL4); and the source side select gate electrode SG, which is connected to the source side select gate Line SGL. The non-volatile semiconductor memory device 1 constitutes the memory cell forming portions 3a, 3b, 3c, and 3d for each of the memory cells 2a, 2b; 2d, 2e; 2g, 2h; 2i, 2j arranged in the column direction, for example, A specific substrate voltage is applied to the memory cells 2a, 2b, 2d, and 2e by the substrate voltage line Back. Further, the nonvolatile semiconductor memory device 1 is a memory cell 2a, 2d, 2g, 2i (2b, 2e, 2h) arranged in the row direction among the memory cells 2a, 2b, 2d, 2e, 2g, 2h, 2i, 2j. And 2j) sharing one bit line BL1 (BL2), which can be uniformly applied to each of the memory cells 2a, 2d, 2g, 2i, 2b, 2e, 2h, 2j in the row direction by the bit lines BL1, BL2 Specific bit voltage. Further, the nonvolatile semiconductor memory device 1 shares the drain side selection gate lines DGL1, DGL2, DGL3, and DGL4, for example, in each of the memory cell forming portions 3a, 3b, 3c, and 3d, and can be separated by the respective drain sides. The gate lines DGL1, DGL2, DGL3, and DGL4 are selected to apply a specific voltage to each of the memory cell forming portions 3a, 3b, 3c, and 3d. Further, in the nonvolatile semiconductor memory device 1, one memory gate line MGL and one source side selection gate are shared by all the memory cells 2a, 2b, 2d, 2e, 2g, 2h, 2i, 2j. The line SGL and the one source line SL can apply a specific memory gate voltage to the memory gate line MGL, and apply a specific source gate voltage to the source side selection gate line SGL to the source line. The SL applies a specific source voltage. (1-3) Voltages in Various Operation of Nonvolatile Semiconductor Memory Devices Next, various operations of the nonvolatile semiconductor memory device 1 will be described. 3 is a table showing an example of voltage values of respective portions in the following operation, that is, in the nonvolatile semiconductor memory device 1 shown in FIG. 2, for example, charge is injected into the charge accumulation layer EC of the memory cell 2a. When the data is written ("Prog"), the data storage operation is performed when the charge accumulation layer EC of the memory cell 2a accumulates charge ("Read"); and the charge accumulation of the memory cell 2a or the like is extracted. When the data of the charge in the layer EC is deleted ("Erase"). In the "Prog" column of Fig. 3, the voltage values ("selection row" and "selection column") when charge is injected into the charge accumulation layer EC of the memory cell 2a, and the charge which does not inject charge into the memory cell 2a are shown. The voltage value at the time of accumulating layer EC ("non-selected row" and "non-selected column"). For example, when a charge is injected into the charge accumulation layer EC of the memory cell 2a, as shown in the column of "Prog" of FIG. 3, 12 [V] can be applied to the memory gate electrode MG from the memory gate line MGL. The charge accumulates the gate voltage, and applies a substrate voltage of 0 [V] to the well W (described as "Back" in FIG. 3). Further, at this time, the gate-side selection gate electrode SG may apply a gate-off voltage of 0 [V] from the source-side selection gate line SGL, and apply 0 to the source region WS from the source line SL [ The source of V] is disconnected from the voltage. Thereby, the source side selection gate structure 6a blocks the source region WS and is electrically connected to the channel layer formation carrier region of the memory gate structure 4a, thereby preventing the source line SL from being transferred to the memory. The channel layer of the gate structure 4a forms a carrier region to apply a voltage. On the other hand, the drain gate side selectable gate electrode DG can be applied from the drain side select gate line DGL1. A gate voltage is selected on the drain side of 5 [V], and a charge accumulation bit voltage of 0 [V] is applied to the drain region WD from the bit line BL1. Thereby, the drain side selective gate structure 5a can electrically connect the drain region WD to the channel layer forming carrier region of the memory gate structure 4a. In the memory gate structure 4a, by electrically connecting the channel layer carrier formation region and the drain region WD, the carrier region is induced in the channel layer to induce a carrier, which is the same as the charge accumulation bit voltage. The channel layer of V] can be formed on the surface of the well W by a carrier. Thus, in the memory gate structure 4a, a large voltage difference (12 [V]) of 12 [V] is generated between the memory gate electrode MG and the channel layer, whereby the quantum tunneling effect is generated. On the other hand, a charge can be injected into the charge storage layer EC, and the data can be written. Further, when the charge accumulation gate voltage required to inject a charge into the charge accumulation layer EC is applied to the memory gate electrode MG of the memory cell 2a, when the memory cell 2a prevents the charge from being injected into the charge accumulation layer EC, By the source side selection gate structure 6a, the well W and the source region WS in the region facing the memory gate electrode MG are electrically connected, and the gate structure is selected by the drain side. 5a blocks the well W of the region opposite to the memory gate electrode MG and the electrical connection with the drain region WD. Thereby, in the memory cell 2a in which the data is not written, the depletion layer is formed in the channel layer formation carrier region, and the potential on the surface of the well W rises based on the charge accumulation gate voltage, due to the memory gate electrode The potential difference between the surface of the MG and the well W is reduced, so that it is possible to prevent the charge from being injected into the charge accumulation layer EC. Further, in the data reading operation shown in the "read" column of Fig. 3, for example, the bit line BL1 connected to the memory cell 2a to be read is precharged to 1. 5[V], and the source line SL is set to 0 [V], and the potential of the bit line BL1 which changes according to whether or not the memory cell 2a flows current is detected, whereby it is judged whether or not the charge accumulation layer EC of the memory cell 2a is Accumulated with electric charge. Specifically, when the data of the memory cell 2a is read, when the charge accumulation layer EC of the memory gate structure 4a accumulates a charge (in the case of writing data), the memory gate structure is The well W immediately below the body 4a is in a non-conducting state, so that the electrical connection between the drain region WD and the source region WS can be blocked. Thereby, in the memory cell 2a of the read data, the bit line BL1 connected to the drain region WD is 1. The read voltage of 5[V] can be maintained. On the other hand, when the data of the memory cell 2a is read, when the charge is not accumulated in the charge accumulation layer EC of the memory gate structure 4a (in the case where no data is written), the memory gate structure The well W immediately below 4a is turned on, and the drain region WD is electrically connected to the source region WS. As a result, the source line SL of 0 [V], and 1. The bit line BL1 of 5 [V] is electrically connected via the memory cell 2a. Thereby, in the memory cell 2a of the read data, the read voltage of the bit line BL1 is applied to the source line SL of 0 [V], thereby being applied to the bit line BL1. The read voltage of 5[V] is lowered. in this way, In the non-volatile semiconductor memory device 1, By detecting whether the read voltage of the bit line BL1 changes, The reading operation of whether or not the charge accumulation layer EC of the memory cell 2a accumulates electric charge can be performed. Furthermore, It is possible to connect the memory cell 2b to which only unread data is connected, 2e, 2h, A non-read voltage of 0 [V] is applied to the bit line BL2 of 2j. Incidentally, When the data of the electric charge in the charge accumulation layer EC of the memory cell 2a is deleted ("Erase" in Fig. 3), Applying a memory gate voltage of -12 [V] to the memory gate electrode MG from the memory gate line MGL, The charge in the charge accumulation layer EC can be extracted toward the well W of 0 [V] to delete the data. (1-4) The planar layout of the non-volatile semiconductor memory device is second, The planar layout of the above-described nonvolatile semiconductor memory device 1 will be described below. 4 is a view showing a plurality of memory cell forming portions 3a disposed on a semiconductor substrate as viewed from above the semiconductor substrate, 3b, 3c, A schematic view of the planar layout of the non-volatile semiconductor memory device 1 of the present invention. Furthermore, Due to the memory cell forming portion 3a, 3b, 3c, ...with the same composition, Therefore, the following description will be made focusing on a memory cell forming portion 3a. Incidentally, Fig. 1 showing the cross-sectional structure of the memory cell 2a is a cross-sectional structure of the A-A' portion of Fig. 4. also, In Figure 4, The sidewall spacer 28a formed on the side wall of the memory gate structure 4a shown in FIG. 1 is omitted, Other than 28b, The side wall SW or the vaporized layer S1 formed on the drain side selective gate structure 5a and the source side selective gate structure 6a is also omitted. Graphic of S2, etc. Furthermore, In the case of this embodiment, Memory cell forming portion 3a, 3b, 3c, ... extending in one direction (in the direction of the series in Figure 4), And disposed on the semiconductor substrate in parallel with a specific distance being set. In this case, The memory cell forming portion 3a has a selective gate forming region ER9, The source gate selection gate electrode SG and the drain side selection gate electrode DG are disposed opposite to each other via the memory gate electrode MG. The gate formation region ER9 is selected to include: Memory cell area ER3, a plurality of memory cells 2a are formed along the length direction of the memory cell forming portion 3a, 2b, 2c; Selecting the gate contact area ER6, It is disposed at one end of the memory cell region ER3; And another selection of the gate contact area ER7, It is disposed at the other end of the memory cell region ER3. Incidentally, The other memory cell forming part 3b (3c) is a plurality of memory cells 2d, 2e, 2f (2g, 2h, 2i) is formed in the memory cell region ER3 along the length direction. The memory cell forming portion 3a (3b, shown in FIG. 2) 3c), Only the memory cell 2a is shown, 2b (2d, 2e, 2g, 2h), However, in FIG. 4, there is also a memory cell 2b with the second row (2e, 2h) Memory cell 2c adjacent to the third row (2f, 2i). Actually, In the memory cell forming portion 3a, A memory gate electrode MG extending in one direction is formed in the selection gate formation region ER9. The memory gate electrode MG that selects the gate formation region ER9 has: First side wall, It extends throughout the selection gate formation region ER9; And the second side wall 12, Arranging opposite to the first side wall; And the source-side selection gate electrode SG is disposed along the first sidewall 11 A drain side selective gate electrode DG is disposed along the second side wall 12. Here, In the memory cell area ER3, Forming a well W of a specific shape on the surface of the semiconductor substrate, For example, a memory configuration area W1 formed in a strip shape in the well W W2 W3, The memory cell forming portion 3a is disposed in an intersecting manner. In the memory cell region ER3 of the memory cell forming portion 3a, Having a memory gate structure 4a, Selecting the gate structure 5a on the drain side, And the source side selects the memory cell 2a of the gate structure 6a (2b, 2c) formed in the memory configuration area W1 (W2 W3). Well W memory configuration area W1 W2 W3 is divided into a source region WS side and a drain region WD side with the memory gate structure 4a as a boundary. Each memory configuration area W1 W2 W3 is in the memory cell forming portion 3a, The undone regions WD between 3b are separated from each other. And each has a configuration in which columnar bit contacts BC are individually provided. Different bit lines BL1 are connected to each of the element contacts BC BL2 ……(figure 2), Self-corresponding bit line BL1 BL2 ... apply a specific bit voltage individually. With this, Each of the drain regions WD of the memory cell forming portion 3a can be different from the different bit lines BL1, respectively. BL2 ... applying a specific bit voltage via the bit contact BC. Furthermore, In the case of this embodiment, Since the drain region WD is also shared by another memory cell forming portion 3b connected to one memory cell forming portion 3a, Therefore, it is also possible to connect the memory cell 2a with a memory cell forming portion 3a (2b, 2c) the same bit voltage is applied to the memory cell 2d of another memory cell forming portion 3b (2e, 2f). on the other hand, Memory configuration area W1 W2 The source regions WS of W3 are connected to each other. And the columnar source contact SC disposed at a specific position is shared. The source contact SC has a structure in which a source line SL (FIG. 2) is connected, And the area W1 can be configured for each memory. W2 The source region WS of W3 uniformly applies a specific source voltage applied from the source line SL. In the case of this embodiment, In the memory cell forming portion 3a, The first sidewall 11 of the memory gate electrode MG is disposed on the source region WS side of the well W, A source-side selective gate structure 6a is formed along the first sidewall 11 of the memory gate electrode MG. also, In the memory cell forming portion 3a, a second sidewall 12 of the memory gate electrode MG is disposed on the drain region WD side of the well W, A drain-side selective gate structure 5a is formed along the second sidewall 12 of the memory gate electrode MG. Selecting the gate structure 6a on the source side, A source-side selective gate electrode SG having a sidewall shape is formed along the first sidewall 11 of the memory gate structure 4a. Further, a wide selective gate contact forming portion Ca formed integrally with the source side selection gate electrode SG is formed in a selection gate contact region ER7. Furthermore, The selected gate contact forming portion Ca is formed with: Cross the upper part, It straddles the memory gate electrode MG; And the plane, The surface of the system is formed in a planar shape along the semiconductor substrate; Further, a columnar source side selection gate contact SGC connected to the source side selection gate line (not shown) is provided on the plane portion. With this, Even if the narrow side and the inclined side wall-shaped source side selects the gate electrode SG, The specific voltage from the source side selection gate line SGL may be applied via the source side selection gate contact SGC and the selection gate contact forming portion Ca. also, Selecting the gate structure 5a on the side of the drain, A sidewall-shaped drain-side selective gate electrode DG is formed along the second sidewall 12 of the memory gate structure 4a. And a wide selection gate contact forming portion Cb formed integrally with the drain side selection gate electrode DG, Formed in another select gate contact region ER6. The selected gate contact forming portion Cb is also formed with: Cross the upper part, It straddles the memory gate electrode MG; And the plane, The surface of the system is formed in a planar shape along the semiconductor substrate; Further, a columnar drain side selection gate contact DGC to which the drain side selection gate line DGL1 is connected is disposed on the plane portion. With this, Even if the width is narrow and the side wall of the inclined side is selected as the gate electrode DG, The gate contact DGC and the gate contact forming portion Cb may be selected via the drain side, A specific voltage from the drain side selection gate line DGL1 is applied. Incidentally, About setting in the gate contact area ER7, ER6 selects the gate contact forming portion Ca, Cb, If it is connected to the source side selection gate electrode SG or the drain side selection gate electrode DG, And a source side selective gate contact SGC or a drain side selective gate contact DGC may be formed. Can be set to other various shapes, also, As long as the gate contact area ER7 is selected, Within ER6, It can be formed in various locations of one or both of them. In addition to the above composition, In the memory cell forming portion 3a, An electrical cut-off area ER2 (ER4) is disposed at the end of the selected gate contact region ER6 (ER7), A solid cut region ER1 (ER5) is disposed at the end of the electrical cut region ER2 (ER4). In the electrical cut-off area ER2 (ER4) and the physical cut-off area ER1 (ER5), An extension electrode portion 15a (15b) formed by directly extending the memory gate electrode MG from the selection gate formation region ER9 is provided. In the case of this embodiment, The extension electrode portion 15a (15b) is formed in a U shape as viewed from above the semiconductor substrate. And the end of the self-selected gate formation region ER9 extends to the physical cut region ER1 (ER5) via the electrical cut region ER2 (ER4), The solid cut region ER1 (ER5) is folded back and extended again to the electrical cut-off region ER2 (ER4). Actually, The extension electrode portion 15a (15b) includes: Extension 16a, The memory gate electrode MG of the self-selected gate formation region ER9 extends linearly; Linear end 16b, It is formed at a laterally outer position of the extension portion 16a; And the connecting portion 16c, The connecting portion 16a and the end portion 16b are connected; And the extension portion 16a and the end portion 16b are disposed in the electrical cut-off region ER2, The connecting portion (side wall non-forming portion) 16c to be the folded portion is disposed in the solid cutting region ER1. Furthermore, In the case of this embodiment, The extending electrode portion 15a is folded back to the first side wall 11 side of the memory gate electrode MG, and the end portion 16b is disposed on the first side wall 11 side. on the other hand, The other extension electrode portion 15b is folded back to the second side wall 12 side of the memory gate electrode MG, and the end portion 16b is disposed on the second side wall 12 side. In the electrical cut-off area ER2 (ER4), The self-selected gate formation region ER9 is provided with a memory gate electrode MG extending as an extension electrode portion 15a (15b), But unlike the gate forming region ER9, The source side selection gate electrode SG and the drain side selection gate electrode DG are not extended, Instead of the source side selection gate electrode SG and the drain side selection gate electrode DG, Four electrical cut-off portions 13a are formed on the side walls of the extending electrode portion 15a (15b), 13b, 13c, 13d (13e, 13f, 13g, 13h). Here, The electrical cut-off portion 13a, 13b, 13c, 13d (13e, 13f, 13g, 13h) all have the same composition, a sidewall-shaped intrinsic semiconductor layer Ia made of i-type, Ib, Forming a conductive semiconductor layer OC opposite to the sidewall shape, And having the intrinsic semiconductor layer Ia, A structure of the opposite conductivity type semiconductor layer OC is formed between Ib. Furthermore, The opposite-conductivity-type semiconductor layer OC is formed by a conductivity type (p-type in this case) different from the source-side selection gate electrode SG and the drain-side selection gate electrode DG. Extending the extension portion 16a of the electrode portion 15a, An electrical cut-off portion 13a is formed along one side wall of the same plane as the first side wall 11 of the memory gate electrode MG. Another electrically cut portion 13c is formed along the other side wall that is connected to the same plane as the second side wall 12 of the memory gate electrode MG. In the memory cell forming portion 3a, For example, the n-type source side selection gate electrode SG can be used as a starting point by the electrical cut-off portion 13a. The first side wall 11 of the memory gate electrode MG forms a pin junction along the side wall of the extension portion 16a. also, In the memory cell forming portion 3a, Similarly, Even on the second side wall 12 side of the memory gate electrode MG, For example, the n-type drain side selection gate electrode DG may be used as a starting point by the electrical cut-off portion 13c. A pin joint surface is formed from the second side wall 12 along the side wall of the extending portion 16a. Furthermore, Extending the end portion 16b of the electrode portion 15a, Forming an electrical cut-off portion 13b on a sidewall opposite to the extending portion 16a, Another electrical cut-off portion 13d is formed on the side wall disposed on the outer side. With this, Extending the electrode portion 15a, The gate side selection gate electrode SG formed from the source side along the first sidewall 11 of the memory gate electrode MG to the drain side selection gate electrode DG formed along the second sidewall 12 of the memory gate electrode MG The side wall between them, Four electrical cut-off portions 13a can be formed in sequence, 13b, 13d, 13c. With this, Three or more opposite conductive semiconductor layers and intrinsic semiconductor layers are provided on the sidewall of the extended electrode portion 15a. With this, For example, even if foreign matter adheres to the electrical cut-off portion 13a of the extending portion 16a, Or the connecting unit 16c, which will be described later, And the source side selects the gate electrode SG, The electrical cut-off portion 13b of the end portion 16b is turned on. Or by the electrical cutting portion 13b, 13d, the n-type source side selection gate electrode SG is used as a starting point. The first side wall 11 of the memory gate electrode MG forms a pin junction along the side wall of the end portion 16b. In addition to the above composition, The connecting portion 16c as a sidewall non-forming portion in the solid cutting region ER1, A solid cutting portion 14a is formed on the peripheral wall and the inner peripheral wall of the side wall of the extending portion 16a and the side wall of the end portion 16b. 14b. The entity cutting unit 14a, 14b has a conductive layer such as a semiconductor material which is not provided along the outer peripheral wall and the inner peripheral wall of the connecting portion 16c. The outer peripheral wall and the inner peripheral wall of the connecting portion 16c are exposed to the outside. With this, Solid cutting portion 14a, 14b selects the gate electrode SG on the source side, A gap is formed between the gate electrode DG and the drain electrode DG to form an entity cutoff. Further, the source side selection gate electrode SG and the drain side selection gate electrode DG can be in a non-conduction state. Furthermore, In the case of this embodiment, A solid cutting portion 14a is formed along the outer peripheral wall of the connecting portion 16c. And an electrical cut-off portion 13c formed on one side wall of the extending portion 16a, Forming a gap with the electrically cut portion 13d formed on one of the side walls of the end portion 16b, And the electrical cut-off portion 13c, 13d is non-conducting with each other. also, The other solid cutting portion 14b is formed along the inner peripheral wall of the connecting portion 16c. And in the electrical cut-off portion 13a formed on the other side wall of the extending portion 16a, Forming a gap with the electrically cut portion 13b formed on the other side wall of the end portion 16b, And the electrical cut-off portion 13a, 13c are non-conducting with each other. in this way, Extending the electrode portion 15a, The gate side selection gate electrode SG formed from the source side along the first sidewall 11 of the memory gate electrode MG to the drain side selection gate electrode DG formed along the second sidewall 12 of the memory gate electrode MG The side wall between them, The electrical cutting portion 13a can be arranged in sequence, Solid cutting portion 14b, Electrical cut-off portion 13b, 13d, The solid cutting portion 14a and the electrical cutting portion 13c. in this way, The extending electrode portion 15a can be formed by the four electrical cutting portions 13a, 13b, 13d, 13c, With two solid cutting portions 14a, 14b, The source side selection gate electrode SG and the drain side selection gate electrode DG are prevented from being turned on. Incidentally, Similarly, the other extending electrode portion 15b disposed at the other end of the memory cell forming portion 3a is similarly In the extension 16a, An electrical cut-off portion 13e is formed along a sidewall of the same plane that is connected to the first sidewall 11 of the memory gate electrode MG. The other electrically cut portion 13g is formed along the other side wall which is connected to the same plane as the second side wall 12 of the memory gate electrode MG. also, The other end portion 16b of the electrode portion 15b is extended, An electrical cut-off portion 13h is formed on a sidewall opposite to the extending portion 16a. Another electrical cut-off portion 13f is formed on the side wall disposed on the outer side. With this, Extending the electrode portion 15b, The gate side selection gate electrode SG formed from the source side along the first sidewall 11 of the memory gate electrode MG to the drain side selection gate electrode DG formed along the second sidewall 12 of the memory gate electrode MG The side wall between them, Four electrical cut-off portions 13e can be formed in sequence, 13f, 13h, 13g. In addition to the above composition, That is, it is convenient to be in the connection portion 16c of the other entity cutting area ER5, A solid cut portion 14c is also formed on the peripheral wall and the inner peripheral wall of the side wall of the extending portion 16a and the side wall of the end portion 16b. 14d. The entity cutting unit 14c, 14d also has a conductive layer such as a semiconductor material which is not provided along the outer peripheral wall and the inner peripheral wall of the connecting portion 16c. The outer peripheral wall and the inner peripheral wall of the connecting portion 16c are exposed to the outside. With this, Solid cutting portion 14c, 14d selects the gate electrode SG on the source side, Forming a gap between the gate electrode DG and the gate electrode DG to form a solid cut, Therefore, the source side selection gate electrode SG and the drain side selection gate electrode DG can be in a non-conduction state. Furthermore, In the case of this embodiment, A solid cutting portion 14c is formed along the outer peripheral wall of the connecting portion 16c. And the electrical cut-off portion 13e formed on one side wall of the extending portion 16a, The electrically cut portion 13f formed on one of the side walls of the end portion 16b is in a non-conducting state. also, The other solid cutting portion 14d is formed along the inner peripheral wall of the connecting portion 16c. And the electrical cut-off portion 13g formed on the other side wall of the extending portion 16a, The electrically cut portion 13h formed on the other side wall of the end portion 16b is in a non-conducting state. in this way, Even if it is provided with another extension electrode portion 15b provided by the object of the extension electrode portion 15a, The gate side selection gate electrode SG formed along the first side wall 11 along the memory gate electrode MG and the drain side selective gate electrode formed along the second side wall 12 of the memory gate electrode MG The side wall between DG, The electrical cut-off portion 13e is arranged in sequence, Solid cutting portion 14c, Electrical cut-off portion 13f, 13h, The solid cutting portion 14d and the electrical cutting portion 13g. in this way, Even if the electrode portion 15b is extended, The four electrical cut-offs 13e, 13f, 13h, 13g, With two solid cutting portions 14c, In 14d, the source side selection gate electrode SG and the drain side selection gate electrode DG are prevented from being turned on. Incidentally, Since the other memory cell forming portion 3b adjacent to the memory cell forming portion 3a shares the drain region WD between the memory cell forming portion 3a and the memory cell forming portion 3a, Therefore, the second side wall 12 of the memory gate electrode MG on which the drain side selective gate electrode DG is disposed can be disposed to face the second side wall 12 of the memory gate electrode MG of the memory cell forming portion 3a. also, The memory cell forming portion 3b is in an electrical cut-off region ER2 and an entity cut-off region ER1, An extension electrode portion 15c having an end portion 16b disposed on a side adjacent to one of the memory cell forming portions 3a, And in another electrical cut-off area ER4 and an entity cut-off area ER5, The extending electrode portion 15d having the end portion 16b disposed on the adjacent memory cell forming portion 3c side is provided. With this, Between the memory cell forming portion 3a of the first column and the memory cell forming portion 3b of the second row, The end portion 16b and the connecting portion 16c of the extending electrode portion 15c of the second column memory cell forming portion 3b may be disposed in the one electrically cut region ER2 and the solid cut region ER1; The other end portion 16b and the connecting portion 16c of the extending electrode portion 15b of the first column memory cell forming portion 3a are disposed in the other electrically cut region ER4 and the solid cut region ER5. in this way, In the non-volatile semiconductor memory device 1, In the adjacent memory cell forming portion 3a, 3b, Arranging the end portions 16b of the memory cell forming portion 3a in the column direction, With the end portion 16b of the other memory cell forming portion 3b, And avoiding the adjacent memory cell forming portion 3a, The expansion of the two end portions 16b between 3b in the row direction is caused by the continuous arrangement. Therefore, it is possible to achieve miniaturization, Highly dense. Here, The memory cell forming portion 3a is on the memory gate electrode MG of the selection gate forming region ER9, An electrical cut-off region ER2 formed by extending the memory gate electrode MG A film CP is formed on each of the extension portion 16a and the end portion 16b of the ER 4 . With this, In the memory cell forming portion 3a, In the manufacturing process, The memory gate electrode MG or the extension portion 16a can be prevented by the film CP, The upper surface of the end portion 16b is self-aligned. on the other hand, In the physical cut-off area ER1 In ER5, The film CP is not formed on the connecting portion 16c formed by the extension of the memory gate electrode MG. Since the connecting portion 16c is exposed to the outside, Therefore, the upper surface is self-aligned, A columnar memory gate contact MGC is provided via a vapor layer (not shown) formed on the connecting portion 16c. A memory gate line MGL (Fig. 2) is connected to the memory gate contact MGC. A specific voltage from the memory gate line MGL can be applied. With this, For the memory gate electrode MG of the gate forming region ER9, The electrode portion 15a can be extended from the memory gate contact MGC via the extension, 15b applies the voltage of the memory gate line MGL. in this way, In the non-volatile semiconductor memory device 1, In the memory cell area ER3, Or select the gate contact area ER6, The memory gate electrode MG of ER7 is covered by the film CP, But for the solid cut area ER1 The ER5 exposed connection portion 16c applies a specific voltage via the memory gate contact MGC, Thereby, a specific voltage can be applied to the memory gate electrode MG covered by the film CP in the memory cell region ER3. Incidentally, Since the non-volatile semiconductor memory device 1 can be implemented by a general CMOS (Complementary MOS: Complementary MOS) manufacturing process, ie film forming step, Resist coating step, Exposure development step, Etching step, Impurity injection step, It is produced by each step such as a resist stripping step. Therefore, the manufacturing method is omitted here. (1-5) Functions and effects in the above composition, In the memory cell forming portion 3a, The extension electrode portion 15a formed by extending the memory gate electrode MG of the selection gate formation region ER9 of the drain side selection gate structure 6a and the drain side selection gate structure 5a, 15b is set in the electrical cut-off area ER2 ER4 and physical cut-off area ER1 ER5. also, In the memory cell forming portion 3a, Along the side wall of the electrode portion 15a (15b), Between the selection of the gate electrode SG from the source side and the selection of the gate electrode DG on the drain side, Providing four electrical cut-off portions 13a that form a pin joint structure, 13b, 13d, 13c (13e, 13f, 13h, 13g). in this way, In the memory cell forming portion 3a, The four electrical cut-off portions 13a capable of cutting the source side selective gate electrode SG and the drain side selective gate electrode DG are provided along the side wall of the electrode portion 15a (15b). 13b, 13d, 13c (13e, 13f, 13h, 13g), Since the source side selection gate electrode SG and the drain side selection gate electrode DG are cut off from the previous increase, Therefore, it is possible to prevent the readout malfunction caused by the voltage fluctuation at the time of the data reading operation. also, In the memory cell forming portion 3a, The electrical cut-off portion 13a formed along the side wall of the electrode portion 15a extending, 13b (13b, 13d), Providing a sidewall-shaped solid cut portion 14b (14a) in which a semiconductor material is not formed, By the solid cutting portion 14b (14a), The source side selection gate electrode SG and the drain side selection gate electrode DG can be made non-conductive. in this way, In the memory cell forming portion 3a, The cutting principle and the electrical cut-off portion 13a for cutting off the source side selective gate electrode SG and the drain side selective gate electrode DG are also separately provided. 13b, 13d, 13c different physical cutting portion 14b (14a), And only the electrical cut-off portion 13a is provided, 13b, 13d, Compared with the situation of 13c, The source side selection gate electrode SG and the drain side selection gate electrode DG can be cut off more surely. Furthermore, In the memory cell forming portion 3a, The extended electrode portion 15a (15b) is folded back in the solid cut region ER1 (ER5). And a plurality of electrical cut-off portions 13a are formed in the electrical cut-off region ER2 (ER4), 13b, 13d, 13c (13e, 13f, 13h, 13g) Side by side configuration. With this, In the memory cell forming portion 3a, That is, the electrode portion 15a (15b) for facilitating the extension is provided with a plurality of electrical cut-off portions 13a, 13b, 13d, 13c (13e, 13f, 13h, 13g), It is also possible to prevent the layout area from expanding toward the length of the memory cell forming portion 3a. (2) The planar layout of the nonvolatile semiconductor memory device of the second embodiment is in the above embodiment. As an extension electrode portion in which three or more electrical cutting portions are formed, And the formation of four electrical cut-offs 13a, 13b, 13d, 13c (13e, 13f, 13h, 13g) of the extension electrode portion 15a (15b) is described, However, the present invention is not limited to this. The extension electrode portion can be configured in various configurations as long as three or more electrical cutting portions are formed. E.g, 5 is a plan layout of the nonvolatile semiconductor memory device 21 of the second embodiment, with the same reference numerals as those in FIG. Also shown in the extension electrode portion 25a (25b) are provided with six electrical cut-off portions 23a, 23b, 23c, 23f, 23e, The composition of 23d. Furthermore, Due to the memory cell forming portion 23a, 23b, 23c, ...all have the same composition, Therefore, the following description will be made focusing on a memory cell forming portion 22a. also, Regarding the part corresponding to FIG. 4, since the description is repeated, Therefore, the description of the overlapping portion is omitted here. In the case of this embodiment, The electrode portion 25a (25b) extending from the memory cell forming portion 22a is formed in an E shape as viewed from above the semiconductor substrate. And the end of the self-selected gate formation region ER9 extends to the physical cut region ER1 (ER5) via the electrical cut region ER2 (ER4), In the solid cut region ER1 (ER5), the memory gate electrode MG is divided into two directions, and is folded back toward the first side wall 11 side and the second side wall 12 side of the memory gate electrode MG. And extended to the electrical cut-off area ER2 (ER4). Actually, The extension electrode portion 25a (25b) includes: Extension 26a, The memory gate electrode MG of the self-selected gate formation region ER9 extends linearly; Linear end 26b, 26c, Formed at a laterally outer position of the extension 26a; And a connecting portion (side wall non-forming portion) 26d, It will extend portion 26a and end portion 26b, 26c connection; And the extension portion 26a and the end portion 26b, 26c is disposed in the electrical cut-off area ER2 (ER4), The connecting portion 26d that becomes the folded portion is disposed in the solid cutting region ER1 (ER5). Furthermore, In the case of this embodiment, The extending electrode portion 25a (25b) is disposed such that the one end portion 26b is disposed on the first side wall 11 side of the memory gate electrode MG. The other end portion 26c is disposed on the second side wall 12 side of the memory gate electrode MG. In the electrical cut-off area ER2 (ER4), The memory gate electrode MG is extended from the selection gate formation region ER9 as the extension electrode portion 25a (25b). But unlike the gate forming region ER9, The source side selection gate electrode SG and the drain side selection gate electrode DG are not extended, Instead of the source side selection gate electrode SG and the drain side selection gate electrode DG, six electrical cutoff portions 23a are formed on the side walls of the extended electrode portion 25a (25b), 23b, 23c, 23f, 23e, 23d. Here, The electrical cut-off portion 23a, 23b, 23c, 23f, 23e, 23d all have the same composition, a sidewall-shaped intrinsic semiconductor layer Ia made of i-type, Ib, Forming a conductive semiconductor layer OC opposite to the sidewall shape, And having the intrinsic semiconductor layer Ia, A structure of the opposite conductivity type semiconductor layer OC is formed between Ib. Furthermore, The opposite-conductivity-type semiconductor layer OC is formed of a conductivity type (p-type in this case) different from the source-side selection gate electrode SG and the drain-side selection gate electrode DG. In this case, Extending the extension portion 26a of the electrode portion 25a (25b), An electrical cut-off portion 23a is formed along one side wall of the same plane as the first side wall 11 of the memory gate electrode MG. The other electrically cut portion 23d is formed along the other side wall of the same plane as the second side wall 12 of the memory gate electrode MG. In the memory cell forming portion 22a, For example, the n-type source side selection gate electrode SG can be used as a starting point by the electrical cut-off portion 23a. The first side wall 11 of the memory gate electrode MG forms a pin junction along the side wall of the extension portion 26a. also, In the memory cell forming portion 22a, Similarly, That is, it is convenient for the second side wall 12 side of the memory gate electrode MG, For example, the pin-shaped surface may be formed from the second side wall 12 along the side wall of the extending portion 26a by using the electric-cutting portion 23d with the n-type drain-side selective gate electrode DG as a starting point. Furthermore, Arranged on one end portion 26b of the first side wall 11 side of the memory gate electrode MG, Forming an electrical cut-off portion 23b on a sidewall opposite to the extending portion 26a, Further, another electrically cut portion 23c is formed on the side wall disposed on the outer side. also, The other end portion 26c disposed on the second side wall 12 side of the memory gate electrode MG, An electrical cut-off portion 23e is also formed on the side wall opposite to the extending portion 26a. Another electrical cut-off portion 23f is formed on the side wall disposed on the outer side. With this, Extending the electrode portion 25a (25b), The gate side selection gate electrode SG formed from the source side along the first sidewall 11 of the memory gate electrode MG to the drain side selection gate electrode DG formed along the second sidewall 12 of the memory gate electrode MG The side wall between them, Six electrical cut-off portions 23a can be formed in sequence, 23b, 23c, 23f, 23e, 23d. With this, Extending the electrode portion 25a, Side wall of 25b, Three or more opposite conductivity type semiconductor layers and intrinsic semiconductor layers are provided. With this, For example, even if foreign matter adheres to the electrical cut-off portion 23a of the extending portion 26a, Or the connecting unit 26d, which will be described later, It is assumed that the gate electrode SG is electrically connected to the electrical cutoff portion 23b of the end portion 26b from the source side, and is electrically turned on due to foreign matter. By the remaining electrical cut-off portion 23b, 23d, 23f, 23e, 23d formed pin junction, The source side selection gate electrode SG and the drain side selection gate electrode DG are electrically cut. In addition to the above composition, The connecting portion 26d as a sidewall non-forming portion in the solid cutting region ER1, In the side wall of one of the extensions 26a, An inner cut wall 24b is formed on an inner peripheral wall that is connected to a side wall of one end portion 26b on the first side wall 11 side, In the other side wall of the extension 26a, The other inner peripheral wall that is connected to the side wall of the other end portion 26c on the side of the second side wall 12 is formed with a solid cut portion 24c. Furthermore, At the end portion 26b, A solid cut portion 24a is also formed on the peripheral wall of the side wall of the 26c. The entity cutting unit 24a, 24b, 24c has a conductive layer such as a semiconductor material that is not provided along the outer peripheral wall and the inner peripheral wall of the connecting portion 26d. The outer peripheral wall and the inner peripheral wall of the connecting portion 26d are exposed to the outside. With this, Solid cutting portion 24a, 24b, 24c selects the gate electrode SG on the source side, Forming a gap between the gate electrode DG and the gate electrode DG to form a solid cut, Therefore, the source side selection gate electrode SG and the drain side selection gate electrode DG can be in a non-conduction state. Furthermore, In the case of this embodiment, The first solid cutting portion 24a is connected to the end portion 26b, a peripheral wall of the connecting portion 26c of the side wall of 26c is formed, And the electrical cut-off portion 23c formed on the side wall of the one end portion 26b, Forming a gap with the electrically cut portion 23f formed on the side wall of the other end portion 26c, And the electrical cut-off portion 23c, 23f is non-conducting with each other. also, The second solid cutting portion 24b is formed along an inner peripheral wall of one of the connecting portions 26d connected to the side wall of the extending portion 26a and the side wall of the end portion 26b. And an electrical cut-off portion 23a formed on one of the side walls of the extending portion 26a, Forming a gap with the electrically cut portion 23b formed on the side wall of the end portion 26b, And the electrical cut-off portion 23a, 23b is non-conducting with each other. Furthermore, The third solid cutting portion 24c is formed along the other inner peripheral wall of the connecting portion 26d that is connected to the side wall of the extending portion 26a and the side wall of the end portion 26c. And another electrically cut portion 23d formed on the side wall of the extending portion 26a, Forming a gap with the electrically cut portion 23e formed on the side wall of the end portion 26c, And the electrical cut-off portion 23d, 23e are non-conducting with each other. in this way, The extension electrode portion 25a (25b) is formed from the source side selection gate electrode SG formed along the first side wall 11 of the memory gate electrode MG to the second side wall 12 along the memory gate electrode MG. The drain side selects the sidewall between the gate electrode DG, The electrical cutting portion 23a can be arranged in sequence, Solid cutting portion 24b, Electrical cut-off portion 23b, 23c, Solid cutting portion 24a, Electrical cut-off portion 23f, 23e, The solid cutting portion 24c and the electrical cutting portion 23d. in this way, The extending electrode portion 15a can be provided by the six electrical cutting portions 23a, 23b, 23c, 23f, 23e, 23d, With three solid cutting portions 24b, 24a, 24c, The source side selection gate electrode SG and the drain side selection gate electrode DG are prevented from being in an on state. In the above composition, That is, it is convenient in the memory cell forming portion 22a, Further, six electrical cut-off portions 23a capable of cutting the source side selective gate electrode SG and the drain side selective gate electrode DG are provided along the side wall of the extending electrode portion 25a (25b), 23b, 23c, 23f, 23e, 23d, Since the source side selection gate electrode SG and the drain side selection gate electrode DG are cut off from the previous increase, Therefore, it is possible to prevent the readout malfunction caused by the voltage fluctuation at the time of the data reading operation. also, In the memory cell forming portion 22a, An electrical cut-off portion 23a formed along a side wall of the electrode portion 25a (25b) extending, 23b, Or the electrical cut-off portion 23c, 23f, Electrical cut-off portion 23e, 23d, Providing a sidewall-shaped solid cut portion 24b in which a semiconductor material is not formed, 24a, 24c, By three solid cutting portions 24b, 24a, 24c, The source side selection gate electrode SG and the drain side selection gate electrode DG can be made non-conductive. in this way, In the memory cell forming portion 22a, The cutting principle and the electrical cut-off portion 23a for cutting off the source side selection gate electrode SG and the drain side selection gate electrode DG are also separately provided. 23b, 23c, 23f, 23e, 23d different physical cutting part 24b, 24a, 24c, And only the electrical cut-off portion 23a, 23b, 23c, 23f, 23e, Compared to the situation of 23d, The source side selection gate electrode SG and the drain side selection gate electrode DG can be cut off more surely. also, That is, in the memory cell forming portion 22a, The extended electrode portion 25a (25b) is folded back in the solid cut region ER1 (ER5). And in the electrical cut-off region ER2 (ER4), the plurality of electrical cut-off portions 23a, 23b, 23c, 23f, 23e, 23d side by side configuration, With this, The layout area can be suppressed from expanding in the longitudinal direction of the memory cell forming portion 22a. (3) The planar layout of the nonvolatile semiconductor memory device of the third embodiment is in the above embodiment. For setting the extension electrode portion 15a, 15b as the memory cell forming portion 3a, 3b, Part of the composition of 3c, And in each memory cell forming portion 3a, 3b, A nonvolatile semiconductor memory device 1 in which each of 3c is independently constructed is described. However, the present invention is not limited to this. For example, it may be a non-volatile semiconductor memory device 31 as follows. which is, As shown in Fig. 6 which is denoted by the same reference numeral as the portion corresponding to Fig. 4, And the memory cell forming portion 32a, 32b, 32c, ...the extension electrode portion 35a is provided differently, 35b, Extending the electrode portion 35a, 35b is connected to each of the memory cell forming portions 32a, 32b, 32c. In this case, Memory cell forming portion 32a (32b, 32c) having a gate formation region ER9, It is separated by a memory gate structure 4a (4b, 4c) and the opposite side of the configuration of the source side select gate structure 6a (6b, 6c) and the drain side select gate structure 5a (5b, 5c). also, In each memory cell forming portion 32a, 32b, Each memory gate structure 4a of 32c, 4b, 4c, The memory gate electrode MG extending in the column direction is disposed in the selection gate formation region ER9, A film CP is formed on the memory gate electrode MG. In the case of this embodiment, The memory cell forming portion 32a of the first column, The memory cell forming portion 32b of the second column adjacent to the memory cell forming portion 32a of the first column is shared with the drain region WD formed in the well W, The memory cell 2a of the memory cell forming portion 32a of the first column can be accessed via the drain region WD (2b, 2c), The memory cell 2d (2e, with the memory cell forming portion 32b of the second column 2f) Apply the same bit voltage evenly. in this way, The memory cell forming portion 32b of the second column adjacent to the memory cell forming portion 32a of the first column shares the drain region WD between the memory cell forming portion 32a and the memory cell forming portion 32a of the first column. Therefore, the second side wall 12 of the memory gate electrode MG on which the drain side selection gate electrode DG is disposed is disposed to face the second side wall 12 of the memory gate electrode MG of the memory cell forming portion 32a of the first column. In addition to the above composition, Formed in the memory cell forming portion 32a, 32b, 32c, Each memory gate electrode MG extends from the selective gate formation region ER9 to the electrical cut region ER2 (ER4) and the physical cut region ER1 (ER5), And the electrode portion 35a is extended, 35b is formed in the isoelectric cut region ER2 (ER4) and the solid cut region ER1 (ER5). In the case of this embodiment, Extending the electrode portion 35a, 35b is formed into a denture type when viewed from above the semiconductor substrate, Memory cell forming portion 32a, 32b, 32c, The memory gate electrode MG extends linearly extending portion 36a, The linear end portion 36b formed at the laterally outer position of the extending portion 36a may be along the memory cell forming portion 32a, 32b, 32c, ... The direction of the arrangement is alternately arranged in sequence. also, The extension portion 36a and the end portion 36b are formed in the electrical cutoff region ER2. ER4, And formed in the solid cut region ER1 The connection portion (side wall non-formation portion) 36c of the ER 5 is connected. Here, Focusing on the memory cell forming portion 32b of the second column, For extending the electrode portion 35a, 35b is explained. The memory cell forming portion 32b of the second column is formed with the second side wall 12 of the memory gate electrode MG on which the drain side selective gate electrode DG is formed and the memory cell forming portion 32b in the adjacent first column. The second sidewall 12 of the memory gate electrode MG of the gate electrode of the pole side is extended by the electrode portion 35a, The side walls of the 35b are connected to each other. In the case of this embodiment, Extending the electrode portion 35a, 35b, Between the second side wall 12 of the memory gate electrode MG of the memory cell forming portion 32b of the second column and the second side wall 12 of the memory gate electrode MG of the memory cell forming portion 32a of the first column The side walls sequentially form four electrical cut-off portions 33a, 33b, 33c, 33d. Actually, Extending the electrode portion 35a, 35b is formed along the side wall of the extending portion 36a of the same plane as the second side wall 12 of the memory gate electrode MG of the memory cell forming portion 32b of the second row, and an electrical cut portion 33a is formed. An electrical cut-off portion 33d is formed along the side wall of the extending portion 36a of the same plane as the second side wall 12 of the memory gate electrode MG of the memory cell forming portion 32a of the first row. also, The electrode portion 35a is extended in the column direction between the memory cell forming portion 32a of the first row and the memory cell forming portion 32b of the second row. End 36b of 35b, An electrical cut-off portion 33c is formed along a side wall disposed on the memory cell forming portion 32a side of the first column, Further, another electrically cut portion 33b is formed along the side wall disposed on the memory cell forming portion 32b side of the second column. in this way, The extension from the second side wall 12 of the memory gate electrode MG of the memory cell forming portion 32b of the second column to the second side wall 12 of the memory gate electrode MG of the memory cell forming portion 32a of the first column Providing the electrode portion 35a, 35b, Four electrical cut-off portions 33a may be sequentially formed along the side wall, 33b, 33c, 33d. With this, Extending the electrode portion 35a, Side wall of 35b, Three or more opposite conductivity type semiconductor layers and intrinsic semiconductor layers are provided. In addition to the above composition, In the connecting portion 36c of the physical cutting area ER1, For example, the side wall of the extending portion 36a connected to the memory cell forming portion 32b of the second column, The inner peripheral wall of the end portion 36b between the second column memory cell forming portion 32b and the first column memory cell forming portion 32a is formed with a solid cutting portion 34c. also, In the connecting portion 36c of the physical cutting area ER1, For example, the side wall of the extending portion 36a connected to the memory cell forming portion 32a of the first column, And another inner peripheral wall connected to the side wall of the end portion 36b between the first column memory cell forming portion 32a and the second column memory cell forming portion 32b, Similarly, the solid cut portion 34b is formed. The entity cutting unit 34b, 34c has a conductive layer such as a semiconductor material that is not disposed along the inner peripheral wall of the connecting portion 36c. The inner peripheral wall of the connecting portion 36c is exposed to the outside. With this, Solid cutting portion 34b, 34c selects the gate electrode DG on the drain side of the memory cell forming portion 32a of the first column, A gap is formed between the drain gate selection gate electrode DG of the memory cell forming portion 32b of the second column to form a solid cut. Therefore, the gate electrode DG can be selected on the drain side of the memory cell forming portion 32a of the first column, The gate side selective gate electrode DG of the memory cell forming portion 32b of the second column is in a non-conduction state. in this way, Extending the electrode portion 35a, 35b, The side wall between the gate electrode DG and the drain side of the memory cell forming portion 32a of the first column is selected from the drain side of the memory cell forming portion 32b of the second column, and the gate electrode DG is selected. The electrical cut-off portion 33a may be arranged in sequence, Solid cutting portion 34c, Electrical cut-off portion 33b, 33c, The solid cutting portion 34b and the electrical cutting portion 33d. in this way, Extending the electrode portion 35a, 35b can be by the four electrical cut-offs 33a, 33b, 33c, 33d, With two solid cutting portions 34b, 34c, The gate electrode DG of the memory cell forming portion 32a of the first column is prevented from being selected, The drain side selective gate electrode DG of the memory cell forming portion 32b of the second column is turned on. also, Extending the electrode portion 35a, The 35b end portion 36b is from the solid cutting area ER1 The connecting portion 36c of the ER 5 faces the electrical cut-off region ER2 ER4 extension, And the end portion 36b is disposed adjacent to the memory cell forming portion 32a, The area between 32b, With this, It can prevent the electrical cut-off area ER2 ER4 is directed to the memory cell forming portion 32a, The length of 32b increases the amount of end portion 36b. Incidentally, The memory cell forming portion 32b of the second column, The memory cell forming portion 32c of the third column adjacent to the memory cell forming portion 32b of the second column is formed in the source region WS of the well W, The memory cell 2d of the memory cell forming portion 32b of the second column can be 2e, 2f, And the memory cell 2g of the memory cell forming portion 32c of the third column, 2h, 2i uniformly applies the same source voltage. in this way, The memory cell forming portion 32b of the second column adjacent to the memory cell forming portion 32c of the third column shares the source region WS between the memory cell forming portion 32c and the third cell. Therefore, the first side wall 11 of the memory gate electrode MG on which the source side selection gate electrode SG is disposed is disposed to face the first side wall 11 of the memory gate electrode MG of the memory cell forming portion 32c of the third column. in this way, The memory cell forming portion 32b of the second column forms a source electrode in the first sidewall 11 of the memory gate electrode MG forming the source-side selective gate electrode SG and the adjacent third column memory cell forming portion 32c. The first sidewall 11 of the memory gate electrode MG of the side selection gate electrode SG is provided with the electrode portion 35a extending, The side walls of the 35b are connected to each other. In the case of this embodiment, Extending the electrode portion 35a, 35b, Between the first side wall 11 of the memory gate electrode MG of the memory cell forming portion 32b of the second column and the first side wall 11 of the memory gate electrode MG of the memory cell forming portion 32c of the third column Side wall, Forming four electrical cut-off portions 33e in sequence, 33f, 33g, 33h. Actually, Extending the electrode portion 35a, 35b is formed with an electrical cut-off portion 33e along a side wall of the extending portion 36a formed on the same plane as the first side wall 11 of the memory gate electrode MG of the memory cell forming portion 32b of the second row, An electrical cut-off portion 33h is formed along the side wall of the extending portion 36a of the same plane as the first side wall 11 of the memory gate electrode MG of the memory cell forming portion 32c of the third row. also, The electrode portion 35a is extended in the column direction between the memory cell forming portion 32b of the second row and the memory cell forming portion 32c of the third row. End 36b of 35b, An electrical cut-off portion 33f is formed along a side wall disposed on the side of the memory cell forming portion 32b of the second column, Another electrical cut-off portion 33g is formed along the side wall disposed on the memory cell forming portion 32c side of the third column. in this way, The extension from the first side wall 11 of the memory gate electrode MG of the memory cell forming portion 32b of the second column to the first side wall 11 of the memory gate electrode MG of the memory cell forming portion 32c of the third column Providing the electrode portion 35a, 35b, Four electrical cut-off portions 33e may be sequentially formed along the sidewalls, 33f, 33g, 33h. In addition to the above composition, In the connecting portion 36c of the physical cutting area ER1, For example, the side wall of the extending portion 36a connected to the memory cell forming portion 32b of the second column, The inner peripheral wall of the end portion 36b between the second column memory cell forming portion 32b and the third column memory cell forming portion 32c is formed with a solid cutting portion 34e. also, In the connection portion 36c of the solid cutting area ER1, For example, the side wall of the extending portion 36a connected to the memory cell forming portion 32c of the third column, And another inner peripheral wall connected to the side wall of the end portion 36b between the third column memory cell forming portion 32c and the second column memory cell forming portion 32b, Similarly, the solid cut portion 34d is formed. The entity cutting unit 34e, 34d also has a conductive layer such as a semiconductor material that is not disposed along the inner peripheral wall of the connecting portion 36c. The inner peripheral wall of the connecting portion 36c is exposed to the outside. With this, Solid cutting portion 34e, 34d selects the gate electrode SG on the source side of the memory cell forming portion 32b of the second column, A gap is formed between the source side selective gate electrode SG of the memory cell forming portion 32c of the third column to form a solid cut. The source side of the memory cell forming portion 32b of the second column can be selected as the gate electrode SG, The source side selection gate electrode SG of the memory cell formation portion 32c of the third column is in a non-conduction state. in this way, Extending the electrode portion 35a, 35b, The side wall between the gate electrode SG and the source side selection gate electrode SG of the memory cell forming portion 32c of the third column is selected from the source side of the memory cell forming portion 32b of the second column, The electrical cutting portion 33e may be disposed in sequence, Solid cutting portion 34e, Electrical cut-off portion 33f, 33g, The solid cutting portion 34d and the electrical cutting portion 33h. in this way, Extending the electrode portion 35a, 35b can be by the four electrical cut-offs 33e, 33f, 33g, 33h, With two solid cutting portions 34e, 34d, Further, the source side selection gate electrode SG of the memory cell forming portion 32b of the second column is prevented, The source side selection gate electrode SG of the memory cell formation portion 32c of the third column is turned on. Incidentally, The non-volatile semiconductor memory device 31 is in the memory cell forming portion 32a, 32b, 32c, ...each of the memory gate electrodes MG, The memory gate electrode MG is extended to form an electrical cut-off region ER2 On the extension 36a in the ER4, And the electrical cut-off area ER2 A film CP is formed on each end portion 36b of the ER4, And during the manufacturing process, The memory gate electrode MG or the extension portion 36a can be prevented by the film CP, The upper surface of the end portion 36b is self-aligned. on the other hand, In the physical cut-off area ER1 In ER5, Since the film CP is not formed on the connecting portion 36c formed by the extension of the memory gate electrode MG, The connecting portion 36c is exposed to the outside. Therefore, the upper surface is self-aligned and mashed, A columnar memory gate contact MGC is provided via a vaporized layer (not shown) formed on the connecting portion 36c. In the above composition, In the non-volatile semiconductor memory device 31, Providing the electrode portion 35a along the extension, a side wall of 35b is provided to cut off the adjacent memory cell forming portion 32a, The drain side of 32b selects four electrical cut-off portions 33a of the gate electrodes DG, 33b, 33c, 33d, a portion where the gate electrode DG is cut off from each other by the gate electrode DG, Accordingly, it is possible to prevent the readout malfunction caused by the voltage fluctuation at the time of the data reading operation. also, In the non-volatile semiconductor memory device 31, Providing the electrode portion 35a along the extension, The other side wall of 35b is provided to cut off the adjacent memory cell forming portion 32b, The source side of 32c selects four electrical cut-off portions 33e of the gate electrodes SG, 33f, 33g, 33h, a portion where the source side selection gate electrodes SG are cut off from each other, as compared with the prior art, Accordingly, it is possible to prevent the readout malfunction caused by the voltage fluctuation at the time of the data reading operation. also, E.g, In the adjacent memory cell forming portion 32a, 32b, Providing the electrode portion 35a along the extension, An electrical cut-off portion 33a formed by the side wall of 35b, 33b, Or the electrical cut-off portion 33c, 33d, a solid-cut portion 34c in which a semiconductor material is not formed in a sidewall shape, 34b, And by two solid cutting portions 34c, 34b, The drain-side selection gate electrodes DG are not in contact with each other and are in a non-conductive state. in this way, In the memory cell forming portion 32a, 32b, Further, a cutting principle and an electrical cut-off portion 33a for cutting the drain-side selection gate electrodes DG from each other are additionally provided. 33b, 33c, 33d different physical cutting portion 34c, 34b, And only the electrical cut-off portion 33a, 33b, 33c, Compared with the situation of 33d, The drain-side selection gate electrodes DG can be more reliably cut off from each other. Furthermore, That is, it is convenient for the adjacent memory cell forming portion 32b, 32c, In the same manner, the cutting principle and the electrical cut-off portion 33e for cutting off the source-side selection gate electrodes SG are separately provided. 33f, 33g, 33h different physical cutting part 34e, 34d, And only the electrical cut-off portion 33e, 33f, 33g, Compared with the situation of 33h, The source side selection gate electrodes SG can be more reliably cut off from each other. Furthermore, The extended electrode portion 35a (35b) is folded back to the side of the electrical cut-off region ER2 (ER4) in the solid cut region ER1 (ER5). And adjacent to the memory cell forming portion 32a, End portion 36b is provided between 32b, By being disposed in the extension portion 36a and the end portion 36b of the electrical cut-off region ER2 (ER4), And a plurality of electrical cut-offs 23a, 23b, 23c, 23f, 23e, All 23d are arranged side by side in the electrically cut region ER2 (ER4). With this, In the non-volatile semiconductor memory device 31, By providing the end portion 36b, the electrical cut-off region ER2 (ER4) can be prevented from expanding toward the length of the memory cell forming portion 32a. Thereby achieving miniaturization, Highly integrated. Furthermore, In the non-volatile semiconductor memory device 31, Due to poor manufacturing, For example, the memory cell forming portion 32b adjacent to one side, When there is a foreign matter between the 32c along the side wall of the extending electrode portion 35a which is connected to the first side wall 11 of each of the memory gate electrodes MG, Adjacent memory cell forming portion 32b, The source side selection gate electrodes SG of 32c are electrically connected to each other. In this case, In the non-volatile semiconductor memory device 31, Due to the data readout action, Applying the same voltage to the source side selection gate electrode SG, Therefore, even the memory cell forming portion 32b, The source side selection gate electrodes SG of 32c are electrically connected to each other, It is also possible to prevent the voltage variation of the source side selection gate electrode SG due to a short circuit failure during the data reading operation, Or select the voltage variation of the gate electrode DG on the drain side. Furthermore, In the non-volatile semiconductor memory device 31, Due to poor manufacturing, For example, the memory cell forming portion 32a adjacent to the other party, When there is a foreign matter between the 32b along the side wall of the extending electrode portion 35a which is connected to the second side wall 12 of each of the memory gate electrodes MG, The adjacent memory cell forming portion 32a, The drain side selection gate electrodes DG of 32b are electrically connected to each other. In this case, In the non-volatile semiconductor memory device 31, Since the same kind of drain side selective gate electrodes DG which are highly likely to apply the same voltage during the data reading operation are electrically connected to each other, Therefore, it is possible to reduce the probability that the gate electrode DG generates a voltage variation on the drain side when the data is read. (4) The planar layout of the nonvolatile semiconductor memory device of the fourth embodiment In the third embodiment described above, Just in the physical cut-off area ER1 ER5 is connected to the memory cell forming portion 32a, 32b, 32c, The non-volatile semiconductor memory device 31 has been described. However, the present invention is not limited to this. It can be set as the following non-volatile semiconductor memory device 41, That is, as shown in FIG. 7 in which the parts corresponding to those in FIG. 4 are denoted by the same reference numerals, With the physical cut-off area ER1 The ER5 is provided with a connection area ER10 differently. ER11, And in the area ER10, The ER 11 is connected to the adjacent memory cell forming portion 42a, 42b. In this case, The memory cell forming portion 42a (42b) has a selective gate forming region ER9, The source-side selection gate structure 6a (6b) and the drain-side selection gate structure 5a (5b) are disposed opposite to each other via the memory gate structure 4a (4b). also, In each memory cell forming portion 42a, Each memory gate structure 4a of 42b, 4b, A linear memory gate electrode MG extending in the column direction is disposed in the selection gate formation region ER9, A film CP is formed on the memory gate electrode MG. In addition to the above composition, In the non-volatile semiconductor memory device 41, Adjacent to the selection gate formation region ER9, a connection region ER10 is provided, ER11, The solid cut region ER1 (ER5) is provided at the end of the connection region ER10 (ER11) via the electrical cut region ER2 (ER4). In this case, In the connection area ER10 (ER11), Electrical cut-off area ER2 (ER4) and physical cut-off area ER1 (ER5), Extending the memory gate electrode MG, Further, an extended electrode portion 45a (45b) formed by the memory gate electrode MG is provided. Incidentally, In the adjacent memory cell forming portion 42a, In 42b, The common is formed in the source region WS of the well W, And the memory cell 2d of a memory cell forming portion 42a may be from the source region WS, 2e, 2f, And the memory cell 2g of the other memory cell forming portion 42b, 2h, 2i uniformly applies the same source voltage. Adjacent memory cell forming portion 42a, 42b has the first side wall 11 of the memory gate electrode MG facing each other. Further, a configuration in which the gate electrode SG is selected along the source side of the side wall is provided along the first side wall 11. also, In addition to the above composition, Adjacent memory cell forming portion 42a, 42b in the connected area ER10, The ER 11 is provided by extending the electrode portion 45a, 45b is connected to the end of the memory gate electrode MG. Here, Extending the electrode portion 45a, 45b is formed into an E-shape from the top of the semiconductor. And starting from the center of the memory cell formation, The reflection object is set in the connection area ER10, ER11, Electrical cut-off area ER2 ER4 and physical cut-off area ER1 ER5. In this case, Extending the electrode portion 45a, 45b contains: Branch connecting portion 46a, It is set in the connected area ER10, ER11, And the memory cell forming portion 43a is connected, 42b memory gate electrodes MG each other; Extension 46b, 46f, It is disposed in the electrical cut-off area ER2 ER4, And extending from the branch connecting portion 46a along the length direction of the memory gate electrode MG; End 46d, It is disposed in the same electrical cut-off area ER2 ER4, And disposed on the extension portion 46b, 46f; And a sidewall non-forming portion 46c, 46g, 46e, It is disposed in the solid cutting area ER1 ER5, And respectively arranged in the extension portion 46b, 46f and the front end of the end 46d. Actually, Adjacent memory cell forming portion 42a, 42b by being in the connected area ER10, The first side wall 11 of the memory gate electrode MG of the memory cell forming portion 42a is connected to the side wall 47a of the branch connecting portion 46a of the ER 11 The first side wall 11 of the memory gate electrode MG of the other memory cell forming portion 42b. The branch connecting portion 46a is formed with a sidewall-shaped semiconductor layer 11a along the sidewall 47a. And the source side selection gate electrode SG of the memory cell forming portion 42a is connected to the semiconductor layer 11a, The gate electrode SG is selected from the source side of the other memory cell forming portion 42b. In the branch connecting portion 46a, At a specific position of the semiconductor layer 11a, A wide selection gate contact forming portion Ca is provided which is provided with the source side selection gate contact SGC. The selected gate contact forming portion Ca is formed with: Cross the upper part, It straddles the branch connecting portion 46a; And the plane, The surface thereof is formed in a planar shape along the semiconductor substrate; Further, a columnar source side selection gate contact SGC connected to the source side selection gate line (not shown) is provided on the plane portion. With this, Even if the narrow side and the inclined side wall-shaped source side selects the gate electrode SG, The specific voltage from the source side selection gate line SGL may be applied via the source side selection gate contact SGC and the selection gate contact forming portion Ca. Furthermore, In the case of this embodiment, Selecting the gate contact forming portion Ca to arrange the planar portion in the selective gate contact region ER6, ER7, The upper portion is disposed in the connected area ER10, ER11. Incidentally, In the above embodiment, The case where the selected gate contact forming portion Ca is provided in the semiconductor layer 11a of the branch connecting portion 46a has been described. However, the present invention is not limited to this. The selection gate contact forming portion Ca may be disposed in the selection gate contact region ER6, The gate electrode SG is selected on the source side of the ER7. Here, In the branch connecting portion 46a, The U-shaped side wall 47b opposite to the side wall 47a on which the selective gate contact forming portion Ca is provided, 47c, A semiconductor layer 11b having a sidewall shape is also formed, respectively. Furthermore, The semiconductor layer 11b is formed to form the memory cell forming portion 42a, When the gate side of the 42b source selects the gate electrode SG or the drain side selects the gate electrode DG, the U-shaped sidewall 47b remaining in the branch connecting portion 46a, 47c. also, In addition to the above composition, In the memory cell forming portion 42a, 42b, Opposite the first side wall 11 of the memory gate electrode MG, Further, a sidewall-shaped drain-side selective gate electrode DG is formed along the second sidewall 12 on the drain region WD side of the well W. Furthermore, E.g, The memory cell forming portion 42a shares a memory cell forming portion and a drain region WD which are not shown in the drawing. Further, the same bit voltage as the memory cell 2d of the memory cell forming portion 42a may be applied to a memory cell of the adjacent memory cell forming portion (not shown). In the extension portion 46b provided in the electrical cut-off region ER2 (ER4), 46f and end 46d, The source side selection gate electrode SG and the drain side selection gate electrode DG are not formed on the sidewall side, And six electrical cut-off portions 43a are formed along the side wall, 43b, 43c, 43f, 43e, 43d. Here, The electrical cut-off portion 43a, 43b, 43c, 43f, 43e, 43d all have the same composition, a sidewall-shaped intrinsic semiconductor layer Ia made of i-type, Ib, Forming a conductive semiconductor layer OC opposite to the sidewall shape, And having the intrinsic semiconductor layer Ia, A structure of the opposite conductivity type semiconductor layer OC is formed between Ib. Furthermore, The opposite-conductivity-type semiconductor layer OC is formed by a conductivity type (p-type in this case) different from the source-side selection gate electrode SG and the drain-side selection gate electrode DG. Extending the extension portion 46b of the electrode portion 45a (45b), An electrical cut-off portion 43a is formed along a sidewall of the same plane that is connected to the second sidewall 12 of the memory gate electrode MG of the memory cell forming portion 42a. And forming another electrically cut portion 43b along the other side wall disposed opposite to the one side wall. In a memory cell forming portion 42a, For example, the gate electrode DG can be selected from the n-type drain side by the electrical cut-off portion 43a. The second side wall 12 of the memory gate electrode MG forms a pin junction along the side walls of the branch connecting portion 46a and the extending portion 46b. also, The extension portion 46f of the electrode portion 45a (45b) is extended, An electrical cut-off portion 43f is formed along a sidewall of the same plane that is connected to the second sidewall 12 of the memory gate electrode MG of the memory cell forming portion 42b. And forming another electrical cut-off portion 43e along the other side wall disposed opposite to the one side wall. In the other memory cell forming portion 42b, For example, the gate electrode DG can be selected from the n-type drain side by the electrical cut-off portion 43f. The second side wall 12 of the memory gate electrode MG forms a pin junction along the side walls of the branch connecting portion 46a and the extending portion 46f. Furthermore, Extending the end portion 46d of the electrode portion 45a (45b) along the extending portion 46b, The length direction of 46f extends linearly from the branch connecting portion 46a. And disposed on the extension portion 46b, 46f. At the end 46d, An electrical cut-off portion 43c is formed on a sidewall opposite to an extending portion 46b. Another electrical cut-off portion 43d is formed on the side wall opposite to the other extending portion 46f. With this, Extending the electrode portion 45a (45b), The gate electrode DG is selected from the drain side formed on the second side wall 12 of the memory gate electrode MG along the memory cell forming portion 42a, and the memory gate electrode MG is formed along the other memory cell forming portion 42b. a sidewall between the drain side of the second sidewall 12 and the gate electrode DG. Six electrical cut-off portions 43a may be formed in sequence, 43b, 43c, 43d, 43e, 43f. With this, Extending the electrode portion 45a, The side wall of 45b is provided with three or more opposite conductive semiconductor layers and intrinsic semiconductor layers. With this, For example, even if foreign matter adheres to the electrical cut-off portion 43a of the extension portion 46b, 43b, Or a side wall non-forming portion 46c of the extending portion 46b, which will be described later, It is assumed that the gate electrode DG is selected from the drain side of the memory cell forming portion 42a via the electrical cut portion 43a, 43b, Side wall non-forming portion 46c, The semiconductor layer 11b of the side wall 47b and the electrically cut portion 43c of the end portion 46d are electrically turned on due to foreign matter. By the electrical cutting portion 43c, A pin junction may also be formed along the sidewall of the end portion 16b. In addition to the above composition, Each side wall non-formation portion 46c of the solid cut region ER1, 46e, 46g is formed on the side wall forming solid cutting portion 44a, 44b, 44c. The entity cutting unit 44a, 44b, 44c has no non-formed portion 46c along the side wall, 46e, A conductive layer such as a semiconductor material is disposed on the sidewall of the 46 g, And the sidewall non-formation portion 46c, 46e, The side wall of 46g is exposed to the outside. With this, Solid cutting portion 44a, 44b, 44c selects the gate electrode DG on the drain side of a memory cell forming portion 42a, A gap is formed between the drain gate selection gate electrode DG of the other memory cell forming portion 42b to form a solid cut. Thereby, the gate electrode DG of the drain side can be made non-conductive to each other. in this way, Extending the electrode portion 45a (45b), The gate electrode DG is formed on the drain side formed from the second side wall 12 of the memory gate electrode MG of the memory cell forming portion 42a, and the memory gate electrode MG is formed along the other memory cell forming portion 42b. The sidewall formed between the drain side of the second sidewall 12 and the gate electrode DG is selected. The electrical cutting portion 43a can be arranged in sequence, Solid cutting portion 44a, Electrical cut-off portion 43b, 43c, Solid cutting portion 44b, Electrical cut-off portion 43d, 43e, The solid cutting portion 44c and the electrical cutting portion 43f. in this way, The extending electrode portion 45a (45b) can be separated by the six electrical cutting portions 43a, 43b, 43c, 43d, 43e, 43f, With three solid cutting portions 44a, 44b, 44c prevents the gate electrode DG from being turned on in the drain side. In the above composition, In the non-volatile semiconductor memory device 41, A drain-side selective gate electrode DG capable of cutting a memory cell forming portion 42a is provided along a sidewall of the extending electrode portion 45a (45b), The six electrical cut-off portions 43a of the gate electrode DG are selected from the drain side of the other memory cell forming portion 42b, 43b, 43c, 43d, 43e, 43f, The portion of the gate electrode DG that cuts off the drain side is increased from the previous portion. With this, Correspondingly, the readout malfunction caused by the voltage fluctuation during the data reading operation can be prevented. also, In the extension electrode portion 45a (45b), The electrical cut-off portion 43a formed along the sidewall, 43b, Or the electrical cut-off portion 43c, 43d, Electrical cut-off portion 43e, 43f, a solid-cut portion 44a in which a semiconductor material is not formed in a sidewall shape, 44b, 44c, By three solid cutting portions 44a, 44b, 44c, The drain-side selection gate electrodes DG can be made non-conductive with each other without being in contact with each other. in this way, In the adjacent memory cell forming portion 42a, In 42b, Further, a cutting principle and an electrical cut-off portion 43a for cutting the drain-side selection gate electrodes DG from each other are additionally provided. 43b, 43c, 43d, 43e, 43f different physical cutting portion 44a, 44b, 44c, And only the electrical cut-off portion 43a is provided, 43b, 43c, 43d, 43e, Compared with the case of 43f, The drain-side selection gate electrodes DG can be more reliably cut off from each other. also, That is, the memory cell forming portion 42a that is so adjacent is facilitated, In 42b, The extension electrode portion 45a (45b) is also folded back in the solid cutting region ER1 (ER5). And providing an end portion 46d and an extension portion 46b in the electrical cut-off region ER2 (ER4), 46f, With the end portion 46d and the extension portion 46b, 46f causes a plurality of electrical cut-off portions 43a, 43b, 43c, 43d, 43e, All 43f are arranged in the electrical cut-off area ER2 (ER4). With this, In the non-volatile semiconductor memory device 41, The electrical cut-off region ER2 (ER4) can be prevented from being directed to the memory cell forming portion 42a, The length direction of 42b is increased, and the end portion 46d is not arranged in series in the extending portion 46b. The amount of 46f. Furthermore, In the non-volatile semiconductor memory device 41, That is, it is convenient for, for example, the adjacent memory cell forming portion 42a due to manufacturing defects, When there is a foreign matter between the 42b along the side wall of the extending electrode portion 45a which is connected to the second side wall 12 of the memory gate electrode MG, The adjacent memory cell forming portion 42a, The drain side selection gate electrodes DG of 42b are electrically connected to each other. In this case, In the non-volatile semiconductor memory device 41, Since the same kind of drain side selective gate electrodes DG which are highly likely to apply the same voltage when the data reading operation is performed are electrically connected to each other, Therefore, it is possible to reduce the probability that the gate electrode DG generates a voltage variation on the drain side when the data is read. Furthermore, In the third embodiment described above, Selecting the gate electrode DG for the drain side of the memory cell forming portion 42a, An electrical cut-off portion 43a electrically connected to the drain-side selective gate electrode DG of the other memory cell forming portion 42b, 43b, 43c, 43d, 43e, 43f, As a first selection gate electrode for cutting a memory cell formation portion, The case of the electrical cut-off portion electrically connected to the first selection gate electrode or the second selection gate electrode of the other memory cell formation portion is described. However, the present invention is not limited to this. It is also possible to apply a source-side selection gate electrode that cuts off a memory cell formation portion, An electrical cut-off portion electrically connected to the source side selective gate electrode of the other memory cell forming portion. In this case, In a memory cell formation and another memory cell formation, The configuration of the drain side selection gate electrode DG and the source side selection gate electrode SG shown in FIG. 7 is replaced. also, As another embodiment, It is also possible to apply a gate electrode for cutting off the drain side of a memory cell formation portion, An electrical cut-off portion electrically connected to the source side selective gate electrode of the other memory cell forming portion. In this case, The memory cell forming portion and the other memory cell forming portion have the following configuration. which is, Do not share the source area WS, On the other hand, the drain side selection gate electrode DG of the other memory cell forming portion 42b shown in FIG. 7 is switched to the source side selection gate electrode SG. (5) Other embodiments, The present invention is not limited to the embodiment. Various modifications can be implemented within the scope of the gist of the invention. For example, various voltage values can be applied to the voltage values of the respective parts. also, In the first and second embodiments described above, As the first selection gate electrode formed on the first sidewall of the memory gate electrode, The case where the source side selects the gate electrode SG is described. However, the present invention is not limited to this. Alternatively, the drain side selective gate electrode may be formed as a first selection gate electrode on the first side wall of the memory gate electrode. Furthermore, In this case, The second selection gate electrode formed on the second sidewall of the memory gate electrode serves as a source side selection gate electrode. also, In the above embodiment, An electric cut-off portion 13a that forms a pin junction is provided with the drain-side selection gate electrode DG or the source-side selection gate electrode SG as a starting point. 13b, 13d, 13c (13e, 13f, 13h, 13g), 23a, 23b, 23c, 23f, 23e, 23d, 33a, 33b, 33c, 33d, 43a, 43b, 43c, 43d, 43e, The situation of 43f is described. However, the present invention is not limited to this. Alternatively, the gate electrode DG or the source side selection gate electrode SG may be selected as the starting point on the drain side. Or the electrical cutting portion is separately provided to form a nin junction structure, Pip junction construction, Npn junction construction, Or an electrical cut-off portion of the pnp junction structure. which is, Extending the side wall of the electrode portion from the extension of the memory gate electrode, It is possible to provide three or more opposite conductivity type semiconductor layers different in conductivity type from the first selection gate electrode and the second selection gate electrode, Or any of the intrinsic semiconductor layers. at this time, It is desirable to adjoin the opposite conductive semiconductor layers to each other, Or adjacent intrinsic semiconductor layers between each other, A solid cut portion that does not form a semiconductor layer on the side wall of the electrode portion extending is formed. Furthermore, Above the first 2nd, In the third and fourth embodiments, Set to set the physical cut-off area ER1 The composition of ER5, However, the present invention is not limited to this. It is also possible not to set the physical cut-off area ER1. ER5, Only the electrical cut-off area ER2 is set. ER4. Furthermore, In the above embodiment, The semiconductor substrate is viewed from above and is provided with a U-shape, Or E-shaped, The tooth portion is extended to provide the electrode portion 15a, 15b, 15c, 15d, 25a, 25b, 35a, 35b, 45a, The situation of 45b is described. However, the present invention is not limited to this. For example, it can be applied by F-shaped, Or H-shaped, J-shaped, K-shaped, L-shaped, M-shaped, N-shaped, T-shaped, U-shaped, V shape, W type, Y-shaped, An extended electrode portion formed by various other shapes such as a zigzag shape. Furthermore, In the above embodiment, A memory gate structure 4a for forming an N-type transistor structure is provided using a P-type well W, Forming a drain-side selective gate structure 5a of an N-type MOS transistor structure, The case where the source side selective gate structure 6a of the N-type MOS transistor structure is also formed is described. However, the present invention is not limited to this. A memory gate structure that forms a P-type transistor structure can be provided using an N-type well, Forming a drain-side selective gate structure of a P-type MOS transistor structure, And a source side selective gate structure which also forms a P-type MOS transistor structure. In this case, The memory cell 2a described in the above embodiment has the opposite polarity of the N type and the P type. Therefore, it is applied to the memory gate structure, Selecting the gate structure on the drain side, The source side selects the gate structure, Bit line, The voltages of the source lines and the like also vary depending on this. Furthermore, In the above embodiment, The data is written, for example, by injecting a charge into the charge accumulation layer EC of the memory cell 2a. The case where the data is deleted by extracting the charge of the charge storage layer EC is described. However, the present invention is not limited to this. Contrary to this, Writing data by extracting the charge in the charge accumulation layer EC of the memory cell 2a, The data is deleted by injecting a charge into the charge accumulation layer EC. Furthermore, In the above embodiment, As a film formed on the top portion of the memory gate electrode MG, The film CP constructed by lamination is described. which is, The upper coating film CPb is formed by laminating an insulating material such as SiN different from the lower coating film CPa on the lower coating film CPa. However, the present invention is not limited to this. Can also be a single layer of film, Or a film made of a laminate of three or more layers. also, The following situation is described, which is, In the first embodiment described above, Extending the electrode portion 15a, 15b, 15c, 15d is provided with four electrical cut-off portions 13a, 13b, 13d, 13c (13e, 13f, 13h, 13g), In the second embodiment described above, Extending the electrode portion 25a, 25b is provided with six electrical cut-off portions 23a, 23b, 23c, 23f, 23e, 23d, In the third embodiment described above, Extending the electrode portion 35a, 35b is provided with four electrical cut-off portions 33a, 33b, 33c, 33d, In the fourth embodiment described above, Extending the electrode portion 45a, 45b is provided with six electrical cut-off portions 43a, 43b, 43c, 43d, 43e, 43f, However, the present invention is not limited to this. It is sufficient to provide three or more electrical cut-off portions at each position of the extended electrode portion. also, The electrode portions may be extended on both sides of the memory gate electrode to make the number or shape of the electrical cut portions different. An electrical cut-off portion is formed asymmetrically around the memory gate electrode. (6) Regarding the positional relationship between the electrical cut-off area and the solid cut-off area, In the first to third embodiments described above, The case where the electrical cutoff region ER2 (ER4) and the physical cutoff region ER1 (ER5) are sequentially disposed on both sides of the selective gate formation region ER9 centering on the selected gate formation region ER9 is described. However, the present invention is not limited to this. The arrangement positions of the electrical cut-off area ER2 (ER4) and the physical cut-off area ER1 (ER5) may be reversely provided. On both sides of the selection gate forming region ER9, The solid cut region ER1 (ER5) and the electrical cut region ER2 (ER4) are sequentially disposed. E.g, The parts corresponding to those in FIG. 5 are denoted by the same reference numerals, and FIG. 8 shows that the electrical cut-off area ER2 (ER4) and the physical cut-off area ER1 (ER5) of the memory cell forming portion 22a shown in FIG. 5 are arranged oppositely. The planar layout of the memory cell forming portion 52. In this case, The memory cell forming portion 52 is provided with a solid cut region ER11 at one end of the selected gate forming region ER9. Another physical cut-off area ER15 is disposed at the other end of the selection gate forming region ER9. An electrical cut-off region ER12 (ER14) is disposed at the end of the solid cut region ER11 (ER15). The memory cell forming portion 52 is provided with a strip-shaped memory gate electrode MG extending in the selective gate forming region ER9. In the solid cutting area ER11 (ER15) and the electrical cutting area ER12 (ER14), An extension electrode portion 55a (55b) formed by directly extending the memory gate electrode MG from the selection gate formation region ER9 is provided. In the case of this embodiment, The extending electrode portion 55a (55b) is formed into a three-fork shape when viewed from above the semiconductor substrate. The connecting portion 56d formed in the solid cutting region ER11 (ER15), And an extension portion 56a and an end portion 56b formed in the electrical cut-off region ER12 (ER14), 56c constitutes. In this case, The connecting portion 56d is formed by the solid cutting region ER11 (ER15) from the root portion 57a of the end of the memory gate electrode MG of the selected gate forming region ER9, It is constituted by a branch portion 57b branched from the root portion 57a into a trifurcation, An extension portion 56a is formed in a central branch portion of the branch portion 57b. An end portion 56b is formed at a branch portion of the branch portion 57b at both ends, 56c. In the connecting portion 56d which is a side wall non-forming portion of the solid cutting region ER1, Forming a solid cut portion 54a on the outer peripheral wall of the first side wall 11 and the one end portion 56b of the memory gate electrode MG, In the side wall of the one end portion 56b, Forming a solid cut portion 54b with a peripheral wall of the side wall of the extending portion 56a, Forming a solid cutting portion 54c on the outer peripheral wall of the other side wall of the connecting portion 56a and the side wall of the other end portion 56c, The plurality of solid cut portions 54a are collectively formed on the side wall of the other end portion 56c and the second side wall 12 of the memory gate electrode MG. 54b, 54c, 54d. The entity cutting unit 54a, 54b, 54c, 54d has a conductive layer such as a semiconductor material that is not disposed along the outer peripheral wall of the connecting portion 56d. The outer peripheral wall of the connecting portion 56d is exposed to the outside. With this, Solid cutting portion 54a, 54b, 54c, 54d selects the gate electrode SG on the source side formed along the first sidewall 11 of the memory gate electrode MG, Forming a gap between the drain-side selective gate electrode DG formed along the second sidewall 12 of the memory gate electrode MG to form a solid cut. The source side selection gate electrode SG and the drain side selection gate electrode DG can be in a non-conduction state. Furthermore, The connecting portion 56d of the solid cutting region ER11 (ER15) is extended to the electrode portion 55a (55b), No film CP is formed, The memory gate contact MGC is set at a specific position. In the electrical cut-off area ER12 (ER14), An extension portion 56a disposed on an extension line of the memory gate electrode MG of the selection gate formation region ER9 forms an electrical cut-off portion 53c opposite to the sidewall thereof, 53d, An electrical cut-off portion 53a is formed on the opposite side wall of the end portion 56b formed at one of the laterally outer positions of the extending portion 56a, 53b, An electrical cut-off portion 53e is formed on the side wall opposite to the end portion 56c formed at the other laterally outer position of the extending portion 56a. 53f, A total of six electrical cut-off portions 53a are formed, 53b, 53c, 53d, 53e, 53f. Furthermore, The extension portion 56a and the end portion 56b of the electrically-cut region ER12 (ER14) extending over the electrode portion 55a (55b), 56c, A film CP is formed in the same manner as the memory gate electrode MG that selects the gate formation region ER9. Here, The electrical cut-off portion 53a, 53b, 53c, 53d, 53e, 53f all have the same composition, a sidewall-shaped intrinsic semiconductor layer Ia made of i-type, Ib, Forming a conductive semiconductor layer OC opposite to the sidewall shape, And having the intrinsic semiconductor layer Ia, A structure of the opposite conductivity type semiconductor layer OC is formed between Ib. Furthermore, The opposite-conductivity-type semiconductor layer OC is formed by a conductivity type (p-type in this case) different from the source-side selection gate electrode SG and the drain-side selection gate electrode DG. With this, For example, even if foreign matter adheres to the connecting portion 56d, the source side selects the gate electrode SG, The electrically cut portion 53a of the end portion 56b is turned on. The electrical cut-off portion 53a may form a pin junction from the first side wall 11 of the memory gate electrode MG along the side wall of the end portion 56b with the n-type source side selection gate electrode SG as a starting point. Thereby, the current of the source side selection gate electrode SG can be blocked by the electrical cut-off region ER2 (ER4). Furthermore, For example, in addition to the connecting portion 56d, Even if the foreign matter adheres to one of the electrical cut-off portions 53a of the end portion 56b, the foreign matter is switched from the source-side selective gate electrode SG to the other electrically-cut portion 53b of the end portion 56b. The other side of the end portion 56b may be used to form a pin from the first side wall 11 of the memory gate electrode MG along the side wall of the end portion 56b by using the n-type source side selection gate electrode SG as the starting point from the other electrically-cut portion 53b of the end portion 56b. Junction, Thereby, the current of the source side selection gate electrode SG can be blocked by the electrical cut-off region ER2 (ER4). Even such a memory cell forming portion 52, Also similar to the above embodiment, Six electrical cut-off portions 53a capable of cutting the source side selective gate electrode SG and the drain side selective gate electrode DG are provided along the side wall of the extending electrode portion 55a (55b), 53b, 53c, 53d, 53e, 53f, The portion where the source side selection gate electrode SG and the drain side selection gate electrode DG are cut is increased as compared with the previous one. Therefore, it is possible to prevent the readout malfunction caused by the voltage fluctuation at the time of the data reading operation. Incidentally, In the memory cell forming portion 52 shown in FIG. 8, In the manufacturing process, Since the memory gate contact MGC is formed in the connection portion 56d of the solid cut region ER1 provided between the selection gate formation region ER9 and the electrical cut region ER12 (ER14), Therefore, with respect to the selection of the gate formation region ER9 and the electrical cutoff region ER12 (ER14), It is necessary to ensure a sufficient alignment margin of the memory gate contact MGC. In contrast, In the memory cell forming portion 22a of the second embodiment shown in FIG. 5, It is only necessary to ensure a sufficient alignment margin of the memory gate contact MGC with respect to the electrical cut-off region ER2 (ER4). Therefore, the width of the solid cut region ER1 (ER5) can be narrowed correspondingly to the memory cell forming portion 52 shown in FIG. Therefore, the memory cell forming portion 52 shown in Fig. 8 can be formed in a small size. Furthermore, Here, the electrode portion 55a is provided with an extension provided with a branch of a trifurcation, The memory cell forming portion 52 of 55b is explained. However, the present invention is not limited to this. An electrode portion may be provided for the branch to be a bifurcated extension, Or branching the electrode portion with an extension of four or more, also, The shape of the branch can be various shapes such as an F-shape or a Y-shape. Even if this extension is provided with the electrode portion, A plurality of electrical cutting portions may also be formed in the branch portion. Therefore, it may be the same as the above embodiment. The portion where the source side selection gate electrode SG and the drain side selection gate electrode DG are cut is increased as compared with the prior art. also, Even in the nonvolatile semiconductor memory device 41 of the fourth embodiment shown in FIG. 7, Conversely, the arrangement positions of the electrical cut-off area ER2 (ER4) and the physical cut-off area ER1 (ER5) may be set. And in the area ER10, On both sides of the ER11, The solid cut region ER1 (ER5) and the electrical cut region ER2 (ER4) are sequentially disposed. In this case, a sidewall non-formation portion 46c is provided at an end of the branch connecting portion 46a, 46e, 46g, and then, An extension portion 46b may be disposed at a front end of the sidewall non-formed portion 46c, An end portion 46d is provided at a front end of the sidewall non-formed portion 46e, An extension portion 46f is provided at a front end of the side wall non-formed portion 46g. Even for the composition as described above, It can also be the same as the above embodiment. The electrical cut-off portion 43a, 43b, 43c, 43d, 43e, The number of 43f increases, Accordingly, the portion where the source side selection gate electrode SG and the drain side selection gate electrode DG are cut is increased as compared with the previous one.

1‧‧‧Non-volatile semiconductor memory device
2a~2j‧‧‧ memory cells
3a～3d‧‧‧ memory cell formation
4a～4c‧‧‧ memory gate structure
5a～5c‧‧‧汲polar selection gate structure
6a～6c‧‧‧Source side selection gate structure
11‧‧‧1st side wall
11a‧‧‧Semiconductor layer
11b‧‧‧Semiconductor layer
12‧‧‧ second side wall
13a～13h‧‧‧Electrical cut-off
14a～14d‧‧‧ entity cut-off
15a～15d‧‧‧Extended electrode part
16a‧‧‧Extension
16b‧‧‧End
16c‧‧‧Connected Department
21‧‧‧Non-volatile semiconductor memory devices
22a～22c‧‧‧ memory cell formation
23a～23f‧‧‧Electrical cut-off
24a～24c‧‧‧ entity cut-off
25a‧‧‧Extended electrode section
25b‧‧‧Extended electrode section
26a‧‧‧Extension
26b‧‧‧End
26c‧‧‧End
26d‧‧‧Connected Department
28a‧‧‧Side spacers
28b‧‧‧ sidewall spacers
30‧‧‧The gate side selects the gate insulating film
31‧‧‧Non-volatile semiconductor memory devices
32a～32c‧‧‧ memory cell formation
33‧‧‧Source side selection gate insulating film
33a～33h‧‧‧Electrical cut-off
34b‧‧‧ entity cut-off
34c‧‧‧ entity cut-off
34d‧‧‧ entity cut-off
34e‧‧‧ entity cut-off
35a‧‧‧Extended electrode section
35b‧‧‧Extended electrode section
36a‧‧‧Extension
36b‧‧‧End
36c‧‧‧Connected Department
41‧‧‧Non-volatile semiconductor memory device
42a‧‧‧ Memory Cell Formation
42b‧‧‧ Memory Cell Formation
43a～43f‧‧‧Electrical cut-off area
44a～44c‧‧‧ entity cut-off
45a‧‧‧Extended electrode section
45b‧‧‧Extended electrode section
46a‧‧‧ Branch Office
46b‧‧‧Extension
46c‧‧‧ sidewall non-formation
46d‧‧‧End
46e‧‧‧ sidewall non-formation
46f‧‧‧Extension
46g‧‧‧ sidewall non-formation
47a～47c‧‧‧ Sidewall
52‧‧‧ Memory Cell Formation
53a～53f‧‧‧Electrical cut-off
54a～54d‧‧‧ entity cut-off
55a‧‧‧Extended electrode section
55b‧‧‧Extended electrode section
56a‧‧‧Extension
56b‧‧‧End
56c‧‧‧End
56d‧‧‧Connected Department
57a‧‧‧Foundation 5
57b‧‧‧ Branch
100‧‧‧Non-volatile semiconductor memory device
101a～101d‧‧‧ memory cell formation
102a～102h‧‧‧ memory cells
103a‧‧‧Electrical cut-off
103b‧‧‧Electrical cut-off
104‧‧‧Solid cut-off
111‧‧‧ side wall
112‧‧‧ side wall
113‧‧‧End wall
A-A'‧‧‧ Section
Back‧‧‧Substrate voltage line
BC‧‧‧ bit joint
BL1‧‧‧ bit line
BL2‧‧‧ bit line
Bo‧‧‧lower gate insulating film
Ca‧‧‧Selected gate contact forming section
Cb‧‧‧Selecting the gate contact forming part
CP‧‧‧ film
CPa‧‧‧ lower film
CPb‧‧‧ upper film
DG‧‧‧汲-side selection gate electrode
DGC‧‧‧bend side selection gate contacts
DGL1～DGL4‧‧‧汲polar selection gate line
EC‧‧‧charge accumulation layer
ER1‧‧‧ physically cut area
ER2‧‧‧Electrical cut-off area
ER3‧‧‧ memory cell area
ER4‧‧‧Electrical cut-off area
ER5‧‧‧ physically cut area
ER6‧‧‧Select gate contact area
ER7‧‧‧Select gate contact area
ER9‧‧‧Select gate formation area
ER10‧‧‧Connected area
ER11‧‧‧ connected area
ER11‧‧‧ physically cut area
ER12‧‧‧Electrical cut-off area
ER14‧‧‧Electrical cut-off area
ER15‧‧‧ physically cut area
Ia‧‧‧Intrinsic semiconductor layer
Ib‧‧‧ intrinsic semiconductor layer
MG‧‧‧ memory gate electrode
MGC‧‧‧ memory gate contacts
MGL‧‧‧ memory gate line
MGL1～MGL4‧‧‧ memory gate line
OC‧‧‧ opposite conductive semiconductor layer
S‧‧‧ Telluride layer
S1‧‧‧ Telluride layer
S2‧‧‧ Telluride layer
SC‧‧‧Source contact
SG‧‧‧Source side select gate electrode
SGC‧‧‧Source side select gate contact
SGL‧‧‧Source side selection gate line
SL‧‧‧ source line
SW‧‧‧ side wall
Tp‧‧‧Upper Gate Insulation Film
W‧‧‧ Well
W1‧‧‧ memory configuration area
W2‧‧‧ memory configuration area
W3‧‧‧ memory configuration area
WD‧‧‧Bungee Area
WDa‧‧‧ low concentration bungee area
WS‧‧‧ source area
WSa‧‧‧Low concentration source area

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a cross-sectional structure of a memory cell provided in a nonvolatile semiconductor memory device of the present invention. Fig. 2 is a schematic view showing a circuit configuration of a nonvolatile semiconductor memory device of the present invention. Figure 3 is a table summarizing the voltage values of various operations of the non-volatile semiconductor memory device. Fig. 4 is a schematic view showing a plan layout of a nonvolatile semiconductor memory device according to the first embodiment. Fig. 5 is a schematic view showing a plan layout of a nonvolatile semiconductor memory device according to a second embodiment; Fig. 6 is a schematic view showing a plan layout of a nonvolatile semiconductor memory device according to a third embodiment; Fig. 7 is a schematic view showing a plan layout of a nonvolatile semiconductor memory device according to a fourth embodiment; Fig. 8 is a schematic view showing a plan layout of a nonvolatile semiconductor memory device according to another embodiment. Fig. 9 is a schematic view showing the circuit configuration of a conventional nonvolatile semiconductor memory device. Fig. 10 is a schematic view showing the planar layout of the previous memory cell forming portion.

1‧‧‧Non-volatile semiconductor memory device

2a~2i‧‧‧ memory cells

3a~3c‧‧‧ memory cell formation

4a‧‧‧Memory gate structure

5a‧‧‧汲polar selection gate structure

6a‧‧‧Source side selection gate structure

11‧‧‧1st side wall

12‧‧‧ second side wall

13a~13h‧‧‧Electrical cut-off

14a~14d‧‧‧ entity cut-off

15a~15d‧‧‧Extended electrode section

16a‧‧‧Extension

16b‧‧‧End

16c‧‧‧Connected Department

A-A'‧‧‧ Section

BC‧‧‧ bit joint

Ca‧‧‧Selected gate contact forming section

Cb‧‧‧Selecting the gate contact forming part

CP‧‧‧ film

CPb‧‧‧ upper film

DG‧‧‧汲-side selection gate electrode

DGC‧‧‧bend side selection gate contacts

ER1‧‧‧ physically cut area

ER2‧‧‧Electrical cut-off area

ER3‧‧‧ memory cell area

ER4‧‧‧Electrical cut-off area

ER5‧‧‧ physically cut area

ER6‧‧‧Select gate contact area

ER7‧‧‧Select gate contact area

ER9‧‧‧Select gate formation area

Ia‧‧‧Intrinsic semiconductor layer

Ib‧‧‧ intrinsic semiconductor layer

MG‧‧‧ memory gate electrode

MGC‧‧‧ memory gate contacts

OC‧‧‧ opposite conductive semiconductor layer

SC‧‧‧Source contact

SG‧‧‧Source side select gate electrode

SGC‧‧‧Source side select gate contact

W‧‧‧ Well

W1‧‧‧ memory configuration area

W2‧‧‧ memory configuration area

W3‧‧‧ memory configuration area

WD‧‧‧Bungee Area

WS‧‧‧ source area

Claims (5)

A non-volatile semiconductor memory device characterized in that a plurality of memory cell formation portions are provided, and the memory cell formation portion includes: a first selection gate structure body having a first selection on a well of a semiconductor substrate a gate insulating film including a first selection gate electrode; and a second selection gate structure including a second selection gate electrode via the second selection gate insulating film on the well; a memory gate structure; The gate spacer is provided between the first selection gate structure and the second selection gate structure, and the lower gate insulating film, the charge storage layer, the upper gate insulating film, and the memory are provided. a gate electrode is laminated on the well; and an electrode portion is extended, and the memory gate is disposed in a selected gate formation region of the first selection gate structure and the second selection gate structure a pole electrode extending; and a side wall of the extending electrode portion is provided with three or more opposite conductivity type semiconductor layers different from the first selection gate electrode and the second selection gate electrode Or any of the intrinsic semiconductor layers. A non-volatile semiconductor memory device characterized in that a plurality of memory cell formation portions are provided, and the memory cell formation portion includes: a first selection gate structure body having a first selection on a well of a semiconductor substrate a gate insulating film including a first selection gate electrode; and a second selection gate structure including a second selection gate electrode via the second selection gate insulating film on the well; and a memory gate structure Provided between the first selective gate structure and the second selective gate structure via a sidewall spacer, and the lower gate insulating film, the charge storage layer, the upper gate insulating film, and the memory The body gate electrode is sequentially stacked on the well; and the memory cell forming portion and the other memory cell forming portion are connected by extending the electrode portion, and the extending electrode portion is disposed from the opposite direction The memory gate electrode of the selected gate formation region of the first selection gate structure and the second selection gate structure is extended, and is provided on the sidewall of the extension electrode portion. The above conductivity type and the first selection gate electrode and the second selection gate electrode is different from an opposite conductivity type semiconductor layer, intrinsic semiconductor layer, or of any one. The non-volatile semiconductor memory device of claim 1 or 2, wherein the extension electrode portion comprises: an extension portion extending from the memory gate electrode of the selection gate formation region; and a linear end portion The side wall is disposed opposite to the side wall of the extending portion and arranged in parallel with the extending portion; and the connecting portion is connected to the extending portion and the end portion; and the opposite conductive semiconductor layer or the intrinsic semiconductor layer And formed along the extending portion and the side wall of the end portion. The non-volatile semiconductor memory device according to claim 1 or 2, wherein the adjacent conductive semiconductor layers adjacent to each other or adjacent to the intrinsic semiconductor layers are formed with sidewalls not formed on the extending electrode portion A solid cut-off portion of the semiconductor layer. The non-volatile semiconductor memory device of claim 4, wherein a film is provided on an upper surface of the memory gate electrode, and an entity cut-off region in which the solid cut portion is formed in the extended electrode portion is not The above-mentioned film is formed to provide a memory gate contact.