KR20180077101A - Nonvolatile semiconductor memory device - Google Patents

Abstract

The memory cell forming portion 3a includes four electrically cut portions 13a, 13b, 13d, 13c (13e, 13f, 13h, 13g) capable of cutting the source side select gate electrode SG and the drain side select gate electrode DG, Is provided along the side wall of the elongated electrode portion 15a (15b) and the portion for cutting the source side selection gate electrode SG and the drain side selection gate electrode DG is increased as compared with the conventional one. It is possible to prevent an erroneous reading operation caused by the voltage fluctuation in the data reading operation.

Description

Nonvolatile semiconductor memory device

The present invention relates to a nonvolatile semiconductor memory device.

Japanese Unexamined Patent Application Publication No. 11-129816 (Patent Document 1) discloses a memory cell in which a memory gate structure is disposed between two select gate structures (see Patent Document 1 and FIG. 15). Actually, in this memory cell, a drain region to which a bit line is connected and a source region to which a source line is connected, and one select gate structure, a memory gate structure, and another select Gate structures are arranged in order. In the memory cell including such a structure, a charge accumulation layer is formed in the memory gate structure, and data is written by injecting charge into the accumulation layer, or data can be erased by drawing charge in the charge accumulation layer consist of.

Here, Fig. 9 is a schematic diagram showing an example of the circuit configuration of the conventional nonvolatile semiconductor storage device 100. As shown in Fig. In this case, in the nonvolatile semiconductor memory device 100, for example, a plurality of memory cells 102a, 102b, 102c, 102d, 102e, 102f, 102g, and 102h are arranged in a matrix, The memory cell formation units 101a, 101b, 101c, and 101d are configured for the memory cells 102a, 102b, 102c, 102d, 102e, 102f, 102g, and 102h.

The nonvolatile semiconductor memory device 100 further includes memory cells 102a, 102c, 102e, 102g (102b, 102c, 102e, 102g) arranged in the column direction among the memory cells 102a, 102b, 102c, 102d, 102e, , 102d, 102f, and 102h share one bit line BL1 (BL2), and a predetermined bit voltage can be uniformly applied to each bit line BL1 and BL2. The nonvolatile semiconductor memory device 100 also includes memory gate lines MGL1, MGL2, MGL3, and MGL4 and drain side selection gate lines DGL1, DGL2, and DGL3 for the memory cell formation portions 101a, 101b, 101c, And DGL4, and a predetermined voltage may be applied to each of the memory gate lines MGL1, MGL2, MGL3, and MGL4 and each of the drain side selection gate lines DGL1, DGL2, DGL3, and DGL4.

In this nonvolatile semiconductor memory device 100, one source side selection gate line SGL and one source line SL are shared by all memory cells 102a, 102b, 102c, 102d, 102e, 102f, 102g, and 102h A predetermined source gate voltage is applied to the source side selection gate line SGL, and a predetermined source voltage can be applied to the source line SL.

Each of the memory cells 102a, 102b, 102c, 102d, 102e, 102f, 102g, and 102h has the same configuration. For example, the memory cell 102a includes a memory gate electrode MG to which the memory gate line MGL1 is connected, A drain-side selection gate electrode DG to which the drain-side selection gate line DGL1 is connected, and a source-side selection gate electrode SG to which the source-side selection gate line SGL is connected. In the memory cells 102a, 102b, 102c, 102d, 102e, 102f, 102g and 102h, charges are accumulated in the charge storage layers EC by the quantum tunnel effect generated by the voltage difference between the memory gate electrode MG and the channel layer So that the data can be written.

Here, in such a conventional nonvolatile semiconductor memory device 100, for example, in the data read operation for reading the data written in the memory cell 102a in the first row and first column, Only a memory cell 102b, 102d, 102f, or 102h to which a read voltage of 1.5 [V] is applied to the bit line BL1 connected to the bit line BL2 connected to the bit line BL2 A read inhibiting voltage of [V] may be applied.

In this case, 0 [V] is applied to the memory gate lines MGL1, MGL2, MGL3 and MLG4 in the nonvolatile semiconductor memory device 100, 1.5 [V] is applied to the source side selection gate line SGL, 0 [V] may be applied. At this time, in the nonvolatile semiconductor memory device 100, the read gate voltage of 1.5 [V] is applied to the drain side selection gate line DGL1 connected to the data read cell 102a, and the memory cell 102c The read inhibition gate voltage of 0 [V] can be applied to the drain side selection gate lines DGL2, DGL3, and DGL4 to which only the drain side selection gate lines DGL1, 102d, 102e, 102f, 102g, and 102h are connected.

As a result, in the data read cell 102a, the well immediately below the drain-side selection gate electrode DG connected to the bit line BL1 becomes conductive, but when charges are stored in the charge storage layer EC (data is written , The well under the memory gate electrode MG becomes non-conductive, the electrical connection between the source line SL and the bit line BL1 is cut off, and the read voltage of 1.5 [V] can be maintained as it is on the bit line BL1 .

On the other hand, when no charge is accumulated in the charge accumulation layer EC of the data read cell 102a (no data is written), the well immediately below the memory gate electrode MG becomes conductive and the data read cell The source line SL of 0 [V] and the bit line BL1 of 1.5 [V] are electrically connected to each other through the source line SL of 0 [V] The read voltage is lowered.

At this time, in the other memory cells 102c, 102e and 102g sharing the data read cell 102a and the bit line BL1, the voltage difference between the drain side selection gate lines DGL2, DGL3, DGL4 and the bit line BL1 causes the drain side selection The well immediately below the gate electrode DG becomes non-conductive and does not affect the read voltage of 1.5 [V] of the bit line BL1. Thus, in the nonvolatile semiconductor memory device 100, it is detected whether or not the read voltage of the bit line BL1 is changed to detect whether or not charge is accumulated in the charge storage layer EC of the data read cell 102a can do.

Next, the layout of the memory cell forming portion 101a, among the memory cell forming portions 101a, 101b, 101c, and 101d provided in the nonvolatile semiconductor memory device 100, will be described. Here, as the planar layout of the memory cell formation portion 101a, a planar layout as shown in Fig. 10 is conceivable. 10 is a schematic view showing an example of a planar layout when the memory cell formation portion 101a is viewed from above the semiconductor substrate. Here, the memory cell forming portion 101a in which three memory cells 102a, 102b, and 102c are provided will be described.

In this case, the memory cell formation portion 101a has the memory cell region ER3 in which the memory cells 102a, 102b, and 102c are disposed, and one select gate contact region ER6 is disposed at one end of the memory cell region ER3 And another select gate contact region ER7 is disposed at the other end of the memory cell region ER3. At the distal end of the select gate contact region ER6 (ER7), a physical cut region ER1 (ER5) is disposed via the electrically cut region ER2 (ER4).

In this case, the memory cell formation portion 101a is formed from one physical cut region ER1, one electrically cut region ER2, one select gate contact region ER6, memory cell region ER3, another select gate contact region ER7, A memory-gate contact MG is provided on the memory-gate electrode MG of the physical cut-off areas ER1 and ER5, for example, extending over the ER4 and another physical cut-off area ER5.

In the memory cell region ER3, a well W having a predetermined shape is formed on the surface of the semiconductor substrate. For example, the memory gate electrode MG is arranged so as to cross the memory arrangement regions W1, W2 and W3 formed in a strip shape of the well W. Here, the memory arrangement regions W1, W2 and W3 are divided into the source region WS side and the drain region WD side with the memory gate electrode MG as a boundary. In the memory cell formation section 101a, the source regions WS of the memory arrangement regions W1, W2 and W3 are connected to each other and connected to the source regions WS via the source-side source contacts SC connected to the source lines SL A predetermined source voltage can be uniformly applied.

Further, in the memory cell formation section 101a, the drain regions WD of the memory arrangement regions W1, W2 and W3 are separated from each other, and the other bit lines BL1, BL2, ... through the bit contacts BC provided for the respective drain regions WD. A predetermined bit voltage can be individually applied to each drain region WD.

One side wall 112 of the memory gate electrode MG is disposed on the drain region WD side of the well W in the memory cell region ER3 of the memory cell formation portion 101a and the drain side selection gate electrode DG Respectively. On the other hand, another side wall 111 of the memory gate electrode MG is disposed on the source region WS side of the well W, and a source side select gate electrode SG is formed along the side wall 111. [ In this case, the drain-side selection gate electrode DG and the source-side selection gate electrode SG are shared by the plurality of memory cells 102a, 102b, and 102c arranged in the row direction together with the memory gate electrode MG. The drain-side selection gate electrode DG and the source-side selection gate electrode SG are insulated from the memory gate electrode MG by a sidewall spacer (not shown) containing an insulating material.

A selective gate contact forming portion Ca having a wide width provided with the drain-side select gate contact DGC is formed in one select gate contact region ER6 and a drain-side select gate line DGL2 (Fig. 9) is formed in the drain- A predetermined voltage from the drain side selection gate contact DGC and the selection gate contact formation portion Ca can be applied.

9) is formed in the other selection gate contact region ER7 and the source-side selection gate line SGL (Fig. 9) is formed in the other- Can be applied through the source side selection gate contact SGC and the selection gate contact formation portion Cb.

In addition, in the electrically cut regions ER2 and ER4, the memory gate electrode MG is extended from the memory cell region ER3. However, unlike the memory cell region ER3, the drain-side select gate electrode DG and the source-side select gate electrode SG are extended And electrically disconnected portions 103a and 103b for forming pin junctions are formed instead of the drain-side selection gate electrode DG and the source-side selection gate electrode SG. In practice, the electrically cut portions 103a and 103b are formed so that the intrinsic semiconductor layers Ia and Ib including the i type and the conductive type (p type in this case) different from the drain side selection gate electrode DG and the source side selection gate electrode SG The intrinsic semiconductor layers Ia and Ib and the inversed conductivity semiconductor layer OC are arranged in the order of the intrinsic semiconductor layer Ia, the inverse-conducting semiconductor layer OC, and the intrinsic semiconductor layer Ib, And are formed along the side walls 111 and 112, respectively.

As described above, in the electrically cut regions ER2 and ER4 of the memory cell formation portion 101a, the n-type drain side selection gate electrode DG and the source side selection gate electrode SG are used as the starting points and the i-type intrinsic semiconductor layer Ia, the p- Type semiconductor layer OC and the i-type intrinsic semiconductor layer Ib in this order, a pin junction can be formed at the end portions of the n-type drain-side selection gate electrode DG and the source-side selection gate electrode SG, The drain-side selection gate electrode DG and the source-side selection gate electrode SG can be electrically disconnected at two points of the electrical cut-off portions 103a and 103b.

In addition, a conductive layer made of a semiconductor material or the like is formed along the side walls 111 and 112 and the end wall 113 of the memory gate electrode MG in the physical cut regions ER1 and ER5 at the ends of the electrically cut regions ER2 and ER4 And a physical cutout portion 104 in which the drain-side select gate electrode DG and the source-side select gate electrode SG are not in contact with each other is formed. Thus, in the memory cell forming portion 101a, not only the two electrical cut portions 103a and 103b, but also the physical cut portions 104 of the physical cut regions ER1 and ER5, the drain side select gate electrode DG and the source side select gate electrode SG are electrically disconnected from each other, and a predetermined voltage can be individually applied to the drain-side selection gate electrode DG and the source-side selection gate electrode SG.

Japanese Patent Application Laid-Open No. 2011-129816

In this memory cell formation portion 101a, the electrical connection between the drain side selection gate electrode DG and the source side selection gate electrode SG is prevented by the two electrical cut portions 103a and 103b and one physical cutout portion 104 However, it is conceivable that a problem occurs in these electrical cuts 103a and 103b and the physical cutout 104 due to some cause, and the drain-side selection gate electrode DG and the source-side selection gate electrode SG are electrically connected.

9, in the data read operation for reading the data of the memory cell 102a in the first row and the first column, in the memory cell forming portion 101b that does not read data, If the gate electrode DG and the source side selection gate electrode SG are electrically connected to each other and a short failure occurs, the drain side selection gate line DGL2 of 0 [V] and the source side selection of 1.5 [V] The gate line SGL is electrically connected (indicated by the line L in Fig. 9).

As a result, in the nonvolatile semiconductor memory device 100, the voltage of 0 [V] of the drain side selection gate line DGL2 rises, or the voltage of the source side selection gate DGL2 shared by all the memory cells 102a, 102b, The voltage of 1.5 [V] of the line SGL is lowered, and there is a possibility that the read malfunction may occur due to the voltage fluctuation of the drain side selection gate line DGL2 and the source side selection gate line SGL.

Therefore, in such a nonvolatile semiconductor memory device 100, measures are further taken so as not to cause a situation in which the drain-side selection gate electrode DG and the source-side selection gate electrode SG are electrically connected to each other, It is desired to prevent an erroneous reading operation caused by voltage fluctuation in the read operation.

It is therefore an object of the present invention to provide a nonvolatile semiconductor memory device capable of preventing an erroneous reading operation caused by a voltage fluctuation in a data read operation more than ever.

In order to solve such a problem, a nonvolatile semiconductor memory device according to claim 1 is a nonvolatile semiconductor memory device provided with a plurality of memory cell forming sections, and the memory cell forming section includes a first select gate insulating film A second select gate structure having a first select gate structure having a first select gate electrode, a second select gate structure having a second select gate electrode on the well via a second select gate insulating film, A memory gate structure disposed between the select gate structures with a sidewall spacer interposed therebetween and stacked on the well in the order of a lower gate insulating film, a charge storage layer, a top gate insulating film, and a memory gate electrode; The memory gates of the select gate formation regions in which the second select gate structures are arranged opposite to each other And an extension electrode provided on the sidewall of the elongated electrode section, wherein the sidewall of the elongated electrode section has an inverted-conductivity type semiconductor layer or an intrinsic semiconductor layer having a different conductivity type from the first selection gate electrode and the second selection gate electrode And at least three of them are installed.

The nonvolatile semiconductor memory device according to claim 2 is a nonvolatile semiconductor memory device provided with a plurality of memory cell forming sections, wherein the memory cell forming section includes a first select gate electrode A second select gate structure having a second select gate electrode on the well via a second select gate insulating film; and a second select gate structure between the first select gate structure and the second select gate structure And a memory gate structure provided on the well in the order of the lower gate insulating film, the charge storage layer, the upper gate insulating film, and the memory gate electrode, the memory gate structure being provided with a sidewall spacer, Wherein the memory cell formation portion includes a first selection gate structure and a second selection gate structure, Wherein the first selection gate electrode and the second selection gate electrode are formed continuously on an extended electrode portion extended from the memory gate electrode of the selective gate formation region arranged in the first direction, Is characterized in that at least three of the inversed conductivity type semiconductor layers or the intrinsic semiconductor layers having different conductivity types are provided.

In the nonvolatile semiconductor memory device according to Claim 1 of the present invention, at least three of the reverse conducting semiconductor layers or the intrinsic semiconductor layers capable of cutting the first select gate electrode and the second select gate electrode are provided along the side wall of the elongated electrode portion It is possible to increase the number of portions for cutting the first select gate electrode and the second select gate electrode as compared with the prior art and to prevent the erroneous read operation caused by the voltage fluctuation in the data read operation more than ever.

In the nonvolatile semiconductor memory device according to claim 2 of the present invention, the first select gate electrode of one memory cell forming section and the first select gate electrode or the second select gate electrode of the other memory cell forming section Wherein at least three of the inverted-type semiconductor layer and the intrinsic semiconductor layer which cut the connection are provided along the side wall of the extended electrode portion, and the first selection gate electrode of one memory cell formation portion and the first selection gate electrode of the other memory cell formation portion It is possible to increase the number of portions for cutting the first select gate electrode or the second select gate electrode as compared with the prior art and to prevent the erroneous read operation caused by the voltage fluctuation in the data read operation more than the conventional one.

1 is a schematic diagram showing a cross-sectional structure of a memory cell provided in a nonvolatile semiconductor memory device of the present invention.
2 is a schematic diagram showing a circuit configuration of a nonvolatile semiconductor memory device according to the present invention.
3 is a table summarizing voltage values in various operations of the nonvolatile semiconductor memory device.
4 is a schematic view showing a plane layout of the nonvolatile semiconductor memory device according to the first embodiment.
5 is a schematic view showing a plane layout of the nonvolatile semiconductor memory device according to the second embodiment.
6 is a schematic view showing a plane layout of a nonvolatile semiconductor memory device according to the third embodiment.
7 is a schematic diagram showing a planar layout of the nonvolatile semiconductor memory device according to the fourth embodiment.
8 is a schematic view showing a plane layout of a nonvolatile semiconductor memory device according to another embodiment.
9 is a schematic diagram showing a circuit configuration of a conventional nonvolatile semiconductor memory device.
10 is a schematic view showing a planar layout of a conventional memory cell forming portion.

Hereinafter, embodiments for carrying out the present invention will be described. The description will be given in the following order.

<1. First Embodiment>

1-1. Configuration of memory cell

1-2. Circuit configuration of a nonvolatile semiconductor memory device according to the present invention

1-3. With respect to the voltage in various operations in the nonvolatile semiconductor memory device

1-4. Flat layout of nonvolatile semiconductor memory device

1-5. Action and effect

<2. Flat layout of nonvolatile semiconductor memory device according to the second embodiment >

<3. Flat layout of nonvolatile semiconductor memory device according to the third embodiment >

<4. Flat layout of nonvolatile semiconductor memory device according to the fourth embodiment >

<5. Other Embodiments>

<6. Regarding the positional relationship between the electrical cutting area and the physical cutting area>

(1) First Embodiment

(1-1) Configuration of memory cell

First, the structure of a memory cell arranged in a matrix form in the nonvolatile semiconductor memory device of the present invention will be described first. As shown in Fig. 1, the memory cell 2a includes a memory gate structure 4a for forming an N-type transistor structure on the well W including, for example, P-type Si, A drain-side select gate structure 5a for forming a metal-oxide-semiconductor (MOS) transistor structure and a source-side select gate structure 6a for forming an N-type MOS transistor structure are formed.

A drain region WD at one end of the drain side selection gate structure 5a and a source region WS at one end of the source side selection gate structure 6a are formed at a predetermined distance on the surface of the well W, The bit line BL1 is connected to the region WD, and the source line SL is connected to the source region WS. Also, on the surface of the well W, the lightly doped drain region WDa is formed adjacent to the drain region WD, and a sidewall SW formed along the sidewall of the drain-side select gate structure 5a is disposed on the lightly doped drain region WDa. A low concentration source region WSa is formed adjacent to the source region WS on the surface of the well W, and a sidewall SW formed along the sidewall of the source side select gate structure 6a is disposed on the low concentration source region WSa.

Memory gate structure (4a) is, on the wells W between the lightly doped drain region WDa, and lightly doped source region WSa, via the lower gate insulating film Bo comprising a insulating material such as SiO _2, for example, silicon nitride (Si ₃ N _And a charge storage layer EC including silicon oxynitride (SiON), alumina (Al ₂ O ₃ ), hafnia (HfO ₂ ), and the like. And has a memory gate electrode MG via an upper gate insulating film Tp. Thus, the memory gate structure 4a has a structure in which the charge accumulation layer EC is insulated from the well W and the memory gate electrode MG by the lower gate insulating film Bo and the upper gate insulating film Tp.

In addition to this structure, a cap film CP formed of an insulating material is formed on the memory gate electrode MG in the memory gate structure 4a, and a silicide layer S1 on the upper surface of the drain side select gate structure 5a, The silicide layer S2 on the upper surface of the side selection gate structure 6a is formed so as to be away from the upper surface of the memory gate electrode MG by the thickness of the cap film CP. As described above, the memory gate electrode MG in the region of the memory cell 2a has a structure in which a silicide layer is not formed on the upper surface and is covered with the cap film CP.

In the case of this embodiment, a cap film CP is, for example, the lower cap film CPa phase comprising an insulating material such as SiO _2, the art bottom cap film CPa than an insulating material, such as different SiN upper cap film the CPb are stacked laminate Structure.

The memory gate electrode MG of the memory gate structure 4a is provided with a wall-shaped first sidewall 11 and a wall-shaped second sidewall 12 opposed to the first sidewall 11 . The memory gate structure 4a is formed such that each side wall of the lower gate insulating film Bo, the charge storage layer EC, the upper gate insulating film Tp and the cap film CP is formed along the first sidewall 11 and the second sidewall 12 of the memory gate electrode MG And the lower gate insulating film Bo, the charge accumulating layer EC, the upper gate insulating film Tp, and the cap film CP are formed in the region between the first sidewall 11 and the second sidewall 12 of the memory gate electrode MG.

The memory gate structure 4a is provided with a sidewall spacer (not shown) along the respective side walls of the second sidewall 12 of the memory gate electrode MG, the lower gate insulating film Bo, the charge storage layer EC, the upper gate insulating film Tp, And the drain side selection gate structure 5a is adjoined via the sidewall spacer 28a. The sidewall spacer 28a formed between the memory gate structure 4a and the drain side select gate structure 5a is formed with a predetermined film thickness and the memory gate structure 4a and the drain side select gate structure 5a It is made to be insulated. The film thickness of the sidewall spacer 28a between the memory gate structure 4a and the drain side selection gate structure 5a is preferably set such that the breakdown voltage of the sidewall spacer 28a or the breakdown voltage of the memory gate structure 4a and the drain- In consideration of the read current between the source electrode 5a and the source electrode 5a, a width of 5 [nm] or more and 40 [nm] or less.

The drain side selection gate structure 5a is formed on the well W between the sidewall spacer 28a and the drain region WD so as to have a film thickness of 9 nm or less, preferably 3 nm or less, Side select gate insulating film 30, and a drain-side select gate electrode DG is formed on the drain-side select gate insulating film 30. A silicide layer S1 is formed on the drain-side selection gate electrode DG as a second selection gate electrode, and the drain-side selection gate line DGL1 as a second selection gate line is connected to the silicide layer S1.

The memory gate structure 4a is also provided with side walls 11 including insulating materials along the respective side walls of the first sidewall 11 of the memory gate electrode MG, the lower gate insulating film Bo, the charge storage layer EC, the upper gate insulating film Tp, A spacer 28b is formed, and the source-side selection gate structure 6a is adjoined via the sidewall spacer 28b. The sidewall spacer 28b formed between the memory gate structure 4a and the source side selection gate structure 6a is selected to have a film thickness of 5 [nm] or more and 40 [nm] or less, which is the same as that of the sidewall spacer 28a , And the memory gate structure 4a and the source side selection gate structure 6a can be insulated from each other.

The source side select gate structure 6a is formed on the well W between the sidewall spacer 28b and the source region WS to have a film thickness of 9 nm or less, preferably 3 nm or less, Side select gate insulating film 33, and a source-side select gate electrode SG is formed on the source-side select gate insulating film 33. The source- A silicide layer S2 is formed on the upper surface of the source side selection gate electrode SG as the first selection gate electrode, and the source side selection gate line SGL as the first selection gate line is connected to the silicide layer S2.

In addition, in the case of this embodiment, the source side selection gate electrode SG and the drain side (source side) formed along the first sidewall 11 and the second sidewall 12 of the memory gate electrode MG via the sidewall spacers 28a and 28b The selection gate electrode DG is formed in a sidewall shape in which the top portion descends toward the well W as the memory gate electrode MG is separated from each other.

The memory cell 2a is formed such that the source-side select gate structure 6a and the drain-side select gate structure 5a are disposed along the sidewalls (the first sidewall 11 and the second sidewall 12) of the memory gate structure 4a, Even if these source-side selection gate structures 6a and drain-side selection gate structures 5a are close to the memory gate structure 4a, respectively, by the cap film CP formed on the memory gate electrode MG, The suicide layer S1 on the side selection gate electrode DG and the silicide layer S2 on the source side selection gate electrode SG are separated from the memory gate electrode MG so that shorting between the silicide layers S1 and S2 and the memory gate electrode MG can be prevented consist of.

(1-2) Circuit configuration of the nonvolatile semiconductor memory device according to the present invention

Next, the circuit configuration of the nonvolatile semiconductor memory device according to the present invention will be described. 2, a plurality of memory cells 2a, 2b, 2d, 2e, 2g, 2h, 2i, 2j are arranged in a matrix form in the nonvolatile semiconductor memory device 1, for example. Each memory cell 2b, 2d, 2e, 2g, 2h, 2i, and 2j has the same structure as the memory cell 2a described in FIG. 1 and includes a memory gate electrode MG to which a memory gate line MGL is connected, Side select gate electrode DG to which the side select gate lines DGL1 (DGL2, DGL3, DGL4) are connected, and a source side select gate electrode SG to which the source side select gate line SGL is connected.

The nonvolatile semiconductor memory device 1 includes memory cell forming portions 3a, 3b, 3c, and 3d for each of the memory cells 2a, 2b, 2d, 2e, 2g, 2h, 2i, For example, a predetermined substrate voltage may be applied to the memory cells 2a, 2b, 2d, and 2e by the substrate voltage line Back.

The nonvolatile semiconductor memory device 1 also includes memory cells 2a, 2d, 2g, 2i, 2b, 2h, 2i, 2j arranged in the column direction among the memory cells 2a, 2b, 2d, 2e, 2d, 2g, 2i, 2b, 2e, 2h, and 2j by the bit lines BL1, BL2, A predetermined bit voltage can be applied uniformly. The nonvolatile semiconductor memory device 1 also shares the drain side selection gate lines DGL1, DGL2, DGL3, and DGL4 for each of the memory cell formation portions 3a, 3b, 3c, and 3d, A predetermined voltage may be applied to each of the memory cell formation portions 3a, 3b, 3c, and 3d by the gate lines DGL1, DGL2, DGL3, and DGL4.

In this nonvolatile semiconductor memory device 1, one memory gate line MGL, one source side selection gate line SGL, and one source line SL are connected to all the memory cells 2a, 2b, 2d, 2e, 2g, 2h, 2i, and 2j, a predetermined memory gate voltage is applied to the memory gate line MGL, a predetermined source gate voltage is applied to the source side select gate line SGL, and a predetermined source voltage is applied to the source line SL .

(1-3) Regarding the voltage in various operations in the nonvolatile semiconductor memory device

Next, various operations in the nonvolatile semiconductor memory device 1 will be described. FIG. 3 is a schematic diagram showing the nonvolatile semiconductor memory device 1 shown in FIG. 2, in which a data write operation ("Prog") for injecting a charge into the charge storage layer EC of the memory cell 2a, (&Quot; Read &quot;) for detecting whether or not charge is stored in the charge storage layer EC of the cell 2a, and a data erase operation (&quot; Read &quot;) for extracting charge in the charge storage layer EC Is a table showing an example of the voltage value at each site in the time (&quot; Erase &quot;).

In the column of &quot; Prog &quot; in Fig. 3, the voltage values ("selection column" and "selection row") when charges are injected into the charge storage layer EC of the memory cell 2a, (&Quot; non-selected column &quot; or &quot; unselected row &quot;) when no charge is injected into the EC.

For example, when charges are injected into the charge accumulation layer EC of the memory cell 2a, as shown in the column of &quot; Prog &quot; in FIG. 3, charge accumulation of 12 [V] from the memory gate line MGL to the memory gate electrode MG A gate voltage is applied and a substrate voltage of 0 [V] can be applied to the well W (denoted as &quot; Back &quot; in Fig. 3). At this time, a gate-off voltage of 0 [V] is applied to the source-side selection gate electrode SG from the source-side selection gate line SGL, and a source-off voltage of 0 [V] can be applied to the source region WS from the source line SL . Thus, the source-side selection gate structure 6a blocks the electrical connection between the source region WS and the channel layer forming carrier region of the memory gate structure 4a, The voltage application to the layer forming carrier region can be prevented.

On the other hand, a drain side selection gate voltage of 1.5 [V] is applied to the drain side selection gate electrode DG from the drain side selection gate line DGL1, and a charge accumulation bit voltage of 0 [V] is applied to the drain region WD from the bit line BL1 . Thus, the drain side selection gate structure 5a can electrically connect the drain region WD and the channel layer formation carrier region of the memory gate structure 4a.

In the memory gate structure 4a, the channel layer forming carrier region is electrically connected to the drain region WD, so that a carrier is induced in the channel layer forming carrier region, and a channel layer having a value of 0 [V] The surface of the well W can be formed. In this manner, in the memory gate structure 4a, a large voltage difference 12 [V] of 12 [V] is generated between the memory gate electrode MG and the channel layer, and by the quantum tunnel effect generated thereby, Charge can be injected into the accumulation layer EC, and the data can be written.

Further, when the charge accumulation gate voltage necessary for injecting a charge into the charge accumulation layer EC is applied to the memory gate electrode MG of the memory cell 2a, the injection of the charge from the memory cell 2a into the charge accumulation layer EC is inhibited The source side selection gate structure 6a blocks the electrical connection between the well W in the region facing the memory gate electrode MG and the source region WS and also the drain side selection gate structure 5a, And blocks the electrical connection between the well W in the region facing the gate electrode MG and the drain region WD.

As a result, in the memory cell 2a in which no data is written, a depletion layer is formed in the channel layer forming carrier region, and the potential of the surface of the well W rises based on the charge accumulation gate voltage, And the voltage difference between the surface of the well W and the surface of the well W becomes small, charge injection into the charge storage layer EC can be prevented.

3, the bit line BL1 connected to the memory cell 2a to be read, for example, is precharged to 1.5 [V], for example, The source line SL is set at 0 [V] to detect the potential of the bit line BL1 that changes depending on whether or not a current flows through the memory cell 2a, thereby determining whether or not charge is accumulated in the charge storage layer EC of the memory cell 2a Or not. Specifically, when data is read from the memory cell 2a, when charges are accumulated in the charge storage layer EC of the memory gate structure 4a (when data is written) Conduction state in the well W below, and the electrical connection between the drain region WD and the source region WS can be cut off. Thus, in the memory cell 2a for reading data, the read voltage of 1.5 [V] on the bit line BL1 connected to the drain region WD can be maintained as it is.

On the other hand, in the case where no charge is accumulated in the charge storage layer EC of the memory gate structure 4a (when no data is written) when the data of the memory cell 2a is read, the memory gate structure 4a, The source line SL of 0 [V] and the bit line BL1 of 1.5 [V] are connected to the drain region WD and the source region WS through the memory cell 2a, Are electrically connected. Thus, in the memory cell 2a for reading data, the read voltage of the bit line BL1 is applied to the source line SL of 0 [V], so that the read voltage of 1.5 [V] applied to the bit line BL1 is lowered do.

In this manner, in the nonvolatile semiconductor memory device 1, whether or not the read voltage of the bit line BL1 has changed is detected, thereby reading out whether or not the charge is accumulated in the charge storage layer EC of the memory cell 2a Operation can be executed. Further, a non-read voltage of 0 [V] may be applied to the bit line BL2 to which only the memory cells 2b, 2e, 2h and 2j which do not read data are connected.

Incidentally, at the time of erasing data (&quot; Erase &quot; in FIG. 3) for drawing out the charge in the charge storage layer EC of the memory cell 2a, When the memory gate voltage is applied, the charge in the charge storage layer EC is extracted toward the well W of 0 [V], and data can be erased.

(1-4) Flat layout of nonvolatile semiconductor memory device

Next, the planar layout of the above-described nonvolatile semiconductor memory device 1 will be described. 4 is a schematic view showing a planar layout viewed from above a semiconductor substrate of the nonvolatile semiconductor memory device 1 of the present invention in which a plurality of memory cell forming portions 3a, 3b, 3c, to be. In addition, since the memory cell forming portions 3a, 3b, 3c, ... all have the same configuration, one memory cell forming portion 3a will be described below.

Incidentally, Fig. 1 showing a cross-sectional configuration of the memory cell 2a shows a cross-sectional configuration taken along the line A-A 'in Fig. In addition, in Fig. 4, in addition to the sidewall spacers 28a and 28b formed on the sidewall of the memory gate structure 4a shown in Fig. 1, the drain side selection gate structure 5a and the source side selection gate structure 6a are formed And the sidewall SW, the silicide layers S1, S2, etc., are omitted. Further, in the case of this embodiment, the memory cell forming portions 3a, 3b, 3c, ... extend in one direction (row direction in FIG. 4) and are arranged on the semiconductor substrate so as to be accommodated at a predetermined distance.

In this case, the memory cell formation portion 3a has the selection gate formation region ER9 in which the source-side selection gate electrode SG and the drain-side selection gate electrode DG are opposed to each other with the memory gate electrode MG therebetween. The selection gate formation region ER9 includes a memory cell region ER3 in which a plurality of memory cells 2a, 2b and 2c are formed along the longitudinal direction of the memory cell formation portion 3a and one memory cell region ER3 provided at one end of the memory cell region ER3 A select gate contact region ER6, and another select gate contact region ER7 provided at the other end of the memory cell region ER3.

Incidentally, a plurality of memory cells 2d, 2e, 2f (2g, 2h, 2i) are formed in the memory cell region ER3 along the longitudinal direction in the other memory cell formation portions 3b, 3c. 2 shows only the memory cells 2a and 2b (2d, 2e, 2g, and 2h) in the memory cell forming portions 3a and 3b and 3c shown in FIG. 2. In FIG. 4, (2f, 2i) adjacent to the memory cells 2e, 2h in the third column.

In practice, in this memory cell forming portion 3a, a memory gate electrode MG extending in one direction is formed in the select gate forming region ER9. The memory gate electrode MG of the selection gate formation region ER9 has a first sidewall extending over the selection gate formation region ER9 and a second sidewall 12 disposed opposite to the first sidewall, The source side selection gate electrode SG is arranged along the second side wall 12 and the drain side selection gate electrode DG is arranged along the second side wall 12. [

Here, in the memory cell region ER3, a well W having a predetermined shape is formed on the surface of the semiconductor substrate. For example, in the memory arrangement regions W1, W2 and W3 formed in a strip shape of the well W, . The memory cell region ER3 of one memory cell formation portion 3a is provided with a memory gate structure 4a, a drain side selection gate structure 5a and a memory cell 2a having a source side selection gate structure 6a 2b, and 2c are formed on the memory arrangement areas W1 (W2, W3).

The memory arrangement regions W1, W2 and W3 of the well W are divided into the source region WS side and the drain region WD side with the memory gate structure 4a as a boundary. Among the memory arrangement regions W1, W2 and W3, the drain regions WD between the memory cell formation portions 3a and 3b are separated from each other, and each has a structure in which a columnar bit contact BC is provided individually. Each bit contact BC has different bit lines BL1, BL2, ... (Fig. 2) are connected, and corresponding bit lines BL1, BL2, ... A predetermined bit voltage may be applied individually. As a result, in each drain region WD of the memory cell formation section 3a, different bit lines BL1, BL2, ..., A predetermined bit voltage can be applied through the bit contact BC.

In this embodiment, the drain region WD is shared by one memory cell forming portion 3a and the other memory cell forming portion 3b adjacent to the memory cell forming portion 3a, The same bit voltage as that of the cells 2a (2b, 2c) can be applied to the memory cells 2d (2e, 2f) of the other memory cell forming portion 3b.

On the other hand, the source regions WS of the memory arrangement regions W1, W2 and W3 are connected to one another and share the main-phase source contact SC provided at a predetermined position. The source contact SC has a structure in which a source line SL (FIG. 2) is connected, and a predetermined source voltage applied from the source line SL can be uniformly applied to the source regions WS of the memory layout regions W1, W2 and W3 have.

In this embodiment, the first sidewall 11 of the memory gate electrode MG is disposed on the source region WS side of the well W, and the first sidewall 11 of the memory gate electrode MG is formed in the memory cell forming portion 3a. The source side selection gate structure 6a is formed. A second side wall 12 of the memory gate electrode MG is disposed on the drain region WD side of the well W and a drain side select side 12 along the second side wall 12 of the memory gate electrode MG is formed in the memory cell forming portion 3a. A gate structure 5a is formed.

The source side selection gate structure 6a is formed with a source side selection gate electrode SG formed in the form of a sidewall along the first sidewall 11 in the memory gate structure 4a, A wide selection gate contact forming portion Ca formed integrally with the SG is formed in one select gate contact region ER7.

In the select gate contact forming portion Ca, a sinking portion that is placed on the memory gate electrode MG and a plane portion whose surface is formed in a planar shape along the semiconductor substrate are formed, and a source side select gate line (not shown) And the connected pillar-shaped source side selection gate contacts SGC are provided on the planar portion. Thus, in the source side selection gate electrode SG having a narrow and inclined side wall shape, a predetermined voltage from the source side selection gate line SGL is applied through the source side selection gate contact SGC and the selection gate contact formation portion Ca .

The drain side selection gate structure 5a is also provided with a drain side selection gate electrode DG formed in a sidewall shape along the second sidewall 12 in the memory gate structure 4a, A selective gate contact forming portion Cb formed integrally with the electrode DG and having a wide width is formed in another select gate contact region ER6.

The select gate contact forming portion Cb also has an overlying portion that is placed on the memory gate electrode MG and a flat portion whose surface is formed in a planar shape along the semiconductor substrate. Side selection gate contact DGC is provided on the planar portion. As a result, a predetermined voltage from the drain side selection gate line DGL1 is also applied through the drain side selection gate contact DGC and the selection gate contact formation portion Cb in the narrow side wall type drain side selection gate electrode DG .

Incidentally, the selective gate contact forming portions Ca and Cb provided in the selected gate contact regions ER7 and ER6 are provided continuously with the source side select gate electrode SG or the drain side select gate electrode DG, and the source side select gate contact SGC or drain It may be formed in various other shapes as long as it can form the side select gate contacts DGC and may be formed at various positions on one or both sides in the select gate contact regions ER7 and ER6.

In addition to this structure, the memory cell forming portion 3a is provided with an electrically cut region ER2 (ER4) at the distal end of the selected gate contact region ER6 (ER7) And a region ER1 (ER5) is arranged. In the electrically cut region ER2 (ER4) and the physical cut region ER1 (ER5), extended electrode portions 15a and 15b formed by extending the memory gate electrode MG from the select gate forming region ER9 are provided.

In this embodiment, the elongated electrode portions 15a and 15b are formed in an inverted U shape as viewed from above the semiconductor substrate, and extend from the distal end of the select gate forming region ER9 via the electrically cut region ER2 (ER4) Extends to the cut region ER1 (ER5), is folded back in the physical cut region ER1 (ER5) and extends again to the electrically cut region ER2 (ER4).

In practice, the extended electrode portions 15a and 15b have an extended portion 16a extending linearly from the memory gate electrode MG of the select gate forming region ER9 and a straight line portion 16b formed at a lateral outer position of the extended portion 16a And an extended portion 16a and an end portion 16b are disposed in the electrically cut region ER2, and the extended portion 16a and the continuous portion 16c are connected to each other (Side wall non-forming portion) 16c serving as a folded portion is disposed in the physical cutting region ER1.

In this embodiment, one extended electrode portion 15a is folded back toward the first sidewall 11 of the memory gate electrode MG, and the end portion 16b is disposed on the first sidewall 11 side While the other extended electrode portions 15b are folded back toward the second sidewall 12 of the memory gate electrode MG and the end portion 16b is disposed on the second sidewall 12 side.

In the electrically cut region ER2 (ER4), the memory gate electrode MG extends from the select gate forming region ER9 as extended electrode portions 15a and 15b. However, unlike the select gate forming region ER9, the source side select gate electrode SG and the source- Side selection gate electrode DG is not extended and four electric cut portions 13a and 13b (not shown) are formed on the side walls of the extension electrode portions 15a and 15b instead of the source-side selection gate electrode SG and the drain- , 13c, and 13d (13e, 13f, 13g, and 13h) are formed.

The electric cut portions 13a, 13b, 13c, and 13d (13e, 13f, 13g, and 13h) have the same configuration and include the sidewall-shaped intrinsic semiconductor layers Ia and Ib including i- And a reverse conducting semiconductor layer OC is formed between the intrinsic semiconductor layers Ia and Ib. In addition, the inversing type semiconductor layer OC is formed by a conductive type (p type in this case) different from the source side selection gate electrode SG and the drain side selection gate electrode DG.

One extended portion 16a of the extended electrode portion 15a is formed with one electrical cutout portion 13a along one sidewall which is provided continuously and flatly with the first sidewall 11 of the memory gate electrode MG, Another electrical cut-away portion 13c is formed along the other sidewall that is continuously and flat with the second sidewall 12 of the memory gate electrode MG. In the memory cell forming portion 3a, for example, by the electrical cutout portion 13a, the extension portion 16a is formed from the first sidewall 11 of the memory gate electrode MG with the n-type source side selection gate electrode SG as a start point, Lt; RTI ID = 0.0 &gt; a &lt; / RTI &gt; In the memory cell forming portion 3a as well, on the second sidewall 12 side of the memory gate electrode MG, the n-type drain side selection gate electrode DG is used as the starting point, for example, by the electrical cut- A pin junction can be formed along the side wall of the extension portion 16a from the two side walls 12.

One electrical cutout portion 13b is formed on the side wall facing the extended portion 16a at the end portion 16b of the extended electrode portion 15a and another electrically cutout portion 13d is formed at the side wall disposed on the outer side . The extended electrode portion 15a is formed with a drain formed along the second sidewall 12 of the memory gate electrode MG from the source side select gate electrode SG formed along the first sidewall 11 of the memory gate electrode MG, Four electrically cut portions 13a, 13b, 13d, and 13c may be formed in this order on the sidewall between the side select gate electrodes DG. As a result, three or more reverse-conductivity type semiconductor layers and an intrinsic semiconductor layer are provided on the side wall of the elongated electrode portion 15a.

This makes it possible to prevent the source side selection gate electrode SG and the electrical cutout portion 13b of the end portion 16b from being damaged by foreign substances adhering to the electrical cutout portion 13a of the extension portion 16a or the successive attachment portion 16c Type source side selection gate electrode SG to the first side wall 11 of the memory gate electrode MG along the side wall of the end portion 16b by the electrical cut portions 13b and 13d pin junction can be formed.

In addition to this configuration, the continuous mounting portion 16c as the side wall non-forming portion in the physical cutting area ER1 is provided with a side wall of the extending portion 16a and a side wall of the end portion 16b, Physical cutouts 14a and 14b are formed. These physical cutting portions 14a and 14b are formed by forming the outer peripheral wall and the inner peripheral wall of the continuous mounting portion 16c in the outer side wall and the inner peripheral wall of the continuous mounting portion 16c, As shown in FIG. As a result, the physical cutout portions 14a and 14b form a physical cut with a gap between the source-side select gate electrode SG and the drain-side select gate electrode DG to form the source-side select gate electrode SG and the drain- Conductive state.

In this embodiment, one physical cutout 14a is formed along the outer circumferential wall of the continuous mount 16c and includes an electrical cutout 13c formed on one sidewall of the extension 16a, A gap is formed between the electrically cut portions 13d formed on one sidewall of the first and second cut portions 16a and 16b so that the electrically cut portions 13c and 13d are not connected to each other. The other physical cutting portion 14b is formed along the inner peripheral wall of the continuous mounting portion 16c and includes an electrical cutout portion 13a formed on the other side wall of the extended portion 16a and an electrical cut portion 13b formed on the other side wall of the end portion 16b. A gap is formed between the cut portions 13b so that the electrically cut portions 13a and 13b are not connected to each other.

As described above, the extended electrode portion 15a is provided with the drain side selection gate electrode SG formed along the first sidewall 11 of the memory gate electrode MG, the drain side formed along the second sidewall 12 of the memory gate electrode MG The electrical cut portion 13a, the physical cut portion 14b, the electrical cut portions 13b and 13d, the physical cut portion 14a, and the electrical cut portion 13c can be arranged in this order on the side wall between the selective gate electrode DG have. Thus, the extended electrode portion 15a is electrically connected to the source-side selection gate electrode SG and the drain-side selection gate 14b by the four electrical cutouts 13a, 13b, 13d, and 13c and the two physical cutouts 14a and 14b. It is possible to prevent the electrode DG from becoming conductive.

In addition, similarly to the extended electrode portion 15b disposed at the other end portion of the memory cell forming portion 3a, the extending portion 16a is provided with the first side wall 11 of the memory gate electrode MG, One electrical cutout 13e is formed along one of the installed sidewalls and another electrical cutout 13g is formed along the other sidewall that is continuously and continuously connected to the second sidewall 12 of the memory gate electrode MG. One electrical cutout 13h is formed on the side wall opposite to the extended portion 16a at the end portion 16b of the other extended electrode portion 15b and another electrical cutout 13f is formed at the side wall disposed outside Respectively.

The extended electrode portion 15b is provided with a drain electrode 15a formed along the second sidewall 12 of the memory gate electrode MG from the source side select gate electrode SG formed along the first sidewall 11 of the memory gate electrode MG, Four electrically cut portions 13e, 13f, 13h, and 13g may be formed in this order on the sidewall between the side select gate electrodes DG.

In addition to this configuration, the continuous mounting portion 16c in the other physical cutting area ER5 is also provided with the outer cutout wall in which the side wall of the extended portion 16a and the side wall of the end portion 16b are continuously provided, And 14d are formed. These physical cuts 14c and 14d are also formed in such a manner that a conductive layer such as a semiconductor material is not formed along the outer circumferential wall and the inner circumferential wall of the successive mounting portion 16c and the outer circumferential wall and inner circumferential wall of the successive mounting portion 16c As shown in FIG. As a result, the physical cutout portions 14c and 14d form a physical cut with a gap between the source-side select gate electrode SG and the drain-side select gate electrode DG to form a physical cut along the source-side select gate electrode SG and the drain- DG can be made non-conductive.

In this embodiment, the one physical cutout portion 14c is formed along the outer circumferential wall of the continuous mount portion 16c, and includes an electrical cutout portion 13e formed on one side wall of the extended portion 16a, 16b are electrically disconnected from each other. The other physical cutting portion 14d is formed along the inner peripheral wall of the continuous mounting portion 16c and includes an electrical cutout portion 13g formed on the other side wall of the extended portion 16a and an electric cut portion 13g formed on the other side wall of the end portion 16b And the electrically cut portion 13h is rendered non-conductive.

As described above, one extended electrode portion 15a and the other extended electrode portion 15b provided on the object also extend from the source-side selection gate electrode SG formed along the first sidewall 11 of the memory gate electrode MG to the memory- An electric cut portion 13e, a physical cut portion 14c, an electric cut portion 13f, 13h, a physical cut portion 14d (a third cutout portion), and a second cut portion 14e on the side wall between the drain side selection gate electrode DG formed along the second sidewall 12 of the electrode MG. And an electrical cut portion 13g are arranged in this order. Thus, in the extended electrode portion 15b as well, by the four electrical cuts 13e, 13f, 13h, 13g and the two physical cuts 14c, 14d, the source side select gate electrode SG and the drain side It is possible to prevent the selective gate electrode DG from becoming conductive.

In addition, since one memory cell forming portion 3a and the other memory cell forming portion 3b adjacent thereto share the drain region WD with one memory cell forming portion 3a, the drain side The second sidewall 12 of the memory gate electrode MG in which the select gate electrode DG is disposed is disposed opposite to the second sidewall 12 of the memory gate electrode MG in one memory cell forming portion 3a.

The memory cell forming portion 3b is also provided with an elongated electrode portion 15c having an end portion 16b disposed on one memory cell forming portion 3a side adjacent to the one electrically cut region ER2 and the physical cut region ER1 And an elongated electrode portion 15d in which an end portion 16b is disposed on the other memory cell forming portion 3c side adjacent to the other electrically cut region ER4 and the physical cut region ER5.

Thereby, between the memory cell forming section 3a of the first row and the memory cell forming section 3b of the second column, the memory cell forming section 3b of the second row in the one electrical cut region ER2 and the physical cut region ER1 The end portion 16b and the continuous mounting portion 16c of the extended electrode portion 15c in the memory cell forming portion 3a in the first row are arranged in the other electrically cut region ER4 and the physical cut region ER5. The end portion 16b of the elongated electrode portion 15b and the continuous mounting portion 16c can be disposed.

As described above, in the nonvolatile semiconductor memory device 1, the end portion 16b of one memory cell forming portion 3a and the other end portion 16b of the other memory cell forming portion 3b Are arranged side by side in the row direction and the two end portions 16b are arranged continuously in the column direction between the adjacent memory cell forming portions 3a and 3b, There is an intensification.

Here, the memory cell forming portion 3a is formed on the memory gate electrode MG of the select gate forming region ER9 and on the extending portion 16a of the electrical cut regions ER2, ER4 formed by extension of the memory gate electrode MG, 16b, respectively. Thus, in the memory cell forming portion 3a, the upper surface of the memory gate electrode MG, the extension portion 16a, and the end portion 16b is prevented from being salicided by the cap film CP in the manufacturing process have.

On the other hand, in the physical cutting regions ER1 and ER5, since the cap film CP is not formed on the continuous mounting portion 16c formed by extending the memory gate electrode MG and the continuous mounting portion 16c is exposed to the outside, The upper surface is salicided, and a memory gate contact MGC having a columnar shape is provided via a silicide layer (not shown) formed on the continuous mounting portion 16c. A memory gate line MGL (FIG. 2) is connected to the memory gate contact MGC, and a predetermined voltage from the memory gate line MGL can be applied. Thus, the voltage of the memory gate line MGL can be applied from the memory gate contact MGC to the memory gate electrode MG of the selection gate formation region ER9 via the extended electrode portions 15a and 15b.

As described above, in the nonvolatile semiconductor memory device 1, although the memory gate electrode MG is covered with the cap film CP in the memory cell region ER3 and the selected gate contact regions ER6 and ER7, A predetermined voltage can be applied to the memory gate electrode MG covered by the cap film CP in the memory cell region ER3 by applying a predetermined voltage to the mounting portion 16c through the memory gate contact MGC.

Incidentally, such a nonvolatile semiconductor memory device 1 can be fabricated by a process such as a film forming process which is a general CMOS (Complementary MOS) manufacturing process, a resist coating process, an exposure developing process, an etching process, an impurity implantation process, The manufacturing method thereof will be omitted here.

(1-5) Action and effect

In the above configuration, in the memory cell forming portion 3a, the memory gate electrode MG of the select gate forming region ER9 in which the source side select gate structure 6a and the drain side select gate structure 5a are opposed to each other is extended The extended electrode portions 15a and 15b are provided in the electrically cut regions ER2 and ER4 and the physical cut regions ER1 and ER5, respectively.

Further, in the memory cell forming portion 3a, between the source-side selection gate electrode SG and the drain-side selection gate electrode DG along the side wall of the extended electrode portions 15a and 15b, (13e, 13f, 13h, 13g) are provided for each of the first and second electrical cut portions 13a, 13b, 13d, and 13c.

As described above, in the memory cell forming portion 3a, four electric cut portions 13a, 13b, 13d, 13c (13e, 13f, 13h, 13g) capable of cutting the source side select gate electrode SG and the drain side select gate electrode DG The positions where the source-side selection gate electrode SG and the drain-side selection gate electrode DG are cut are increased as compared with the prior art, and accordingly, It is possible to prevent the reading malfunction caused by the fluctuation.

The memory cell forming portion 3a also includes a physical cutout portion 14b formed between the electrical cutout portions 13a, 13b, 13d formed along the side wall of the extended electrode portion 15a, ) 14a, and the source-side selection gate electrode SG and the drain-side selection gate electrode DG were brought into non-contact with each other by the physical cut-off portions 14b and 14a to make them non-conductive. As described above, in the memory cell forming portion 3a, the cutting principle for cutting the source-side selection gate electrode SG and the drain-side selection gate electrode DG is a physical cut portion 14b ((a)) different from the electrical cut portions 13a, 13b, 13d, The source side selection gate electrode SG and the drain side selection gate electrode DG can be more reliably cut than when only the electrical cutout portions 13a, 13b, 13d, and 13c are provided.

In this memory cell forming portion 3a, the extended electrode portions 15a and 15b are folded back in the physical cut region ER1 (ER5), and the plurality of electrical cut portions 13a, 13b, 13d, 13c) 13e, 13f, 13h, 13g are arranged in parallel. 13b, 13d, and 13c (13e, 13f, 13h, and 13g) are provided in the extended electrode portions 15a and 15b in the memory cell formation portion 3a, It is possible to prevent the layout area from being extended in the longitudinal direction of the cell forming portion 3a.

(2) A planar layout of the nonvolatile semiconductor memory device according to the second embodiment

In the above-described embodiment, the elongated electrode portion having three or more electrically cut portions is formed as an elongated electrode portion having four electrically cut portions 13a, 13b, 13d, 13c (13e, 13f, 13h, 13g) (15a) and (15b). However, the present invention is not limited thereto, and if three or more electrical cut portions are formed, the elongated electrode portions may have various configurations. 5 showing the same parts as those in FIG. 4 with the same reference numerals being attached thereto. FIG. 5 shows a planar layout of the nonvolatile semiconductor memory device 21 according to the second embodiment. The extended electrode parts 25a, 23b, 23c, 23f, 23e, and 23d, respectively, are provided in each of the first through third embodiments.

In addition, since the memory cell forming portions 22a, 23b, 23c, ... all have the same configuration, one memory cell forming portion 22a will be described below. Since the description of the corresponding portion in Fig. 4 is duplicated, the description of the overlapping portion will be omitted here. In this embodiment, the extended electrode portions 25a and 25b of the memory cell forming portion 22a are formed in an E shape as viewed from above the semiconductor substrate, and electrically disconnected from the terminal of the select gate forming region ER9 (ER4) to the physical cutting region ER1 (ER5) via the first side wall 11 (ER4) of the memory gate electrode MG by dividing the physical cutting region ER1 And the second side wall 12, and extends to the electrically cut region ER2 (ER4).

In practice, the extended electrode portions 25a and 25b are formed by extending an extending portion 26a linearly extending from the memory gate electrode MG of the selective gate forming region ER9 and a straight line And a continuous mounting portion (side wall non-forming portion) 26d that continuously connects the end portions 26b and 26c and the extending portion 26a and the end portions 26b and 26c. (26b, 26c) are arranged in the electrically cut region ER2 (ER4), and the continuous mounting portion 26d which is the folded portion is arranged in the physical cut region ER1 (ER5).

The extended electrode portions 25a and 25b are formed such that one end portion 26b is disposed on the first sidewall 11 side of the memory gate electrode MG and the other end portion 26c is disposed on the side of the memory gate electrode MG, And may be disposed on the side of the second side wall 12 of the electrode MG.

Although the memory gate electrode MG extends from the select gate forming region ER9 as extended electrode portions 25a and 25b in the electrically cut region ER2 (ER4), unlike the select gate forming region ER9, the source side select gate electrode SG and the source- The drain side selection gate electrode DG is not extended and six electric cut portions 23a and 23b are formed on the side walls of the extension electrode portions 25a and 25b instead of the source side selection gate electrode SG and the drain side selection gate electrode DG. 23c, 23f, 23e and 23d are formed.

The electrically cut portions 23a, 23b, 23c, 23f, 23e and 23d all have the same constitution and include the sidewall-shaped intrinsic semiconductor layers Ia and Ib including i-type and the sidewall- Layer OC, and a reverse conducting semiconductor layer OC is formed between the intrinsic semiconductor layers Ia and Ib. The inverse-conducting semiconductor layer OC is formed by a different conductivity type (in this case, p-type) from the source-side selection gate electrode SG and the drain-side selection gate electrode DG as described above.

In this case, in the extended portion 26a of the elongated electrode portions 25a and 25b, one electrical cut portion 23a is formed along one sidewall which is provided continuously and flatly with the first sidewall 11 of the memory gate electrode MG. And another electrical cut-off portion 23d is formed along the other sidewall which is provided continuously and flat with the second sidewall 12 of the memory gate electrode MG. In the memory cell forming portion 22a, for example, an electrical cut portion 23a is formed from the n-type source side selection gate electrode SG as a starting point, and extends from the first sidewall 11 of the memory gate electrode MG to the extending portion 26a A pin junction can be formed along the sidewalls. Similarly, in the memory cell forming portion 22a, the n-type drain side selection gate electrode DG is also used as a starting point on the second side wall 12 side of the memory gate electrode MG, for example, by the electrical cut portion 23d. A pin junction can be formed along the side wall of the extended portion 26a from the second sidewall 12.

One end 26b of the memory gate electrode MG disposed on the side of the first sidewall 11 is formed with one electrical cutout 23b on the sidewall facing the extended portion 26a, Another electrical cut-out portion 23c is formed. One electrical cutout 23e is formed on the side wall opposite to the extended portion 26a on the other end 26c disposed on the side of the second side wall 12 of the memory gate electrode MG, Another electrical cut portion 23f is formed.

This allows the extension electrode 25a and the extension electrode 25b to extend from the source side selection gate electrode SG formed along the first sidewall 11 of the memory gate electrode MG to the second sidewall 12 of the memory gate electrode MG Six electrically cut portions 23a, 23b, 23c, 23f, 23e, and 23d may be formed in this order on the sidewall between the drain-side selection gate electrode DG formed in accordance with the present invention. Thus, three or more reverse-conductivity type semiconductor layers and intrinsic semiconductor layers are provided on the side walls of the elongated electrode portions 25a and 25b.

Foreign bodies are adhered to the electrically cut portions 23a of the extended portions 26a and the successive set portions 26d described later so that the electric cut portions 23b of the end portions 26b The source-side selection gate electrode SG and the drain-side selection gate electrode DG (gate electrode DG) are electrically connected to each other by the pin junction formed by the remaining electrical cutoff portions 23b, 23d, 23f, 23e and 23d, Can be electrically disconnected.

In addition to this configuration, one continuous sidewall of the extended portion 26a and one end 26b of the first sidewall 11 are formed in the continuous mounting portion 26d as the sidewall non- And the side wall of the other end portion 26c on the side of the second side wall 12 is connected to the other side wall of the extended portion 26a by a continuous installation The physical cutting portion 24c is formed on the other inner peripheral wall and the physical cutting portion 24a is formed on the outer peripheral wall continuously provided with the side walls of the end portions 26b and 26c.

These physical cuts 24a, 24b, and 24c are formed on the outer circumferential wall and the inner circumferential wall of the continuous mount portion 26d without forming a conductive layer such as a semiconductor material along the outer circumferential wall and the inner circumferential wall And exposed to the outside. As a result, the physical cutout portions 24a, 24b, and 24c form a physical cut with a gap between the source-side select gate electrode SG and the drain-side select gate electrode DG, The electrode DG can be made non-conductive.

In this embodiment, the first physical cutout 24a is formed along the outer peripheral wall of the continuous attachment portion 26d continuously provided on the side walls of the end portions 26b and 26c, A gap is formed between the electrical cut portion 23c formed on the side wall and the electrical cut portion 23f formed on the side wall of the other end portion 26c so that the electrical cut portions 23c and 23f are not connected to each other. The second physical cutting portion 24b is formed along one inner peripheral wall of the continuous mounting portion 26d continuously provided on the side wall of the extending portion 26a and the side wall of the end portion 26b, A gap is formed between one electrical cut portion 23a formed on the side wall of the end portion 26b and the electrical cut portion 23b formed on the side wall of the end portion 26b so that the electrical cut portions 23a and 23b are not connected to each other. The third physical cutting portion 24c is formed along the other inner peripheral wall of the continuous mounting portion 26d continuously provided on the side wall of the extending portion 26a and the side wall of the end portion 26c, A gap is formed between the other electrical cut portion 23d formed on the side wall and the electrical cut portion 23e formed on the side wall of the end portion 26c so that the electrical cut portions 23d and 23e are not connected to each other.

Thus, the extended electrode portions 25a and 25b extend from the source-side selection gate electrode SG formed along the first sidewall 11 of the memory gate electrode MG to the second sidewall 12 of the memory gate electrode MG An electrical cut portion 23a, a physical cut portion 24b, electrical cut portions 23b and 23c, a physical cut portion 24a, electrical cut portions 23f and 23e, and a physical (not shown) The cut portion 24c and the electrical cut portion 23d can be arranged in this order. In this way, the extended electrode portion 15a is electrically connected to the source-side selection gate electrode 14a by the six electrical cut portions 23a, 23b, 23c, 23f, 23e, 23d and the three physical cut portions 24b, 24a, 24c. SG and the drain side selection gate electrode DG can be prevented from becoming conductive.

In this configuration, the memory cell forming portion 22a also includes six electrically cut portions 23a, 23b, 23c, 23f, 23e, 23d capable of cutting the source side select gate electrode SG and the drain side select gate electrode DG 25b are provided along the sidewalls of the mounting electrode portions 25a and 25b and the portion for cutting the source side selection gate electrode SG and the drain side selection gate electrode DG is increased as compared with the conventional one, It is possible to prevent the reading malfunction caused by the fluctuation.

The memory cell forming portion 22a also includes electrical cut portions 23a and 23b formed along the side walls of the elongated electrode portions 25a and 25b and between the electrically cut portions 23c and 23f and electrically cut portions 23e and 23d The physical cutout portions 24b, 24a, and 24c are formed between the source-side select gate electrode SG and the drain-side select gate 24b, 24a, and 24c, The electrode DG was brought into a non-contact state to make it into a non-conductive state. As described above, in the memory cell forming portion 22a, the cutting principle for cutting the source-side selection gate electrode SG and the drain-side selection gate electrode DG is different from the electrical cutting portions 23a, 23b, 23c, 23f, 23e, Side selection gate electrode SG and the drain-side selection gate electrode DG are more reliably cut than in the case where only the electrical cut-off portions 23a, 23b, 23c, 23f, 23e and 23d are provided, .

Also in the memory cell forming portion 22a, the extended electrode portions 25a and 25b are folded back in the physical cut region ER1 (ER5), and the plurality of electrical cut portions 23a, 23b, 23c, 23f, 23e and 23d are all arranged in parallel, it is possible to suppress the extension of the layout area in the longitudinal direction of the memory cell forming portion 22a.

(3) Planar layout of the nonvolatile semiconductor memory device according to the third embodiment

The extended electrode portions 15a and 15b are provided as a part of the configuration of the memory cell forming portions 3a to 3c and the memory cell forming portions 3a to 3c The present invention is not limited to this. For example, as shown in Fig. 6 with the same reference numerals attached to the corresponding portions in Fig. 4, the memory cell forming portion 32a 32b, 32c, ... are provided separately from the memory cells 32a, 32b, 32c, ..., and the memory cell forming portions 32a, 32b, 32c, The nonvolatile semiconductor memory device 31 may be used.

In this case, the memory cell forming portions 32a, 32b, 32c are formed by the source side select gate structures 6a, 6b, 6c and the drain side select gate structures 4a, 4b, 4c, And a select gate formation region ER9 in which the structures 5a and 5b and 5c are arranged opposite to each other. A memory gate electrode MG extending in the row direction is provided in each of the memory gate structures 4a, 4b and 4c of the memory cell formation portions 32a, 32b and 32c in the selection gate formation region ER9, A cap film CP is formed on the electrode MG.

In this embodiment, the memory cell forming portion 32a in the first row and the memory cell forming portion 32b in the second row adjacent to the memory cell forming portion 32a in the first row are formed in the drain region The memory cells 2a and 2b of the memory cell forming portion 32a of the first row and the memory cells 2d and 2e of the memory cell forming portion 32b of the second row share the WD, The same bit voltage can be uniformly applied through the drain region WD. As described above, the memory cell forming portion 32b in the second row adjacent to the memory cell forming portion 32a in the first row shares the drain region WD with the memory cell forming portion 32a in the first row The second sidewall 12 of the memory gate electrode MG in which the drain side selection gate electrode DG is disposed is opposed to the second sidewall 12 of the memory gate electrode MG in the memory cell formation portion 32a of the first row, Respectively.

Each memory gate electrode MG formed in these memory cell formation portions 32a, 32b, 32c, ... is electrically disconnected from the select gate formation region ER9 by the electrically cut region ER2 (ER4) and the physical cut region ER1 (ER5) And the elongated electrode portions 35a and 35b are formed in the electrically cut region ER2 (ER4) and the physical cut region ER1 (ER5). In this embodiment, the extended electrode portions 35a and 35b are formed in a comb shape when viewed from above the semiconductor substrate, and the memory gate electrodes MG of the memory cell forming portions 32a, 32b, 32c, And a linear end portion 36b formed at a lateral outer position of the extended portion 36a are arranged in a column direction in which the memory cell forming portions 32a, 32b, 32c, And can be arranged in sequence alternately. The extended portion 36a and the end portion 36b are formed in the electrically cut regions ER2 and ER4 and are continuously provided by continuous mounting portions (side wall non-forming portions) 36c formed in the physical cut regions ER1 and ER5.

Here, the extended electrode portions 35a and 35b will be described with attention to the memory cell forming portion 32b in the second row. The memory cell forming portion 32b in the second row is formed such that the second sidewall 12 of the memory gate electrode MG in which the drain side select gate electrode DG is formed is connected to the drain side select The second side wall 12 of the memory gate electrode MG having the gate electrode formed therein and the inner side wall of the extending electrode portions 35a and 35b.

In this embodiment, the extended electrode portions 35a and 35b are formed in the memory cell forming portion 32a of the first row from the second side wall 12 of the memory gate electrode MG in the memory cell forming portion 32b of the second row, Four electrical cut portions 33a, 33b, 33c, and 33d are formed in this order along the side wall between the first side wall 12 and the memory gate electrode MG of the first gate electrode 32a. The extended electrode portions 35a and 35b are formed in such a manner that the side wall of the extended portion 36a formed flat with the second sidewall 12 of the memory gate electrode MG in the memory cell forming portion 32b of the second row The electrical cut portion 33a is formed along the side wall of the extended portion 36a formed flat with the second sidewall 12 of the memory gate electrode MG in the memory cell forming portion 32a in the first row, (33d) are formed.

In the end portion 36b of the extending electrode portions 35a and 35b extending in the row direction between the memory cell forming portion 32a of the first column and the memory cell forming portion 32b of the second column, One electrical cutout portion 33c is formed along the side wall disposed on the cell formation portion 32a side and another electrical cutoff portion 33b is formed along the side wall disposed on the memory cell formation portion 32b side of the second row have. The second sidewall 12 of the memory gate electrode MG in the memory cell forming portion 32a in the second row is electrically connected to the second sidewall 12b of the memory gate electrode MG in the memory cell forming portion 32a in the first row Four electrically cut portions 33a, 33b, 33c, and 33d along the side wall may be formed in this order on the elongated electrode portions 35a and 35b that are continuously provided up to the electrodes 12a to 12d. Thereby, three or more reverse-conductivity type semiconductor layers and an intrinsic semiconductor layer are provided on the side walls of the elongated electrode portions 35a and 35b.

In addition to such a configuration, in the continuous mounting portion 36c in the physical cutting area ER1, for example, a side wall of the extended portion 36a continuously provided with the memory cell forming portion 32b of the second row, A physical cutout portion 34c is formed on one inner peripheral wall that continuously provides the side wall of the end portion 36b between the cell forming portion 32b and the memory cell forming portion 32a in the first row. In the continuous mounting portion 36c in the physical cutting area ER1, for example, the side wall of the extended portion 36a continuously provided with the memory cell forming portion 32a in the first row and the side wall of the memory cell forming portion 32a ) And the other inner circumferential wall that continuously connects the side wall of the end portion 36b between the second row and the memory cell forming portion 32b of the second row is similarly formed with the physical cut portion 34b.

These physical cutting portions 34b and 34c have a structure in which the inner peripheral wall of the continuous mounting portion 36c is exposed to the outside without forming a conductive layer such as a semiconductor material along the inner peripheral wall of the continuous mounting portion 36c . As a result, the physical cutout portions 34b and 34c are electrically connected to the drain side selection gate electrode DG in the memory cell formation portion 32a in the first row and the drain side selection gate electrode DG in the memory cell formation portion 32b in the second row, A physical cut is formed with a gap between the electrodes DG so that the drain side selection gate electrode DG of the memory cell formation portion 32a of the first row and the drain side selection gate electrode DG of the memory cell formation portion 32b of the second row Non-conductive state.

As described above, the drain-side selection gate electrode DG in the memory cell formation portion 32b in the second row is provided with the drain side (the side in the memory cell formation portion 32a in the first row) The electrical cut portion 33a, the physical cut portion 34c, the electrical cut portions 33b and 33c, the physical cut portion 34b and the electrical cut portion 33d can be arranged in this order on the sidewall between the selective gate electrode DG have. The elongated electrode portions 35a and 35b are electrically connected to the memory cell forming portions 32a and 32b of the first row by the four electrical cut portions 33a, 33b, 33c, and 33d and the two physical cut portions 34b and 34c, And the drain side selection gate electrode DG of the memory cell formation portion 32b of the second row can be prevented from becoming conductive.

The extended electrode portions 35a and 35b are formed such that the end portions 36b extend from the continuous mounting portions 36c of the physical cut regions ER1 and ER5 toward the electrically cut regions ER2 and ER4, It is possible to prevent the electrical cut regions ER2 and ER4 from being extended in the lengthwise direction of the memory cell forming portions 32a and 32b by the end portions 36b by disposing the end portions 36b in the region between the end portions 36a and 32b can do.

Incidentally, the memory cell forming portion 32b in the second row and the memory cell forming portion 32c in the third row adjacent to the memory cell forming portion 32b in the second row share the source region WS formed in the well W And the same source voltage is applied to the memory cells 2d, 2e and 2f of the memory cell forming portion 32b of the second row and the memory cells 2g, 2h and 2i of the memory cell forming portion 32c of the third row It can apply uniformly. As described above, the memory cell formation portion 32b in the second row adjacent to the memory cell formation portion 32c in the third row shares the source region WS with the memory cell formation portion 32c in the third row The first sidewall 11 of the memory gate electrode MG in which the source side selection gate electrode SG is disposed is opposed to the first sidewall 11 of the memory gate electrode MG in the memory cell formation portion 32c in the third row, Respectively.

As a result, the memory cell formation portion 32b of the second row is formed so that the first sidewall 11 of the memory gate electrode MG on which the source-side selection gate electrode SG is formed is arranged in the memory cell formation portion 32c in the third row The first side wall 11 of the memory gate electrode MG in which the source side selection gate electrode SG is formed and the side wall on the inner side of the extension electrode portions 35a and 35b.

In this embodiment, from the first sidewall 11 of the memory gate electrode MG in the memory cell formation portion 32b in the second row to the memory electrode formation portion 32b in the third row, Four electrical cut portions 33e, 33f, 33g, and 33h are formed in this order along the side wall between the first side wall 11 and the memory gate electrode MG in the first side wall 32c. The extended electrode portions 35a and 35b are formed so that the side wall of the extended portion 36a formed flat with the first sidewall 11 of the memory gate electrode MG in the memory cell forming portion 32b of the second row The electrical cut portion 33e is formed and along the side wall of the extended portion 36a formed flat with the first sidewall 11 of the memory gate electrode MG in the memory cell forming portion 32c in the third row, 33h.

In the end portions 36b of the extending electrode portions 35a and 35b extending in the row direction between the memory cell forming portion 32b of the second column and the memory cell forming portion 32c of the third column, One electrical cutout portion 33f is formed along the side wall disposed on the side of the memory cell forming portion 32b and another electrical cutout portion 33g is formed along the side wall disposed on the side of the memory cell forming portion 32c on the third row Respectively. As described above, the first sidewall 11 of the memory gate electrode MG in the memory cell forming portion 32b in the second row, the first sidewall 11b of the memory gate electrode MG in the memory cell forming portion 32c in the third row Four electrical cut portions 33e, 33f, 33g and 33h can be formed along the side wall in this order on the elongated electrode portions 35a and 35b continuously provided up to the electrodes 11a to 11d.

In addition to such a configuration, in the continuous mounting portion 36c in the physical cutting area ER1, for example, a side wall of the extended portion 36a continuously provided with the memory cell forming portion 32b of the second row, A physical cutout portion 34e is formed on one inner peripheral wall for continuously providing the side wall of the end portion 36b between the cell forming portion 32b and the memory cell forming portion 32c in the third row. In the continuous mounting portion 36c in the physical cutting area ER1, for example, the sidewall of the extended portion 36a continuously provided with the memory cell forming portion 32c in the third row and the side wall of the extending portion 36a provided in the memory cell forming portion 32c ) And the other inner circumferential wall in which the side wall of the end portion 36b between the memory cell forming portion 32b in the second row and the side wall of the memory cell forming portion 32b is continuously provided.

These physical cut portions 34e and 34d also have a structure in which the inner peripheral wall of the continuous attachment portion 36c is exposed to the outside without forming a conductive layer such as a semiconductor material along the inner peripheral wall of the continuous attachment portion 36c . As a result, the physical cutout portions 34e and 34d are electrically connected to the source side select gate electrode SG in the memory cell forming portion 32b in the second row and the source side select gate electrode SG in the memory cell forming portion 32c in the third row, The source-side selection gate electrode SG of the memory cell formation portion 32b of the second row and the source-side selection gate electrode SG of the memory cell formation portion 32c of the third row are formed so as to have a gap between the electrodes SG Non-conductive state.

As described above, the source-side selection gate electrode SG in the memory cell formation portion 32b in the second row and the source-side selection gate electrode SG in the memory cell formation portion 32c in the third row are formed in the extended electrode portions 35a and 35b, The electric cut portion 33e, the physical cut portion 34e, the electric cut portions 33f and 33g, the physical cut portion 34d and the electric cut portion 33h can be arranged in this order have. The extended electrode portions 35a and 35b are electrically connected to the memory cell forming portion 32b of the second row by the four electrical cut portions 33e, 33f, 33g, and 33h and the two physical cut portions 34e and 34d, Side select gate electrode SG of the third row and the source-side select gate electrode SG of the memory cell forming portion 32c of the third row can be prevented from becoming conductive.

The nonvolatile semiconductor memory device 31 includes the memory gate electrodes MG of the memory cell forming portions 32a, 32b, 32c, ..., the electrically cut regions ER2 formed by extending the memory gate electrodes MG, The cap film CP is formed on the extended portion 36a in the ER4 and on the end portion 36b in the electrically cut region ER2 and ER4 respectively and in the manufacturing process, So that the upper surface of the end portion 36a and the end portion 36b can be prevented from being salicided. On the other hand, in the physical cutting regions ER1 and ER5, since the cap film CP is not formed on the continuous mounting portion 36c formed by extending the memory gate electrode MG and the continuous mounting portion 36c is exposed to the outside, And the memory gate contact MGC of the main phase is provided via a silicide layer (not shown) formed on the continuous mounting portion 36c.

In the nonvolatile semiconductor memory device 31 as described above, four electrical cutoff portions 33a, 33b, 33c, and 33d are provided to cut off the drain-side select gate electrodes DG of the adjacent memory cell forming portions 32a and 32b, Side selection gate electrodes DG are arranged to extend along one sidewall of the elongated electrode portions 35a and 35b and the portion where the drain-side select gate electrodes DG are cut off is increased as compared with the prior art. It is possible to prevent a reading malfunction that occurs.

In this nonvolatile semiconductor memory device 31, the four electric cut portions 33e, 33f, 33g, and 33h capable of cutting the source side select gate electrodes SG of the adjacent memory cell forming portions 32b and 32c are extended The number of the source-side selection gate electrodes SG is increased along the other side walls of the electrode portions 35a and 35b and the number of the source-side selection gate electrodes SG is increased as compared with the prior art. As a result, Can be prevented.

For example, between the adjacent memory cell forming portions 32a and 32b, electrical cut portions 33a and 33b formed along the side walls of the elongated electrode portions 35a and 35b, and between the electrically cut portions 33c and 33d The physical cut portions 34c and 34b in which the sidewall-shaped semiconductor material is not formed are provided and the drain-side selection gate electrodes DG are made non-contact by the two physical cut portions 34c and 34b to be in the non-conductive state . The physical cutting portions 34c and 34b different from the electrical cutting portions 33a, 33b, 33c and 33d are separately provided between the memory cell forming portions 32a and 32b as well as between the drain side selection gate electrodes DG. The drain side selection gate electrodes DG can be cut more reliably than in the case where only the electrical cutoff portions 33a, 33b, 33c and 33d are provided. Similarly, between the adjacent memory cell forming portions 32b and 32c, the cutting principle for cutting the source side selection gate electrodes SG is also the physical cut portions 34e and 34d which are different from the electrical cut portions 33e, 33f, 33g, and 33h The source side selection gate electrodes SG can be more reliably cut than when only the electrically cut portions 33e, 33f, 33g, and 33h are provided.

The elongated electrode portions 35a and 35b are folded back to the electrically cut region ER2 (ER4) side in the physical cut region ER1 (ER5), and an end portion 36b is formed between the adjacent memory cell forming portions 32a and 32b 23b, 23c, 23f, 23e, and 23d are all electrically disconnected from each other by the extended portion 36a and the end portion 36b disposed in the electrically cut region ER2 (ER4) ER4). &Lt; / RTI &gt; Thus, in the nonvolatile semiconductor memory device 31, it is possible to prevent the electrically cut region ER2 (ER4) from being extended in the longitudinal direction of the memory cell forming portion 32a by providing the end portion 36b, High integration can be realized.

In the nonvolatile semiconductor memory device 31, due to manufacturing defects, for example, the first side wall 11 of each memory gate electrode MG is connected to the adjacent memory cell forming portions 32b, 32c The source side selection gate electrodes SG of the adjacent memory cell formation portions 32b and 32c can be electrically connected to each other when foreign matter remains along the side wall of the installed extension electrode portion 35a. In this case, in the nonvolatile semiconductor memory device 31, since the same voltage is applied to the source-side selection gate electrode SG during the data read operation, the source-side selection gate electrode SG of the memory cell formation portions 32b and 32c It is possible to prevent the voltage fluctuation at the source-side selection gate electrode SG and the voltage fluctuation at the drain-side selection gate electrode DG due to the short defects during the data read operation, even if they are electrically connected to each other.

In the nonvolatile semiconductor memory device 31, due to manufacturing defects, for example, the second side wall 12 of each memory gate electrode MG is connected to the adjacent memory cell forming portions 32a, 32b The drain side selection gate electrodes DG of the adjacent memory cell formation portions 32a and 32b can be electrically connected to each other when foreign matter remains along the side wall of the installed extension electrode portion 35a. In this case, the nonvolatile semiconductor memory device 31 can electrically connect the same type of drain-side selection gate electrodes DG, which are likely to be applied with the same voltage at the time of data read operation, The probability of occurrence of the voltage fluctuation at the drain-side selection gate electrode DG can be reduced.

(4) A planar layout of the nonvolatile semiconductor memory device according to the fourth embodiment

In the third embodiment described above, the nonvolatile semiconductor memory device 31 in which the memory cell forming portions 32a, 32b, 32c, ... are provided continuously in the physical cut regions ER1, ER5 has been described. However, 7, the same reference numerals are attached to the corresponding portions in FIG. 4, and the continuous mounting regions ER10 and ER11 are provided separately from the physical cut regions ER1 and ER5, and the adjacent memory cell forming portions 42a and 42b are provided, Volatile semiconductor storage device 41 that is continuously provided in the continuous installation areas ER10 and ER11.

In this case, the memory cell formation portions 42a and 42b are formed by the source side selection gate structures 6a and 6b and the drain side selection gate structures 5a and 5b (5b) via the memory gate structures 4a and 4b ) Are arranged opposite to each other. The memory gate structures 4a and 4b of the memory cell formation portions 42a and 42b are provided with a linear memory gate electrode MG extending in the row direction in the selection gate formation region ER9, A cap film CP is formed on the MG.

In addition to this structure, the nonvolatile semiconductor memory device 41 is provided with the continuous mounting regions ER10 and ER11 adjacent to the selective gate forming region ER9, and the electrically disconnecting regions ER10 A physical cut region ER1 (ER5) is provided via ER2 (ER4). In this case, the memory gate electrode MG is extended to the continuous mounting region ER10 (ER11), the electrically cut region ER2 (ER4) and the physical cut region ER1 (ER5), and the extended electrode portion 45a and 45b.

The memory cells 2d, 2e, and 2f of one memory cell forming portion 42a share the source region WS formed in the well W and the memory cells 2d, 2e, and 2f of the one memory cell forming portion 42a share the source region WS formed in the well W. [ The same source voltage can be uniformly applied to the memory cells 2g, 2h, and 2i of the memory cell formation portion 42b from the source region WS. The memory cell forming portions 42a and 42bb adjacent to each other are arranged such that the first sidewalls 11 of the memory gate electrode MG are opposed to each other and the sidewall- SG are opposed to each other.

In addition to this configuration, the memory cell forming portions 42a and 42b adjacent to each other are continuously provided with the end portions of the memory gate electrode MG by the extended electrode portions 45a and 45b in the continuous mounting regions ER10 and ER11. The extended electrode portions 45a and 45b are formed in an E shape as viewed from above the semiconductor substrate and are provided with continuous mounting regions ER10 and ER11, electrically cut regions ER2 and ER4, It is installed in the physical cutting areas ER1 and ER5 as management targets. In this case, the extended electrode portions 45a and 45b are provided in the continuous mounting regions ER10 and ER11 and the branching continuous mounting portions 46a and 46b for continuously connecting the memory gate electrodes MG of the memory cell forming portions 43a and 42b, Extended portions 46b and 46f extending in the longitudinal direction of the memory gate electrode MG from the branch continuous mounting portion 46a and electrically connected to the electrically cut regions ER2 and ER4 in the electrically cut regions ER2 and ER4, And an end portion 46d which is provided between the extended portions 46b and 46f and is provided in the physical cutting regions ER1 and ER5 and which is provided at the distal ends of the extended portions 46b and 46f and the end portion 46d And non-side wall non-forming portions 46c, 46g, and 46e.

The memory cell forming portions 42a and 42b adjacent to each other are arranged on the first sidewall 11 of the memory gate electrode MG in one memory cell forming portion 42a and in the other memory cell forming portion 42b The first sidewall 11 of the memory gate electrode MG in the continuous mounting regions ER10 and ER11 is continuously provided by the side wall 47a of the branch continuous mounting portion 46a. The branch continuous mounting portion 46a has a sidewall-shaped semiconductor layer 11a formed along the sidewall 47a. The source-side select gate electrode SG in one memory cell forming portion 42a, The source side selection gate electrode SG in the other memory cell formation portion 42b is continuously provided by the semiconductor layer 11a.

The branch continuous mounting portion 46a is provided with a selective gate contact forming portion Ca having a wide width and provided with a source side selection gate contact SGC at a predetermined position of the semiconductor layer 11a. The selective gate contact forming portion Ca is formed with a recessed portion that is placed on the branch successive mounting portion 46a and a flat surface portion whose surface is formed in a plane shape along the semiconductor substrate, ) Is connected to the planar portion of the pillar-shaped source side selection gate contact SGC. Thus, in the source side selection gate electrode SG having a narrow and inclined side wall shape, a predetermined voltage from the source side selection gate line SGL is applied through the source side selection gate contact SGC and the selection gate contact formation portion Ca .

In the case of this embodiment, the planar portions are arranged in the select gate contact regions ER6 and ER7, and the settling portions are arranged in the successive mounting regions ER10 and ER11. Incidentally, in the above-described embodiment, a case has been described in which the selective gate contact forming portion Ca is provided in the semiconductor layer 11a in the branch successive mounting portion 46a. However, the present invention is not limited to this, The selection gate contact forming portion Ca may be provided in the source side selection gate electrode SG in the contact regions ER6 and ER7.

A sidewall-shaped semiconductor layer 11b is formed in each of the C-shaped sidewalls 47b and 47c opposite to the sidewall 47a provided with the selective gate contact forming portion Ca, . The semiconductor layer 11b is formed so as to extend from the side of the inverted U-shaped side wall 46a of the branch continuous mounting portion 46a to the side of the memory cell forming portion 42a or 42b when the source side select gate electrode SG or the drain side select gate electrode DG is formed. (47b, 47c).

The memory cell forming portions 42a and 42b are provided with the second side wall 12 opposed to the first side wall 11 of the memory gate electrode MG and also on the drain region WD side of the well W Side gate select gate electrode DG is formed. For example, the memory cell forming portion 42a shares a drain region WD with a memory cell forming portion (not shown) adjacent to the memory cell forming portion 42a, and has the same bit voltage as the memory cell 2d of one memory cell forming portion 42a Can also be applied to one memory cell of an adjacent memory cell forming section, not shown.

The source side selection gate electrode SG and the drain side selection gate electrode DG are not formed on the sidewall of the extension portions 46b and 46f and the end portion 46d provided in the electrical cut region ER2 and ER4, Electrical cut portions 43a, 43b, 43c, 43f, 43e and 43d are formed. The electrically cut portions 43a, 43b, 43c, 43f, 43e and 43d all have the same constitution and include the sidewall-shaped intrinsic semiconductor layers Ia and Ib including i-type and the sidewall- Layer OC, and a reverse conducting semiconductor layer OC is formed between the intrinsic semiconductor layers Ia and Ib. In addition, the inversing type semiconductor layer OC is formed by a conductive type (p type in this case) different from the source side selection gate electrode SG and the drain side selection gate electrode DG.

One extended portion 46b of the extended electrode portions 45a and 45b is provided with a plurality of first and second side walls 12a and 12b which are continuous and flat with the second side wall 12 of the memory gate electrode MG in one memory cell forming portion 42a One electrical cut-away portion 43a is formed along the side wall of the one side wall, and another electrical cut-away portion 43b is formed along the other side wall which faces the one side wall. In one memory cell forming portion 42a, for example, an electric cutoff portion 43a is formed in a direction from the second side wall 12 of the memory gate electrode MG to the side A pin joint can be formed along the side wall of the continuous mounting portion 46a and the extending portion 46b.

Another extended portion 46f of the elongated electrode portions 45a and 45b is provided with a plurality of memory cells each of which is provided continuously and flatly with the second side wall 12 of the memory gate electrode MG in the other memory cell forming portion 42b One electrical cutout 43f is formed along the side wall and another electrical cutout 43e is formed along the other sidewall facing the one sidewall. In the other memory cell forming portion 42b, for example, an electrical cutoff portion 43f is formed from the second sidewall 12 of the memory gate electrode MG, starting from the n-type drain side selection gate electrode DG, A pin joint can be formed along the side wall of the mounting portion 46a and the extending portion 46f.

The end portions 46d of the elongated electrode portions 45a and 45b extend linearly from the branch continuous mounting portion 46a along the longitudinal direction of the extending portions 46b and 46f, 46f. One electrical cutout 43c is formed on the side wall opposing one extension 46b and another electrical cutout 43d is formed on the side wall opposite to the other extension 46f. . Thus, from the drain side selection gate electrode DG formed along the second sidewall 12 of the memory gate electrode MG in one memory cell formation portion 42a, the extended electrode portions 45a, 43b, 43c, and 43c are formed on the sidewalls between the drain-side selection gate electrode DG formed along the second sidewall 12 of the memory gate electrode MG in the other memory cell formation portion 42b. 43d, 43e, 43f may be formed in this order. Thus, three or more reverse-conductivity type semiconductor layers and an intrinsic semiconductor layer are provided on the side walls of the elongated electrode portions 45a and 45b.

This allows foreign objects to adhere to the sidewall non-forming portion 46c of the electrical cutout portions 43a and 43b of one extended portion 46b and the later-described extended portion 46b, for example, The electrical cutout portions 43a and 43b of the edge portion selection gate electrode DG in the portion 42a through the semiconductor layer 11b of the side wall non-formation portion 46c and the side wall 47b 43c can be electrically connected to each other by the foreign matter, a pin junction can be formed along the side wall of the end portion 16b by the electrically cut portion 43c.

In addition to this configuration, the physical cut portions 44a, 44b, and 44c are formed in the side wall non-forming portions 46c, 46e, and 46g in the physical cut region ER1. These physical cuts 44a, 44b and 44c are formed by forming the side wall non-forming portions 46c, 46e and 46g without forming a conductive layer such as a semiconductor material along the side walls of the side wall non-forming portions 46c, 46e and 46g, And the side wall of the semiconductor device is exposed to the outside. As a result, the physical cutout portions 44a, 44b, and 44c are electrically connected to the drain side select gate electrode DG in one memory cell forming portion 42a and the drain side select gate electrode DG in the other memory cell forming portion 42b, It is possible to form a physical cut with a gap between the drain-side selection gate electrodes DG, thereby making the drain-side selection gate electrodes DG nonconductive.

As described above, from the drain-side selection gate electrode DG formed along the second sidewall 12 of the memory gate electrode MG in one memory cell formation portion 42a to the extended electrode portions 45a and 45b, An electrical cutout 43a, a physical cutout 44a, and a cutout 44b are formed on the sidewall between the memory cell forming portion 42b and the drain-side select gate electrode DG formed along the second sidewall 12 of the memory gate electrode MG. The electrical cut portions 43b and 43c, the physical cut portion 44b, the electrical cut portions 43d and 43e, the physical cut portion 44c and the electrical cut portion 43f may be arranged in this order. In this manner, the elongated electrode portions 45a and 45b are electrically connected by the six electrical cut portions 43a, 43b, 43c, 43d, 43e, and 43f and the three physical cut portions 44a, 44b, and 44c, It is possible to prevent the drain-side selection gate electrodes DG from becoming conductive.

In the above configuration, in the nonvolatile semiconductor memory device 41, the drain-side selection gate electrode DG in one memory cell formation portion 42a and the drain-side selection gate electrode DG in the other memory cell formation portion 42b, The six electrical cut portions 43a, 43b, 43c, 43d, 43e and 43f capable of cutting the electrode DG are provided along the side wall of the elongated electrode portions 45a and 45b and the drain side select gate electrodes DG are cut It is possible to prevent an erroneous reading operation caused by the voltage fluctuation at the time of data reading operation as compared with the conventional method.

The elongated electrode portions 45a and 45b are provided between the electrically cut portions 43a and 43b formed along the side wall and between the electrically cut portions 43c and 43d and between the electrically cut portions 43e and 43f, The physical cutout portions 44a, 44b and 44c on which the semiconductor material is not formed are provided and the drain side selection gate electrodes DG are made noncontact with the three physical cutouts 44a, 44b and 44c to make them non-conductive. As described above, in the adjacent memory cell formation portions 42a and 42b, the cutting principle for cutting the drain side selection gate electrodes DG is different from the electrical cutting portions 43a, 43b, 43c, 43d, 43e, and 43f, 44b and 44c are provided separately from each other so that the drain side selection gate electrodes DG can be more reliably cut than when only the electrical cutoff portions 43a, 43b, 43c, 43d, 43e and 43f are provided.

Also in the adjacent memory cell formation portions 42a and 42b as described above, the extended electrode portions 45a and 45b are folded back in the physical cut region ER1 (ER5), and the end portions 46d are formed in the electrically cut region ER2 (ER4) 43b, 43c, 43d, 43e, and 43f are formed in the electrically cut region ER2 (ER4) by the end portions 46d and the extension portions 46b and 46f, 43f are arranged in parallel. Thereby, in the nonvolatile semiconductor memory device 41, since the end portion 46d is not arranged in the extending portions 46b and 46f in series, the electrically cut regions ER2 and ER4 are formed in the memory cell forming portions 42a and 42b It can be prevented from being extended in the longitudinal direction.

In the nonvolatile semiconductor memory device 41, due to a manufacturing defect, for example, an extension extending continuously from the second sidewall 12 of the memory gate electrode MG between the adjacent memory cell formation portions 42a and 42b The drain side selection gate electrodes DG of the adjacent memory cell formation portions 42a and 42b can be electrically connected even when foreign matter remains along the side wall of the installation electrode portion 45a. In this case, the nonvolatile semiconductor memory device 41 can electrically connect the drain-side select gate electrodes DG of the same type, which are likely to be applied with the same voltage during data read operation, The probability of occurrence of the voltage fluctuation at the drain-side selection gate electrode DG can be reduced.

In the third embodiment described above, the electrical connection between the first select gate electrode of one memory cell forming section and the first select gate electrode or the second select gate electrode in the other memory cell forming section is An electric cutoff section for cutting off the electrical connection between the drain side selection gate electrode DG of one memory cell formation section 42a and the drain side selection gate electrode DG of the other memory cell formation section 42b, The source side selection gate electrode of one memory cell formation portion and the source side selection gate electrode of the other memory cell formation portion are formed in the same manner as the source side selection gate electrodes 43a, 43b, 43c, 43d, 43e, The electrical cutoff portion for cutting off the electrical connection of the side select gate electrode may be applied. In this case, the drain-side selection gate electrode DG and the source-side selection gate electrode SG shown in FIG. 7 are replaced with each other in the memory cell formation portion other than one memory cell formation portion.

In another embodiment, an electric cutoff portion for cutting off the electrical connection between the drain-side selection gate electrode of one memory cell formation portion and the source-side selection gate electrode in another memory cell formation portion may be applied. In this case, the drain side selection gate electrode DG of the other memory cell formation portion 42b shown in Fig. 7 is connected to the source side selection gate 42b of the memory cell formation portion 42b, Electrode SG.

(5) Another embodiment

The present invention is not limited to the present embodiment, and various modifications can be made within the scope of the present invention. For example, various voltage values may be applied to voltage values of respective parts. In the first and second embodiments described above, a case has been described in which the source-side selection gate electrode SG is used as the first selection gate electrode formed on the first sidewall of the memory gate electrode. However, the present invention is not limited thereto And the drain side selection gate electrode may be formed as the first selection gate electrode on the first sidewall of the memory gate electrode. In this case, the second selection gate electrode formed on the second sidewall of the memory gate electrode becomes the source-side selection gate electrode.

13b, 13d, and 13c (13e, 13f, 13h, and 13g) forming a pin junction with the drain-side selection gate electrode DG and the source-side selection gate electrode SG as starting points, (23a, 23b, 23c, 23f, 23e, 23d, 33a, 33b, 33c, 33d, 43a, 43b, 43c, 43d, 43e and 43f) are provided. However, the present invention is not limited thereto The nin junction structure, the npn junction structure, or the pnp junction structure may be provided with the drain-side selection gate electrode DG or the source-side selection gate electrode SG as the starting point or the electrical cutoff portion alone do. That is, at least three of the inversely conductive semiconductor layers or the intrinsic semiconductor layers having different conductivity types from the first select gate electrode and the second select gate electrode are provided on the side wall of the extended electrode portion extended from the memory gate electrode It is good. At this time, it is preferable that a physical cut portion in which the semiconductor layer is not formed on the sidewall of the extending electrode portion is formed between the adjacent inductance-type semiconductor layers or between the adjacent intrinsic semiconductor layers.

Although the physical cutting regions ER1 and ER5 are formed in the first, second, third, and fourth embodiments described above, the present invention is not limited thereto, and the physical cutting regions ER1 and ER5 may not be formed, Only the cut regions ER2 and ER4 may be formed.

15b, 15c, 15d, 25a, 25b, 35a, 35b, 45a, 45b of the inverted U-shape, the E-shape, and the comb-like shape when viewed from above the semiconductor substrate in the above- However, the present invention is not limited to this. For example, the present invention is not limited to this. For example, it may be an F-, H-, J-, K-, L-, M-, N-, T-, An extended electrode portion including various shapes such as a W-shape, a Y-shape, a Z-shape, or the like may be applied.

In the above-described embodiment, the memory gate structure 4a for forming an N-type transistor structure and the drain-side selection gate structure 5a for forming an N-type MOS transistor structure are formed by using the P- And the source side selection gate structure 6a for forming the N-type MOS transistor structure are similarly provided. However, the present invention is not limited to this, and the N-type well may be used to form the P- A drain-side select gate structure for forming a P-type MOS transistor structure, and a source-side select gate structure for forming a P-type MOS transistor structure may be provided. In this case, the memory cell 2a described in the above-described embodiment has a memory gate structure, a drain side selection gate structure, a source side selection gate structure, a bit line, a source line, and the like in that the polarities of N- Each applied voltage also changes accordingly.

In the above-described embodiment, the case has been described in which, for example, data is written by injecting charge into the charge storage layer EC of the memory cell 2a and data is erased by drawing out the charge of the charge storage layer EC The present invention is not limited to this. Conversely, data may be written by drawing out the charge in the charge storage layer EC of the memory cell 2a, and data may be erased by injecting charge into the charge storage layer EC.

In the above-described embodiment, the cap film formed on the top of the memory gate electrode MG has a laminated structure in which an upper cap film CPb including an insulating material such as SiN, which is different from the lower cap film CPa, The cap film CP has been described. However, the present invention is not limited to this, and a cap film of a single layer or a cap film of a laminate structure of three or more layers may be used.

In the first embodiment described above, four electrical cutouts 13a, 13b, 13d, 13c (13e, 13f, 13h, 13g) are provided on the extended electrode portions 15a, 15b, 15c, 15d, In the second embodiment described above, six electrically cut portions 23a, 23b, 23c, 23f, 23e and 23d are provided on the elongated electrode portions 25a and 25b. In the third embodiment described above, Four electrically cut portions 33a, 33b, 33c and 33d are provided on the mounting electrode portions 35a and 35b and six electrically cut portions (not shown) are provided on the extended electrode portions 45a and 45b in the above- 43b, 43c, 43d, 43e, and 43f are provided in the extended electrode portion. However, the present invention is not limited thereto, and three or more electrical cut portions may be provided at various positions of the extended electrode portion, The numbers and shapes of the electrically cut portions in the extended electrode portions on both sides of the memory gate The electrical cut portion may be formed asymmetrically around the electrode.

(6) On the positional relationship between the electrical cutting area and the physical cutting area

In the first to third embodiments described above, on both sides of the select gate forming region ER9, the electrically cut region ER2 (ER4) and the physical cut region ER1 (ER5) are arranged in the order of the select gate forming region ER9 However, the present invention is not limited to this, and the positions of the electrically cut region ER2 (ER4) and the physical cut region ER1 (ER5) may be reversed to form a physical cut at both sides of the select gate formation region ER9 The region ER1 (ER5) and the electrically cut region ER2 (ER4) may be formed in this order.

For example, Fig. 8 showing the same parts as those in Fig. 5 with the same reference numerals is used for reversing the electrical cut region ER2 (ER4) and the physical cut region ER1 (ER5) of the memory cell forming portion 22a shown in Fig. In the memory cell forming portion 52 shown in FIG. In this case, in the memory cell formation portion 52, one physical cleavage region ER11 is disposed at one end of the select gate formation region ER9, and another physical cleavage region ER15 is disposed at the other end of the select gate formation region ER9 , And an electrically cut region ER12 (ER14) is disposed at the distal end of the physical cut region ER11 (ER15).

The memory cell forming portion 52 is provided with a memory gate electrode MG extending in the form of a band in the select gate forming region ER9 and is provided with a select gate forming region ER9 (ER15) and an electrically cut region ER12 (55a) and (55b) in which the memory gate electrode (MG) is extended as is. In this embodiment, the elongated electrode portions 55a and 55b are formed in the shape of a ψ-shape in which the leading end portion is divided into three parts as viewed from above the semiconductor substrate, and the continuous mounting portions 56d and an extended portion 56a and end portions 56b, 56c formed in the electrically cut region ER12 (ER14).

In this case, the successive mounting portion 56d is provided with the extended root portion 57a of the physical cut region ER11 (ER15) from the end portion of the memory gate electrode MG of the select gate forming region ER9 and the root portion 57a extending from the root portion 57a in three An extension portion 56a is formed in the central branch portion of the branch portion 57b and ends 56b and 56c are formed at both end branch portions of the branch portion 57b Respectively.

A continuous setting portion 56d as a side wall non-forming portion in the physical cutting region ER1 is provided with a physical cut portion (not shown) on the outer peripheral wall that continuously connects the first sidewall 11 of the memory gate electrode MG and the sidewall of one end 56b A physical cutting portion 54b is formed on the outer wall of the one end portion 56b and the side wall of the extending portion 56a so as to be continuous with the other side wall of the extending portion 56a, A physical cutting portion 54c is formed on the outer peripheral wall of the side wall of the end portion 56c and a physical portion 54c is formed on the outer peripheral wall of the side wall of the other end portion 56c and the second sidewall 12 of the memory gate electrode MG, A cut portion 54d is formed so that a total of four physical cut portions 54a, 54b, 54c, and 54d are provided.

The physical cutting portions 54a, 54b, 54c, and 54d are formed such that a conductive layer such as a semiconductor material is not formed along the outer peripheral wall of the continuous mounting portion 56d and the outer peripheral wall of the continuous mounting portion 56d is exposed . The physical cutout portions 54a, 54b, 54c and 54d are formed so as to cover the source side select gate electrode SG formed along the first sidewall 11 of the memory gate electrode MG and the second side wall 12 of the memory gate electrode MG The source-side selection gate electrode SG and the drain-side selection gate electrode DG can be made non-conductive by forming a physical cut with a gap between the drain-side selection gate electrode DG formed in accordance with this embodiment. In addition, no cap film CP is formed in the continuous mounting portion 56d in the physical cutting region ER11 (ER15) of the elongated electrode portions 55a and 55b, and a memory gate contact MGC is provided at a predetermined position.

Electrical cuts 53c and 53d are formed on the opposing side walls of the extended portion 56a disposed on the extension of the memory gate electrode MG of the selective gate formation region ER9 in the electrically cut region ER12 (ER14) Electrical cut portions 53a and 53b are formed on opposite side walls of an end portion 56b formed at an outer lateral position of one of the lateral sides of the extended portion 56a and the opposite side walls of the end portion 56c formed at the other lateral lateral position of the extended portion 56a Electrical cut portions 53e and 53f are formed and a total of six electrical cut portions 53a, 53b, 53c, 53d, 53e and 53f are formed. The cap film CP is formed on the extended portion 56a and the end portions 56b and 56c in the electrically cut region ER12 (ER14) of the extended electrode portions 55a and 55b in the same manner as the memory gate electrode MG of the select gate forming region ER9 Respectively.

The electrically cut portions 53a, 53b, 53c, 53d, 53e, and 53f all have the same configuration, and include sidewall-shaped intrinsic semiconductor layers Ia and Ib including i-type and sidewall- Layer OC, and a reverse-conducting semiconductor layer OC is formed between the intrinsic semiconductor layers Ia and Ib. In addition, the inversing type semiconductor layer OC is formed by a conductive type (p type in this case) different from the source side selection gate electrode SG and the drain side selection gate electrode DG.

Thereby, even if the foreign substance is attached to the continuous mounting portion 56d and the source side selection gate electrode SG and the electric cutoff portion 53a of the end portion 56b become conductive, the electric cutoff portion 53a A pin junction can be formed along the side wall of the end portion 56b from the first sidewall 11 of the memory gate electrode MG starting from the n-type source side select gate electrode SG, The current can be cut off in the electrically cut region ER2 (ER4).

Foreign bodies are also attached to one of the electrical cut portions 53a of the end portions 56b so that the other electrical cut portions 53b of the end portion 56b can be removed from the source side select gate electrode SG, Type source side selection gate electrode SG to the end of the memory gate electrode MG from the first sidewall 11 by the other electrical cutoff portion 53b of the end portion 56b 56b, and the current of the source side selection gate electrode SG can be cut off in the electrically cut region ER2 (ER4).

The memory cell forming portion 52 also includes six electrically cut portions 53a, 53b, 53c, 53d, 53e, 53f capable of cutting the source side select gate electrode SG and the drain side select gate electrode DG in the same manner as in the above- Is provided along the sidewall of the elongated electrode portions 55a and 55b and the portion for cutting the source side select gate electrode SG and the drain side select gate electrode DG is increased as compared with the conventional one. It is possible to prevent the reading malfunction caused by the voltage fluctuation.

8 includes a continuous mounting portion 56d of the physical cut region ER1 provided between the select gate forming region ER9 and the electrically cut region ER12 (ER14) in the manufacturing process, and the memory cell forming portion 52 shown in Fig. It is necessary to ensure a sufficient margin of the memory gate contact MGC for both the select gate forming region ER9 and the electrically cut region ER12 (ER14).

On the other hand, in the memory cell forming portion 22a according to the second embodiment shown in Fig. 5, since sufficient margin for the memory gate contact MGC can be secured only in the electrically cut region ER2 (ER4) The width of the physical cut region ER1 (ER5) can be made narrower than the memory cell forming portion 52 shown in Fig. 8, so that the memory cell forming portion 52 can be formed more compact than the memory cell forming portion 52 shown in Fig.

Although the memory cell forming portion 52 provided with the elongated electrode portions 55a and 55b branched into three branches has been described here, the present invention is not limited to this, Or may be provided with extended electrodes for branching beyond the branch, and the shape of the branch such as the F-shape or the Y-shape may be various. Even in such an extended electrode portion, a plurality of electrical cutoff portions can be formed in the branch portion, and a portion for cutting the source side select gate electrode SG and the drain side select gate electrode DG can be increased as compared with the conventional one have.

Also in the nonvolatile semiconductor memory device 41 according to the fourth embodiment shown in Fig. 7 described above, the electrical disconnection region ER2 (ER4) and the physical disconnection region ER1 (ER5) The physical cutting region ER1 (ER5) and the electrical cutting region ER2 (ER4) may be provided in the order of ER10, ER11. In this case, the sidewall non-forming portions 46c, 46e, and 46g are provided at the distal end of the branch successive mounting portion 46a, the extending portion 46b is provided at the front end portion of the side wall non-forming portion 46c, An end portion 46d may be provided at the tip end of the month non-forming portion 46e and an extending portion 46f may be provided at the tip end portion of the side wall non-forming portion 46g. The number of the electric cutoff portions 43a, 43b, 43c, 43d, 43e, and 43f can be increased, and the source side select gate electrode SG and the drain side select gate electrode DG It is possible to increase the number of the portions for cutting.

1, 21, 31, 41: nonvolatile semiconductor memory device
2b, 2c, 2d, 2e, 2f, 2g, 2h, 2i, 2j:
A memory cell forming section 3b, 3b, 3c, 3d, 22a, 22b, 22c, 32a, 32b, 32c, 42a,
4a, 4b, 4c: memory gate structure
5a, 5b, 5c: drain side selection gate structure
6a, 6b, 6c: Source side selection gate structure
11: first side wall
12: second side wall
15a, 15b, 15c, 15d, 25a, 25b, 35a, 35b, 45a, 45b, 55a,
CP:
ER9: selection gate forming region
MG: memory gate electrode
DG: drain side selection gate electrode
SG: source side selection gate electrode

Claims (5)

A nonvolatile semiconductor memory device provided with a plurality of memory cell forming sections,
Wherein the memory cell forming section includes:
A first select gate structure having a first select gate electrode on a well of a semiconductor substrate via a first select gate insulating film,
A second select gate structure having a second select gate electrode on the well via a second select gate insulating film;
A memory gate structure provided with a sidewall spacer between the first select gate structure and the second select gate structure and stacked on the well in the order of a lower gate insulator, a charge accumulation layer, a top gate insulator, and a memory gate electrode, Wow,
And an extended electrode portion extending from the memory gate electrode of the selection gate formation region in which the first selection gate structure and the second selection gate structure are arranged opposite to each other,
Wherein at least three of the inversely conductive semiconductor layer or the intrinsic semiconductor layer having a conductivity type different from that of the first select gate electrode and the second select gate electrode are provided on the sidewall of the extended electrode portion
And a nonvolatile semiconductor memory device. A nonvolatile semiconductor memory device provided with a plurality of memory cell forming sections,
Wherein the memory cell forming section includes:
A first select gate structure having a first select gate electrode on a well of a semiconductor substrate via a first select gate insulating film,
A second select gate structure having a second select gate electrode on the well via a second select gate insulating film;
A memory gate structure provided with a sidewall spacer between the first select gate structure and the second select gate structure and stacked on the well in the order of a lower gate insulating film, a charge accumulation layer, a top gate insulating film, and a memory gate electrode, Respectively,
One memory cell forming portion and the other memory cell forming portion are provided with an extended electrode portion extending from the memory gate electrode of the select gate forming region in which the first select gate structure and the second select gate structure are opposed to each other, In a state in which it is continuously installed by the above-
Wherein at least three of the inversely conductive semiconductor layer or the intrinsic semiconductor layer having a conductivity type different from that of the first select gate electrode and the second select gate electrode are provided on the sidewall of the extended electrode portion
And a nonvolatile semiconductor memory device. 3. The method according to claim 1 or 2,
The extended electrode portion
An extension extending from the memory gate electrode of the selection gate formation region,
A straight end portion disposed in parallel with the extending portion and disposed so as to face the side wall of the extending portion,
And a continuous mounting portion for continuously connecting the extension portion and the end portion,
The reverse conducting semiconductor layer or the intrinsic semiconductor layer is formed along the sidewalls of the extended portion and the end portion
And a nonvolatile semiconductor memory device. 4. The method according to any one of claims 1 to 3,
A physical cutout portion in which a semiconductor layer is not formed is formed on the sidewall of the extended electrode portion between the adjacent inductance-increasing semiconductor layers or adjacent intrinsic semiconductor layers adjacent to each other
And a nonvolatile semiconductor memory device. 5. The method of claim 4,
A cap film is formed on the upper surface of the memory gate electrode,
Wherein the cap film is not formed in the physical cut region where the physical cut portion of the extended electrode portion is formed and the memory gate contact is provided
And a nonvolatile semiconductor memory device.

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