TWI591781B - 封裝結構及其形成方法 - Google Patents

封裝結構及其形成方法 Download PDF

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TWI591781B
TWI591781B TW104140043A TW104140043A TWI591781B TW I591781 B TWI591781 B TW I591781B TW 104140043 A TW104140043 A TW 104140043A TW 104140043 A TW104140043 A TW 104140043A TW I591781 B TWI591781 B TW I591781B
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Taiwan
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package
die
support
package structure
forming
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TW104140043A
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TW201642412A (zh
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陳憲偉
陳威宇
謝正賢
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台灣積體電路製造股份有限公司
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Description

封裝結構及其形成方法
本揭露是關於一種半導體結構及其形成方法，且特別是有關於一種封裝結構及其形成方法。
近年來，由於各種電子構件（例如電晶體、二極體、電阻器、電容器等）的積集度不斷提升，半導體工業因而快速成長。這種積集度的提升，大多是因為最小特徵尺寸的持續縮小，因而允許將更多的構件整合在一特定的區域中。
相較於先前的封裝件，這些尺寸較小的電子構件佔據較小的面積，因而需要較小的封裝件。用於半導體的封裝件的類型的實例包括四方扁平封裝（quad flat pack；QFP）、針格陣列（pin grid array；PGA）、球格陣列（ball grid array；BGA）、覆晶（flip chip；FC）、三維積體電路（three dimensional integrated circuit；3DIC）、晶圓級封裝（wafer level package；WLP）以及疊層封裝（package on package；PoP）元件。研磨（grinding）步驟或拋光（polishing）步驟為製作封裝件的製程中的主要步驟之一。如何達到封裝結構的研磨均勻度的較佳控制，已得到業界的關注。
本揭露提供一種封裝結構及其形成方法，可改善封裝結構的研磨均勻度。
根據本揭露的一些實施例，一種封裝結構包括晶粒、介電層、封裝體以及多個支撐物。晶粒包括接點。介電層位於晶粒上方以及接點側邊。封裝體位於晶粒側邊。多個支撐物位於接點側邊的介電層中。此外，支撐物的研磨速率實質上相同於封裝體的研磨速率，但不同於介電層的研磨速率。
在本揭露的一些實施例中，上述支撐物的總頂面積大於晶粒的總頂面積的約百分之三十。
在本揭露的一些實施例中，上述支撐物包括柱狀物、牆狀物、環狀物或其組合。
在本揭露的一些實施例中，上述封裝體的頂部、支撐物的頂部以及接點的頂部為實質上共平面。
根據本揭露的一些實施例，一種疊層封裝元件包括第一封裝結構以及形成於第一封裝結構上方的第二封裝結構。第一封裝結構包括晶粒、介電層、封裝體以及多個支撐物。晶粒包括多個接點。介電層位於晶粒上方以及接點側邊。封裝體位於晶粒側邊。多個支撐物位於介電層中，其中支撐物的材料與封裝體的材料相同。
在本揭露的一些實施例中，上述支撐物的總頂面積大於晶粒的總頂面積的約百分之三十。
根據本揭露的一些實施例，一種封裝結構的形成方法包括以下步驟。提供晶粒，其中所述晶粒包括位於其第一側上方的多個接點。於晶粒的第一側上方形成多個介電圖案，所述介電圖案覆蓋接點。於載板上方置放晶粒。於載板上方形成封裝體，所述封裝體囊封晶粒並填入介電圖案之間的間隙中。移除部分封裝體，直到裸露出接點的頂部，以於介電圖案之間的間隙中提供支撐物。
在本揭露的一些實施例中，於形成介電圖案之後，上述方法更包括進行切割製程，以將所述晶粒與相鄰晶粒分開。
在本揭露的一些實施例中，上述支撐物包括柱狀物、牆狀物、環狀物或其組合。
在本揭露的一些實施例中，上述支撐物的總頂面積大於晶粒的總頂面積的約百分之三十。
基於上述，本揭露提供具有支撐物的封裝結構及其形成方法。晶粒區域內的支撐物與晶粒區域外的封裝體實質上具有相同的研磨速率，且支撐物的總頂面積大於晶粒的總頂面積的約百分之三十。以此種配置方式，於操作其間，研磨輪經受較少的研磨速率變化，因此拋光均勻度可相應改善，且研磨輪的壽命因此延長。
為讓本揭露的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
以下揭露內容提供用於實施所提供的標的之不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本揭露為目的。當然，這些僅僅為實例而非用以限制。舉例來說，於以下描述中，在第一特徵上方或在第一特徵上形成第二特徵可包括第二特徵與第一特徵形成為直接接觸的實施例，且亦可包括第二特徵與第一特徵之間可形成有額外特徵使得第二特徵與第一特徵可不直接接觸的實施例。此外，本揭露在各種實例中可使用相同的元件符號及/或字母來指代相同或類似的部件。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
另外，為了易於描述附圖中所繪示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「在…上」、「在…上方」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向（旋轉90度或在其他定向），而本文所用的空間相對術語相應地作出解釋。
圖1A至圖1G為根據一些實施例所繪示的一種封裝結構的形成方法的剖面示意圖。
請參照圖1A，提供晶圓，所述晶圓具有多個以陣列排列的晶粒10。每一個晶粒10包括內連線102、金屬線104以及多個接點106。於基底100上方形成內連線102。基底100包括（例如但不限於）塊狀矽、摻雜或未摻雜基底、或絕緣體上半導體（semiconductor-on-insulator；SOI）基底的主動層。於內連線102上方形成於金屬線104，且金屬線104與內連線102電性連接。切割區域101位於為兩個相鄰晶粒10之間。
於部分金屬線104上方形成接點106，且接點106與部分金屬線104電性連接。在一些實施例中，接點106形成為晶粒10的上部。接點106從晶粒10的下部或剩餘部分延伸出來。貫穿全文，晶粒10之具有接點106的該側稱為前側第一側11。此外，接點106可為電性接點、虛設接點或兩者。接點106包括錫凸塊、金凸塊、銅柱（copper posts）或類似物。在一些實施例中，接點106為銅凸塊。術語「銅柱」表示銅突起物、銅柱狀物、厚的銅墊及/或含銅突起物。貫穿全文，術語「銅」意欲包括實質上純的元素銅、含有無法避免雜質的銅、以及含有少量元素的銅合金，所述少量元素例如為鈦（tantalum）、銦（indium）、錫（tin）、鋅（zinc）、錳（manganese）、鉻（chromium）鈦（titanium）、鍺（germanium）、鍶（strontium）、鉑（platinum）、鎂（magnesium）、鋁（aluminum）或鋯（zirconium）等等。
接著，於晶粒10的第一側11上方形成介電層108，且介電層108覆蓋接點106並填入接點106之間的間隙中。在一些實施例中，介電層108包括光敏（photo-sensitive）材料，例如聚苯並噁唑（polybenzoxazole；PBO）、聚醯亞胺（polyimide）、苯環丁烯（benzocyclobutene；BCB）、其組合或類似物，其可使用光罩輕易地被圖案化。在替代性實施例中，介電層108包括氮化物（例如氮化矽）、氧化物（例如氧化矽）、磷矽玻璃（phosphosilicate glass；PSG）、硼矽玻璃（borosilicate glass；BSG）、硼磷矽玻璃（boron-doped phosphosilicate glass；BPSG）、其組合或類似物。介電層108可由適當的製作技術所形成，例如旋塗法、化學氣相沉積法（CVD）、電漿增強型化學氣相沉積法（PECVD）或類似方法。
請參照圖1B，將介電層108圖案化以形成多個介電圖案108a以及介電圖案108a之間的多個間隙108b。在一些實施例中，介電圖案108a分別覆蓋對應的接點106的頂部與側面上，且介電圖案108a之間的間隙108裸露出晶粒10的部分第一側11。在一些實施例中，晶粒10的第一側11上方的接點106為（例如）介電圖案108a所囊封（encapsulate）。圖案化步驟包括進行微影製程或進行微影蝕刻製程。在一些實施例中，相鄰晶粒10之間的切割區域101為介電層108（或介電圖案108a）所覆蓋，如圖1B所示。在替代性實施例中，介電層108的間隙108b的局部裸露出相鄰晶粒10之間的切割區域101。
圖1A以及圖1B的步驟為在晶圓階段中進行。在一些實施例中，於形成介電圖案108a之後以及於進行晶粒分離製程之前，於晶粒10的背側或第二側12（其與第一側11相對）上方形成黏著層114，如圖1B所示。黏著層114包括晶粒貼附膜（die attach film；DAF）、銀膠或類似物。
請參照圖1C，沿著切割區域101進行切割（dicing）製程或分離（singulation）製程，以將晶粒10彼此分開。在一些實施例中，於晶粒分離製程其間，切開晶粒10的第二側12上的黏著層114。用於沿著切割區域101分開晶粒10的切開機通常涉及以旋轉刀片或雷射束進行切割。換言之，切割製程或分離製程為（例如）雷射切開製程或機械切開製程。
於進行切割製程或分離製程之後，如圖1D所繪示的實例所示，於載板110上方置放多個晶粒10中的一者。提供具有黏膠層111形成於其上的載板110。載板110可為空白玻璃（blank glass）載板、空白陶瓷（blank ceramic）載板或類似物。黏膠層111可由黏著劑所形成，例如紫外線（UV）膠、光熱轉換（Light-to-Heat Conversion；LTHC）膠、或類似物，也可使用其他類型的黏著劑。在一些實施例中，黏膠層111於光熱作用下分解，從而使載板110從其所在的結構上脫離（release）。
於黏膠層111上方形成介電層112。在一些實施例中，介電層112為聚合物層。聚合物包括（例如）聚醯亞胺、PBO、BCB、味之素堆積膜（Ajinomoto Buildup film；ABF）、阻焊膜（Solder Resist；SR）膜、或類似物。介電層112由適當的製作技術所形成，例如旋塗法、疊層法、沉積法或類似方法。
在一些實施例中，將晶粒10的背側或第二側12（其與第一側11相對）貼附至載板110。在一些實施例中，將每一個晶粒10的第二側12上方的黏著層114貼附至載板110上方的介電層112。
接著，於晶粒10側邊或周圍的載板110上方形成多個穿孔116。在一些實施例中，於介電層112上方形成穿孔116。穿孔116包括銅、鎳、錫、其組合或類似物。在一些實施例中，穿孔116更包括阻障層以避免金屬擴散。穿孔116的示例性形成方法包括於載板110上方形成光阻層（例如乾膜抗蝕劑）。接著，於光阻層中形成開口。然後，以電鍍方式於開口中形成穿孔116。繼之，將光阻層剝除。在一些實施例中，穿孔116的頂部與介電圖案108a的頂部實質上齊平。在替代性實施例中，穿孔116的頂部低於或高於介電圖案108a的頂部。
請參照圖1E，於載板110上方形成封裝體118，以囊封晶粒10並填入介電圖案108a之間的間隙108b中。在一些實施例中，封裝體118囊封穿孔116且囊封晶粒10的頂部及側面。具體而言，封裝體118覆蓋介電圖案108a的頂部及側面並完全地填滿介電圖案108a之間的間隙108b中，覆蓋晶粒10的側面，且同時覆蓋穿孔116的頂部及側面。
在一些實施例中，封裝體118包括模製化合物（molding compound）、模製底部填料（molding underfill）、樹脂或類似物，例如環氧樹脂。封裝體118可由適當的製作技術所形成，例如旋塗法、疊層法、沉積法或類似方法。在一些實施例中，封裝體118包括光敏材料，例如聚苯並噁唑（PBO）、聚醯亞胺、苯環丁烯（BCB）、其組合或類似物，其可使用光罩輕易地被圖案化。在替代性實施例中，封裝體118包括氮化物（如氮化矽）、氧化物（如氧化矽）、磷矽玻璃（PSG）、硼矽玻璃（BSG）、硼磷矽玻璃（BPSG）、其組合或類似物。
封裝體118與介電層108（或介電圖案108a）具有不同的研磨速率（grinding rate）。研磨速率定義為每單位時間的被移除的膜厚度（thickness of a film removed per unit time）。在一些實施例中，當形成於基底上的膜在預定壓力下被研磨或被拋光時，進行研磨速率的量測。研磨速率被各種的製程因子所影響，例如拋光漿或研磨漿的組成物、拋光輪或研磨輪的設計及/或硬度（hardness）、膜的硬度及/或材料等等。
在一些實施例中，對所得到的結構進行研磨製程。在一些實施例中，於研磨製程之後進行拋光製程。在一些實施例中，封裝體118的拋光或研磨速率小於介電層108（或介電圖案108a）的拋光或研磨速率。在替代性實施例中，封裝體118的拋光或研磨速率大於介電層108的拋光或研磨速率。在一些實施例中，封裝體118及介電層108包括具有不同研磨速率的不同材料。
請參照圖1F，移除部分封裝體118，直到裸露出接點106的頂部，以於介電圖案108a之間的間隙108b中分別提供支撐物120。具體而言，使用接點106作為拋光或研磨終止層，進行研磨製程或拋光製程，以移除部分封裝體118以及部分介電圖案108a，因而，剩餘的介電圖案108a之間的剩餘的或變薄的封裝體118會於間隙108b中分別形成支撐物120。在一些實施例中，於研磨製程或拋光製程其間，同時移除掉接點106的上部以及穿孔116的上部，以移除接點106與穿孔116的上表面上的不需要的氧化物或聚合物殘留。
在一些實施例中，支撐物120由封裝體118中形成得來，所以支撐物120及封裝體118由具有實質上相同研磨速率的相同材料所構成，如圖1E以及圖1F的步驟所示。在替代性實施例（例如，圖3A至圖3H的實施例）中，支撐物及封裝體由不同的材料所形成但展現實質上相同的研磨速率。
於研磨製程或拋光製程之後，封裝體118的頂部、支撐物120的頂部以及接點106的頂部為實質上共平面。在一些實施例中，位於晶粒區域13（亦即，為晶粒10所佔據的區域）內的支撐物120、接點106以及介電圖案108a的頂部與晶粒區域13外的封裝體118以及穿孔116的頂部實質上齊平。至此，完成本揭露的封裝結構150。
請參照圖1G，形成金屬線160，其中金屬線160作為重配置層（Redistribution Layer；RDL）且與封裝結構150的接點106電性連接。形成焊球170，其中焊球170與金屬線160電性連接。將具有金屬線160及焊球170的封裝結構150翻轉，黏膠層111於光熱作用下分解，而後載板110從封裝結構150中脫離。接著，將介電層112圖案化，以於介電層112中形成多個開口。
然後，提供另一封裝結構180。在一些實施例中，另一封裝結構180具有基底203以及裝設於基底203的一表面（例如，頂表面）上的晶粒201。打線（bonding wires）207可用於提供晶粒201與位於基底203的頂表面部分中的一組接合墊205之間的電性連接。於上述構件上方形成封裝體209，以保護上述構件免於環境以及外部污染。穿孔（未繪示）可用於提供接合墊205與位於基底203的底表面部分中的另一組接合墊211之間的電性連接。多個接點214（例如錫球）形成於基底203的相對表面（例如，底表面）上，以電性連接至接合墊211。
在一些實施例中，本揭露的封裝結構150可連接至另一封裝結構180，以形成疊層封裝（PoP）元件。具體而言，另一封裝結構180的接點214與介電層112的開口對準且插入於介電層112的開口中，因而與封裝結構150的穿孔116電性連接。
上述圖1A至圖1F的製程步驟可參照圖2的流程圖精簡說明如下。
於步驟200中，提供晶粒10。晶粒10包括位於其第一側11上方的多個接點106。於步驟202中，於晶粒10的第一側上方形成多個介電圖案108a，且介電圖案108a覆蓋接點106，如圖1B所示。於步驟204中，進行切割製程，以將晶粒10與相鄰晶粒10分開，如圖1C所示。於步驟206中，於載板110上方置放晶粒10，如圖1D所示。於步驟208中，於晶粒10側邊的載板110上方形成多個穿孔116，如圖1D所示。於步驟210中，於載板110上方形成封裝體118，且封裝體118囊封晶粒10並填入介電圖案108a之間的間隙108b中，如圖1E所示。於步驟212中，移除部分封裝體118，直到裸露出接點106的頂部，以於介電圖案108a之間的間隙108b中提供支撐物120，如圖1F所示。
請注意，在一些實施例中，支撐物120的總頂面積大於晶粒10的總頂面積的約百分之三十或百分之五十。晶粒10的總頂面積定義為晶粒區域13的面積。換言之，支撐物120對晶粒10的頂面積比率（top area ratio）為大於約0.30或0.50。在一些實施例中，支撐物120對晶粒10的頂面積比率可為（例如但不限於）約0.30、0.35、0.40、0.45、0.50、0.55、0.60、0.65、0.70、0.75、0.80、0.85、0.90、0.95，包括任意兩個前述數值之間的任何範圍，以及大於任一個前述數值的範圍。在一些實施例中，支撐物120對晶粒10的頂面積比率如上所述，以改善研磨均勻度或拋光均勻度。
具體而言，晶粒區域13內的支撐物120與晶粒區域13外的封裝體118提供為具有相似的研磨速率，且支撐物120之對著（against）或接觸（contacting）拋光輪或研磨輪的頂表面盡可能地被最大化。以此方式，於操作其間，拋光輪或研磨輪經受較小的研磨速率變化。因此，大幅減少或未觀察到習知的凹陷效應（dishing effect）。可相應改善拋光均勻度，因而延長拋光輪或研磨輪的壽命。
圖3A至圖3H為根據一些實施例所繪示的一種封裝結構的形成方法的剖面示意圖。圖4為根據一些實施例所繪示的一種封裝結構的形成方法的流程圖。圖3A至圖3H的方法以及圖1A至圖1G的方法之間的差異在於形成支撐物的順序。差異處將詳述如下，相同處則不再贅述。
請參照圖3A以及圖4，提供如圖1B所示的中間結構。提供晶圓，所述晶圓具有多個晶粒10，且每一個晶粒10包括位於其第一側11上方的多個接點106（步驟300）。接著，於晶粒10的第一側11上方形成多個介電圖案108a，且介電圖案108a分別覆蓋接點106（步驟302）。
請參照圖3B、圖3C以及圖4，於介電圖案108a之間的間隙108b中分別形成支撐物120a（步驟304）。支撐物120a與介電圖案108a包括不同的介電材料。在一些實施例中，支撐物120a包括氮化物（例如氮化矽）、氧化物（例如氧化矽）、磷矽玻璃（PSG）、硼矽玻璃（BSG）、硼磷矽玻璃（BPSG）、其組合或類似物。支撐物120a的示例性形成方法包括於基底100上方沉積介電材料層122，且介電材料層122填入介電圖案108a之間的間隙108b中（如圖3B所示）。接著，使用介電圖案108a作為拋光中止層，以化學機械拋光（chemical mechanical polishing；CMP）移除部分介電材料層122（如圖3C所示）。於CMP製程之後，介電圖案108a的頂部與支撐物120a的頂部為實質上共平面。
支撐物120a的研磨速率不同於介電圖案108a的研磨速率。在一些實施例中，支撐物120a的拋光或研磨速率小於介電圖案108a的拋光或研磨速率。在替代性實施例中，支撐物120a的拋光或研磨速率大於介電圖案108a的拋光或研磨速率。
圖3A至圖3B的步驟為在晶圓階段中進行。在一些實施例中，於形成介電圖案108a及支撐物120a之後以及於進行晶粒分離製程之前，於晶粒10的背側或第二側12上方形成黏著層114（例如DAF），如圖3C所示。
請參照圖3D以及圖4，進行切割製程，以將晶粒10與相鄰晶粒10分開（步驟306）。
請參照圖3E以及圖4，於載板110上方置放晶粒10（步驟308）。接著，於晶粒10側邊的載板110上方形成多個穿孔116（步驟310）。
請參照圖3F以及圖4，於載板110上方形成封裝體118，且封裝體118囊封晶粒10（步驟312）。在一些實施例中，封裝體118囊封穿孔116且囊封晶粒10的頂部及側面。具體而言，封裝體118覆蓋介電圖案108a以及支撐物120a的頂部，覆蓋晶粒10的側面，且同時覆蓋穿孔116的頂部及側面。
請參照圖3G以及圖4，移除部分封裝體118，直到裸露出接點106的頂部（步驟314）。在一些實施例中，使用接點106作為拋光或研磨終止層，進行研磨或拋光製程，以移除部分封裝體118、部分介電圖案108a以及部分支撐物120a。在一些實施例中，於研磨或拋光製程其間，視需要，同時移除掉接點106的上部以及穿孔116的上部。於研磨或拋光製程之後，封裝體118的頂部、支撐物120a的頂部以及接點106的頂部為實質上共平面。至此，完成本揭露的封裝結構150a。
請參照圖3H，本揭露的封裝結構150a可連接至另一封裝結構180，以形成疊層封裝元件。
請注意，在一些實施例中，支撐物120a及封裝體118由不同材料所形成但展現實質上相同的研磨速率，且支撐物120a的總頂面積大於晶粒10的總頂面積的約百分之三十或百分之五十。以此方式，晶粒內的抵抗（resistant to）研磨或拋光製程的材料的等效（equivalent）研磨速率與晶粒外的材料的等效研磨速率類似，因此，晶粒內外的研磨速率變化會最小化，因而改善了步驟314中的研磨或拋光均勻度。
本揭露的封裝結構將參照圖1F及圖3G的剖面示意圖以及圖5至圖10的上視圖說明如下。
請參照圖1F以及圖3G，封裝結構包括晶粒10、介電層108、封裝體118、多個穿孔116以及多個支撐物120/120a。晶粒10包括位於其第一側11上方的多個接點106。介電層108位於晶粒10的第一側11上方，且位於接點106側邊或環繞接點106。封裝體118位於晶粒10側邊或環繞晶粒10。穿孔116位於晶粒10側邊或環繞晶粒10，並穿過封裝體118。支撐物120/120a穿過介電層108。此外，支撐物120/120a以及封裝體118具有實質上相同的研磨速率，而支撐物120/120a的研磨速率不同於介電層108的研磨速率。
在一些實施例（例如，圖1A至圖1G的實施例）中，支撐物120及封裝體118包括具有相同研磨速率的相同材料。在替代性實施例（例如，圖3A至圖3H的實施例）中，支撐物120a及封裝體118包括展現實質上相同的研磨速率的不同材料。在一些實施例中，封裝體118的頂部、支撐物120/120a的頂部以及接點106的頂部為實質上共平面。
請參照圖1F、圖3G、圖5以及圖6，支撐物120/120a為以規則或不規則陣列排列的柱狀物。在一些實施例中，相鄰介電圖案108a彼此相連以形成網狀（mesh-shaped）介電層108，且各自以柱狀陣列排列的接點106以及支撐物120/120a穿過介電層108的網孔（meshes）。
在一些實施例中，支撐物形成為圓形的柱狀物，但本揭露不以此為限。在替代性實施例中，方形的柱狀物或其他形狀的柱狀物用來取代圓形的柱狀物。在一些實施例中，每一個柱狀物具有實質上相同的尺寸或頂面積，如圖5所示。在替代性實施例中，依製程需要，支撐物具有不同的尺寸或頂面積，如圖6所示。
請參照圖1F，圖3G以及圖7，支撐物120/120a形成為牆狀物。在一些實施例中，接點106為以陣列排列的多個傾斜列（slanted columns），且一個牆狀物形成於多個接點106側邊，例如，一個牆狀物形成於接點106的兩個傾斜列之間，如圖7所示，但本揭露不以此為限。在替代性實施例中，接點106為以陣列排列的多個垂直列（vertical columns），且一個牆狀物形成於接點106的兩個垂直列之間。在另一些替代性實施例中，接點106為以陣列排列的多個傾斜或垂直行（rows），且一個牆狀物形成於接點106的兩個傾斜或垂直行之間。
請參照圖1F、圖3G、圖8以及圖9，支撐物120/120a為位於接點106側邊的環狀物，且介電圖案108a形成於支撐物120/120a與接點106之間。在一些實施例中，支撐物120/120a為分別環繞至少一接點106的環狀物。在一些實施例中，支撐物120/120a形成為方形環狀（rectangular ring shaped）支撐物，如圖8所示。在替代性實施例中，支撐物120/120a形成為圓形環狀（circular ring shaped）支撐物，如圖9所示。在一些實施例中，至少部分的支撐物120/120a相連以形成網狀物（net-like）結構。在替代性實施例中，多個環狀物為彼此分開。
在上述的實施例中，支撐物為柱狀物、牆狀物或環狀物僅僅是用來說明，但並不用以限定本揭露的範疇。在替代性實施例中，其他形狀的支撐物、或上述柱狀物、牆狀物及環狀物中的至少兩者的組合均可應用於本揭露。在一些實施例中，支撐物120/120a包括環狀物以及牆狀物，如圖10所示，其中每一個環狀支撐物環繞晶粒10的邊角或密集區域中的部分接點106，而牆狀物形成於晶粒10的中心或開放區中。本領域具有通常知識者應理解，可能存在支撐物的其他組合與配置。在一些實施例中，支撐物均勻分布於晶粒區域中。在替代性實施例中，支撐物隨機且不均勻地分布於晶粒區域中。換言之，支撐物的形狀、尺寸、變化、配置以及分布並不以本揭露為限。
只要位於晶粒區域內的接點側邊的介電圖案之間的支撐物與晶粒區域外的封裝體提供為具有相同或相似的研磨速率或由相同或相似的材料所組成，且支撐物的總頂面積大於晶粒的總頂面積約百分之三十，則這種支撐物視為落入本揭露的精神與範疇內。以此配置方式，晶粒區域內的材料的等效研磨速率實質上相同於晶粒區域外的材料的等效研磨速率，以最小化研磨或拋光製程其間的晶粒內外的研磨速率變化。
換言之，與晶粒區域中不具有支撐物的情況相比，由於支撐物佔據晶粒面積的大於三分之一或二分之一且支撐物與封裝體具有相似的研磨速率，因此晶粒區域內的支撐物及介電圖案的等效研磨速率與晶粒區域外的封裝體的研磨速率接近。所以，由晶粒內至晶粒外的抵抗研磨或拋光製程的研磨速率將會微幅地變化，並由此改善了拋光均勻度。
在一些實施例中，於本揭露的封裝結構的形成方法中，可省略形成介電層108（或介電圖案108a）的步驟。
圖11A至圖11F為根據一些實施例所繪示的一種封裝結構的形成方法的剖面示意圖。圖12為根據一些實施例所繪示的一種封裝結構的形成方法的流程圖。
請參照圖11A以及圖12，提供晶圓，所述晶圓具有多個晶粒10，且每一個晶粒10包括位於其第一側11上方的多個接點106（步驟400）。
在一些實施例中，於晶粒分離製程之前，於晶粒10的背側或第二側12上方形成黏著層114（例如DAF），如圖11A所示。
請參照圖11B以及圖12，進行切割製程，以將晶粒10與相鄰晶粒10分開（步驟402）。
請參照圖11C以及圖12，於載板110上方置放晶粒10（步驟404）。接著，於晶粒10側邊的載板110上方形成多個穿孔116（步驟406）。
請參照圖11D以及圖12，於載板110上方形成封裝體118，且封裝體118囊封晶粒10並填入接點106之間的間隙中（步驟408）。在一些實施例中，封裝體118囊封穿孔116且囊封晶粒10的頂部與側面。具體而言，封裝體118覆蓋接點106的頂部及側面，填入接點106之間的間隙中，覆蓋晶粒10的側面，且同時覆蓋穿孔116的頂部及側面。
請參照圖11E以及圖12，移除部分封裝體118，直到裸露出接點106的頂部，使得支撐物120b分別位於接點106之間的間隙中（步驟410）。在一些實施例中，使用接點106作為拋光或研磨終止層，進行研磨或拋光製程，以移除部分封裝體118。在一些實施例中，於研磨或拋光製程其間，視需要，同時移除掉接點106的上部以及穿孔116的上部。於研磨或拋光製程之後，封裝體118的頂部、支撐物120b的頂部以及接點106的頂部為實質上共平面。至此，完成本揭露的封裝結構150b。
請參照圖11F，本揭露的封裝結構150b可連接至另一封裝結構180，以形成疊層封裝元件。
請注意，在一些實施例中，支撐物120b以及封裝體118由具有相同研磨速率的相同材料所組成，且支撐物120b的總頂面積大於晶粒10的總頂面積的約百分之三十或百分之五十。以此方式，改善了步驟410中的研磨或拋光均勻度。
圖13為根據一些實施例所繪示的一種封裝結構的上視圖。支撐物120b彼此連接以形成網狀結構，且以柱狀體陣列排列的接點106穿過網狀結構的網孔。
基於上述，本揭露提供具有內建（built-in）支撐物的封裝結構及其形成方法。晶粒區域內的最高接點側邊的介電圖案之間的非導體支撐物與晶粒區域外的封裝體實質上具有相同的研磨速率，且支撐物的總頂面積大於晶粒的總頂面積的約百分之三十。以本揭露的此種配置方式，於操作其間，研磨輪經受較少的研磨速率變化，因此拋光均勻度可相應改善，且研磨輪的壽命因此延長。
根據本揭露的一些實施例，一種封裝結構包括晶粒、介電層、封裝體以及多個支撐物。晶粒包括至少一接點。於接點側邊的晶粒上方形成介電層。封裝體位於晶粒側邊。支撐物位於接點側邊的介電層中，其中支撐物的研磨速率實質上相同於封裝體的研磨速率，但不同於介電層的研磨速率。
根據本揭露的替代性實施例，一種疊層封裝元件包括第一封裝結構以及第二封裝結構。第一封裝結構包括晶粒、介電層、封裝體以及多個支撐物。晶粒包括多個接點。於接點側邊的晶粒的第一側上方形成介電層。封裝體位於晶粒側邊。支撐物位於介電層中，其中支撐物的材料與封裝體的材料相同。於第一封裝結構上方形成第二封裝結構。
根據本揭露的另一些替代性實施例，一種封裝結構的形成方法包括至少以下步驟。提供晶粒，其中晶粒包括位於其第一側上方的多個接點。於晶粒的第一側上方形成多個介電圖案，以覆蓋接點。於載板上方置放晶粒。於載板上方形成封裝體，以囊封晶粒並填入介電圖案之間的間隙中。移除部分封裝體，直到裸露出接點的頂部，以於間隙中提供支撐物。
以上概述了數個實施例的特徵，使本領域具有通常知識者可更佳了解本揭露的態樣。本領域具有通常知識者應理解，其可輕易地使用本揭露作為設計或修改其他製程與結構的依據，以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解，這種等效的配置並不悖離本揭露的精神與範疇，且本領域具有通常知識者在不悖離本揭露的精神與範疇的情況下可對本文做出各種改變、置換以及變更。
10、201‧‧‧晶粒
11‧‧‧第一側
12‧‧‧第二側
13‧‧‧晶粒區域
100、203‧‧‧基底
101‧‧‧切割區域
102‧‧‧內連線
104、160‧‧‧金屬線
106、214‧‧‧接點
108、112‧‧‧介電層
108a‧‧‧介電圖案
108b‧‧‧間隙
110‧‧‧載板
111‧‧‧黏膠層
114‧‧‧黏著層
116‧‧‧穿孔
118、209‧‧‧封裝體
120、120a、120b‧‧‧支撐物
150、150a、150b‧‧‧封裝結構
170‧‧‧焊球
180‧‧‧另一封裝結構
200、202、204、206、208、210、212、300、302、304、306、308、310、312、314、400、402、404、406、408、410‧‧‧步驟
205、211‧‧‧接合墊
207‧‧‧打線
圖1A至圖1G為根據一些實施例所繪示的一種封裝結構的形成方法的剖面示意圖。 圖2為根據一些實施例所繪示的一種封裝結構的形成方法的流程圖。 圖3A至圖3H為根據一些實施例所繪示的一種封裝結構的形成方法的剖面示意圖。 圖4為根據一些實施例所繪示的一種封裝結構的形成方法的流程圖。 圖5至圖10為根據一些實施例所繪示的封裝結構的上視圖。 圖11A至圖11F為根據一些實施例所繪示的一種封裝結構的形成方法的剖面示意圖。 圖12為根據一些實施例所繪示的一種封裝結構的形成方法的流程圖。 圖13為根據一些實施例所繪示的一種封裝結構的上視圖。
10‧‧‧晶粒
11‧‧‧第一側
12‧‧‧第二側
13‧‧‧晶粒區域
100‧‧‧基底
102‧‧‧內連線
104‧‧‧金屬線
106‧‧‧接點
108、112‧‧‧介電層
108a‧‧‧介電圖案
108b‧‧‧間隙
110‧‧‧載板
111‧‧‧黏膠層
114‧‧‧黏著層
116‧‧‧穿孔
118‧‧‧封裝體
120‧‧‧支撐物
150‧‧‧封裝結構

Claims (10)

  1. 一種封裝結構，包括：晶粒，包括接點；介電層，位於所述晶粒上方以及所述接點側邊；封裝體，位於所述晶粒側邊；以及多個支撐物，位於所述接點側邊的所述介電層中，其中所述支撐物的材料實質上相同於所述封裝體的材料，但不同於所述介電層的材料，且其中所述支撐物的總頂面積佔所述晶粒的總頂面積的百分之三十至百分之七十。
  2. 如申請專利範圍第1項所述的封裝結構，其中所述封裝體的頂部、所述支撐物的頂部以及所述接點的頂部為實質上共平面。
  3. 如申請專利範圍第1項所述的封裝結構，其中所述支撐物包括柱狀物、牆狀物、環狀物或其組合。
  4. 如申請專利範圍第1項所述的封裝結構，更包括多個穿孔，所述穿孔位於所述晶粒側邊且穿過所述封裝體。
  5. 一種疊層封裝元件，包括：第一封裝結構，包括：晶粒，包括多個接點；介電層，位於所述晶粒上方以及所述接點側邊；封裝體，位於所述晶粒側邊；以及多個支撐物，位於所述介電層中，其中所述支撐物的材料與所述封裝體的材料不同；以及 第二封裝結構，形成於所述第一封裝結構上方。
  6. 如申請專利範圍第5項所述的疊層封裝元件，其中所述支撐物的總頂面積大於所述晶粒的總頂面積的百分之三十。
  7. 一種封裝結構的形成方法，包括：提供晶粒，其中所述晶粒包括多個接點，所述接點位於所述晶粒的第一側上方；於所述晶粒的所述第一側上方形成多個介電圖案，所述介電圖案覆蓋所述接點；於載板上方置放所述晶粒；於所述載板上方形成封裝體，所述封裝體囊封所述晶粒並填入所述介電圖案之間的間隙中；以及移除部分所述封裝體，直到裸露出所述接點的頂部，以於所述介電圖案之間的所述間隙中提供支撐物，其中所述支撐物的總頂面積佔所述晶粒的總頂面積的百分之三十至百分之七十。
  8. 如申請專利範圍第7項所述的封裝結構的形成方法，於形成所述介電圖案之後，更包括進行切割製程，以將所述晶粒與相鄰晶粒分開。
  9. 如申請專利範圍第7項所述的封裝結構的形成方法，其中所述支撐物包括柱狀物、牆狀物、環狀物或其組合。
  10. 如申請專利範圍第7項所述的封裝結構的形成方法，於所述載板上方置放所述晶粒的步驟之後以及於所述載板上方形成所述封裝體的步驟之前，更包括於所述晶粒側邊的所述載板上方形成多個穿孔。
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