TWI590389B - Method for preparing vacuum field effect transistor nonvolatile memory - Google Patents

Description

Vacuum tube flash memory structure manufacturing method

The present invention relates to the field of semiconductor manufacturing, and in particular, to a vacuum tube flash memory structure and a method of fabricating the same.

A Vacuum Tube is an electronic component that controls the flow of electrons in a circuit. The electrodes involved in the work are packaged in a vacuum vessel (most of the walls are glass), hence the name. Before the middle of the twentieth century, because semiconductors were not popular, basically all the electronic equipment used vacuum tubes at the time, which formed the demand for vacuum tubes at that time. However, under the development of semiconductor technology and civilians, vacuum tubes were eventually replaced by semiconductors due to their high cost, lack of durability, bulkiness, and low performance. However, the vacuum tube can be seen in the high frequency transmitters of stereos, microwave ovens and satellites. In order to prevent the electromagnetic pulse damage caused by the nuclear explosion, the electronic equipment on the machine also adopts a vacuum tube. The vacuum tube structure is as shown in Fig. 1, which includes a grid 1, a collector 3, an emitter 2 and a heating resistor wire 5. The electrons 4 flow from the emitter 2 to the collector 3.

In the early days of electronics, vacuum tubes were used to amplify, switch, or adjust electrical signals. However, with the development of semiconductor technology, solid-state components have replaced vacuum tubes for decades, such as metal oxide half field effect transistors (MOSFETs), bipolar junction transistors (BJTs), and diodes.

However, vacuum tubes are still used in sound systems and high power radio base stations. This is because vacuum tubes are more environmentally resistant than solid-state components and can be used in high temperature and various radiation environments. Vacuum is in principle a transmission medium superior to solid supports. The velocity of electrons in the vacuum is theoretically 3 x 10 ¹⁰ cm/sec, but the speed in the semiconductor is only 5 x 10 ⁷ cm/sec. Therefore, vacuum tubes perform much better than solid-state components in certain requirements.

It is an object of the present invention to provide a vacuum cell flash memory structure manufacturing method which is manufactured by using a semiconductor standard process which is generally used in the industry, and which has better programming, erasing speed and storage time, and can also improve superiority. Gate control performance and minimal gate leakage current.

To achieve the above object, a method for fabricating a vacuum tube flash memory structure of the present invention includes providing a substrate; forming a dielectric layer, a source layer, a second dielectric layer, a gate layer, and a hard screen on the substrate in sequence a cap layer; patterning the second dielectric layer, the gate layer and the hard mask layer to form a gate structure; trimming the second dielectric layer and the gate layer in the gate structure to make the remaining second dielectric layer And a gate layer having a width smaller than the hard mask layer; performing a heat treatment to form a gate dielectric layer on the sidewall of the gate layer; depositing a drain layer; and depositing the interlayer dielectric layer on the entire substrate and planarizing A vacuum is formed in the gate.

Further, the method for manufacturing the vacuum tube flash memory structure of the present invention further comprises: after planarizing the interlayer dielectric layer, treating the source layer and the drain layer with a high temperature annealing to form a cylindrical shape.

Further, the gas used in the high temperature annealing is He, N ₂ , Ar or H ₂ .

Further, wherein the temperature range of the high temperature annealing is 600 to 1000 ° C between.

Further, wherein the pressure in the vacuum in the gate ranges from 0.1 torr to 50 torr.

Further, the source layer and the drain layer are made of Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In, Ti, TiN, TaN, C. And their combinations.

Further, the gate layer material is Al, poly Si, Cu, Ga, In, Ti, Ta, W, Co, Ti, Ta, TiN, TaN and combinations thereof.

Further, wherein the heat treatment uses a plasma to perform thermal oxidation or thermal nitridation of the gate layer in an atmosphere of oxygen, nitrogen, N ₂ O or NH ₃ .

Further, the material of the hard mask layer is oxynitride, tantalum nitride, titanium nitride (TiN).

Another object of the present invention is to provide a vacuum tube flash memory structure including a substrate; a first dielectric layer and a source layer over the substrate; and a gate structure over the source layer The gate structure includes a gate layer and a hard mask layer, a gate dielectric layer on a sidewall of the gate layer, and a hollow vacuum channel, wherein the gate layer in the gate structure The width is less than the width of the hard mask layer; and a drain layer over the gate structure and enclosing the vacuum channel.

1‧‧‧Gate

2‧‧‧射极

3‧‧‧ Collector

4‧‧‧Electronics

5‧‧‧heating resistance wire

10‧‧‧Substrate

20‧‧‧First dielectric layer

30‧‧‧Source layer

35‧‧‧Second dielectric layer

40‧‧‧gate dielectric layer

50‧‧‧ gate layer

60‧‧‧vacuum channel

70‧‧‧汲pole

80‧‧‧ hard mask layer

90‧‧‧Interlayer dielectric layer

1 is a schematic view showing the working principle of a vacuum tube in the prior art; FIG. 2 is a schematic perspective view showing the structure of a vacuum tube flash memory structure according to an embodiment of the present invention; 3 is a cross-sectional view showing an embodiment of the present invention; FIG. 4 is a cross-sectional view showing another embodiment of the present invention; and FIG. 5 is a view showing a structure of a vacuum tube flash memory structure according to an embodiment of the present invention; A flow chart of the method; and FIGS. 6 to 13 are schematic cross-sectional views showing a vacuum tube flash memory structure in a manufacturing process according to an embodiment of the present invention.

The vacuum tube flash memory structure of the present invention and its manufacturing method will be described in more detail below with reference to the accompanying drawings, wherein a preferred embodiment of the invention is shown, and it is understood that those skilled in the art can modify the invention described herein. The advantageous effects of the present invention are still achieved. Therefore, the following description is to be understood as a broad description of the invention, and is not intended to limit the invention.

For the sake of clarity, the description does not describe all of the features of the actual embodiments. In the following description, well-known functions and structures are not described in detail, as they may obscure the invention in unnecessary detail. It should be understood that in the development of any actual embodiment, a large number of implementation details must be made to achieve a particular goal of the developer, such as changing from one embodiment to another in accordance with the limitations of the system or related business. Additionally, such development work should be considered complex and time consuming, but is merely a simple replacement for those skilled in the art.

The invention is more specifically described in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will be apparent from the description and appended claims. It should be noted that the drawings are in a very simplified form and all use non-precise proportions, only for convenience and clarity. The purpose of the embodiments of the present invention is explained.

Referring to FIG. 2 to FIG. 4, in this embodiment, an empty tube flash memory structure is proposed, including: a substrate 10, a dielectric layer 20, a source layer 30, a gate dielectric layer 40, and a gate. 50, a drain 70, a hard mask layer 80, and an interlayer dielectric layer (ILD) 90, wherein the dielectric layer 20 is formed on the substrate 10, the source layer 30, the gate dielectric layer 40, a gate 50 and a drain 70 are formed on the dielectric layer 20, the source layer 30 and the drain 70 are respectively located at two sides of the gate 50, and the gate 50 is provided with a vacuum channel 60. The source layer 30 and the drain 70 are exposed on both sides, and the gate dielectric layer 40 is formed on the sidewall of the gate 50 in the vacuum.

Referring to FIG. 5, in another aspect of the embodiment, a method for fabricating a vacuum tube flash memory structure for fabricating a vacuum tube flash memory structure as described above, comprising the steps of: S100: providing a substrate; S200: forming a dielectric layer on the substrate; S300: forming a source layer on the dielectric; S400: forming a second dielectric layer on the source layer; S500: in the second Forming a gate layer and a hard mask layer on the dielectric layer; S600: patterning the second dielectric layer, the gate layer and the hard mask layer to form a gate pattern; S700: trimming the gate pattern a second dielectric layer and a gate layer, such that the remaining gate layer width is smaller than the hard mask layer; S800: forming a gate dielectric layer on the sidewall of the gate by heat treatment; S900: depositing a drain layer; S1000: depositing between layers The dielectric layer is on the entire substrate and planarized; S1100: performing high temperature annealing to form the source layer and the drain layer into a cylindrical source germanium electrode.

Specifically, referring to FIG. 6, a dielectric layer 20 is formed on the substrate 10. The substrate 10 may be a general substrate such as a germanium substrate or a germanium on insulator (SOI), and the dielectric layer 20 is usually hafnium oxide.

Referring to FIG. 7, a source layer 30, a second dielectric layer 35, a gate layer 50, and a hard mask layer 80 are deposited on the dielectric layer 20 in sequence. The material of the source layer 30 is made of Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In, Ti, TiN, TaN or C. The source layer 30 can be formed by a process such as CVD or PVD. The second dielectric layer 35 is also typically cerium oxide. The gate layer 50 is a metal gate and can be formed by CVD, MOCVD or PVD. In one embodiment, the material of the metal gate is Al, poly Si, Cu, Ga, In, Ti, Ta, W, Co, Ti, Ta, TiN, TaN or the like. The material of the hard mask layer 80 is oxynitride, tantalum nitride, titanium nitride (TiN) or the like, and can be formed by a process such as CVD, MOCVD or ALD.

Referring to FIG. 8, the second dielectric layer 35, the gate layer 50 and the hard mask layer 80 are patterned to form a gate structure 31. The specific formation can be performed by a conventional lithography and etching process.

Referring to FIG. 9, the gate layer 50 and the second dielectric layer 35 in the gate structure 31 are trimmed using selective etching so that the remaining gate layer 50a and the second dielectric layer 35a are less than the hard mask layer 80. . The selective etching can be carried out The gate layer 50 is plasma trimmed (e.g., BCl ₃ , Cl ₂ ) and the second dielectric layer 35 in the gate structure 31 is trimmed by BOE or DHF wet etching.

Referring to FIG. 10, a gate dielectric layer 40 is formed by heat treatment on the sidewalls of the exposed gate 50 as shown in the drawing. The heat treatment may be a thermal oxidation or thermal nitridation process of the metal gate by using plasma in an environment of oxygen, nitrogen, N ₂ O or NH ₃ .

Referring to FIG. 11, a drain layer 70 is deposited on the surface of the substrate 10. The material of the drain layer 70 is made of Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In, Ti, TiN, TaN or C. The drain layer 70 can be formed by processes such as CVD, PVD, or sputtering. Therefore, the vacuum gate channel 60 is formed by sealing the source 30, the drain 70 and the gate structure 50, and the gas pressure in the vacuum ranges from 0.1 torr to 50 torr.

Referring to FIG. 12, an interlayer dielectric layer 90 is deposited on the surface of the substrate 10. The interlayer dielectric layer 90 is also generally cerium oxide, and can be formed by processes such as CVD, PECVD, HDP CVD, and the like.

Referring to FIG. 13, after planarizing the deposited interlayer dielectric layer 90, the source electrode 30 and the drain electrode 70 are processed into a cylindrical shape by a high temperature annealing process to avoid the presence of edges and corners, resulting in subsequent component processes. Problems such as poor reliability may occur at the corners, and the planarization may be performed by a process such as chemical mechanical polishing or etchback, and the gas used in the high temperature annealing process is He, N ₂ , Ar or H ₂ . The temperature range of the high temperature annealing process is 600 degrees Celsius to 1000 degrees Celsius, for example, 800 degrees Celsius.

In summary, in the vacuum tube flash memory structure and the manufacturing method thereof provided by the embodiments of the present invention, a vacuum is formed in the channel, wherein the gate dielectric layer uses plasma in oxygen, nitrogen, N ₂ O or NH ₃ . The thermal oxidation or thermal nitridation process of the gate layer is performed under the environment. The structure disclosed in the present invention can make the formed component have better programming, erasing speed and storage time, and can also improve superior gate control performance and extremely small gate leakage current.

The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any change in the technical solutions and technical contents disclosed in the present invention may be made in any form without departing from the technical scope of the present invention, without departing from the scope of the present invention. It is still within the scope of protection of the present invention.

It will be apparent that those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention cover the modifications and the modifications thereof

S100~S1100‧‧‧Process steps of manufacturing method of vacuum tube flash memory structure

Claims (14)

A method for manufacturing a vacuum tube flash memory structure, comprising the steps of: providing a substrate; sequentially forming a dielectric layer, a source layer, a second dielectric layer, a gate layer and a hard mask layer on the substrate; Processing the second dielectric layer, the gate layer and the hard mask layer to form a gate structure; trimming the second dielectric layer and the gate layer in the gate structure, leaving the second dielectric layer and the gate layer remaining a width less than the hard mask layer; heat treatment to form a gate dielectric layer on the sidewall of the gate layer; depositing a drain layer; depositing an interlayer dielectric layer over the entire substrate and planarizing the gate A vacuum is formed in the middle. The method according to claim 1, further comprising treating the source layer and the drain layer to have a cylindrical shape by high-temperature annealing after planarization of the interlayer dielectric layer. The manufacturing method according to claim 2, wherein the gas used for the high temperature annealing is He, N ₂ , Ar or H ₂ . The manufacturing method according to claim 2, wherein said high temperature annealing has a temperature in the range of 600 to 1000 °C. The manufacturing method according to claim 1, wherein a pressure in the vacuum in the gate is in a range of 0.1 torr to 50 torr. The manufacturing method according to claim 1, wherein said heat treatment is performed by using a plasma in a thermal oxidation or thermal nitridation process of said gate layer in an atmosphere of oxygen, nitrogen, N ₂ O or NH ₃ . The manufacturing method according to claim 1, wherein said source layer and said drain layer are made of Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In, Ti, TiN, TaN, C, and combinations thereof. The manufacturing method according to claim 1, wherein the gate layer is made of Al, poly Si, Cu, Ga, In, Ti, Ta, W, Co, Ti, Ta, TiN, TaN, and combinations thereof. The manufacturing method according to claim 1, wherein the hard mask layer is made of oxynitride, tantalum nitride, or titanium nitride (TiN). A vacuum tube flash memory structure includes: a substrate; a first dielectric layer and a source layer over the substrate; a gate structure over the source layer, the gate structure including a gate layer and a hard mask layer, a gate dielectric layer on sidewalls of the gate layer and a hollow vacuum channel, wherein a width of the gate layer in the gate structure is smaller than the hard mask a width of the layer; and a drain layer over the gate structure and enclosing the vacuum channel. The vacuum tube flash memory structure according to claim 10, wherein said source layer and said drain layer are made of Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In, Ti, TiN, TaN, C, and combinations thereof. A vacuum tube flash memory structure according to claim 10, wherein said gate layer is made of Al, poly Si, Cu, Ga, In, Ti, Ta, W, Co, Ti, Ta, TiN, TaN and combination. A vacuum tube flash memory structure according to claim 10, wherein said gate dielectric layer uses a plasma to thermally oxidize said gate layer in an atmosphere of oxygen, nitrogen, N ₂ O or NH ₃ or Generated by a thermal nitridation process. The vacuum tube flash memory structure according to claim 10, wherein the hard mask layer is made of oxynitride, tantalum nitride, or titanium nitride (TiN).