TW201810620A - Method for preparing vacuum field effect transistor nonvolatile memory - Google Patents

Abstract

The present invention relates to a method for preparing vacuum transistor flash memory structure, to form a vacuum channel in the transistor flash memory, and the gate dielectric layer is formed by metal gate plasma oxidation or nitridation process in oxygen or nitrogen or N2O, NH3 atmosphere. The present structure exhibits superior program and erase speed as well as the retention time. It also provide with excellent gate controllability and negligible gate leakage current.

Description

Manufacturing method of vacuum tube flash memory structure

The invention relates to the field of semiconductor manufacturing, in particular to a vacuum tube flash memory structure and a manufacturing method thereof.

A vacuum tube is an electronic component that controls the flow of electrons in a circuit. Participating electrodes are named in a vacuum container (most of the tube wall is glass). Before the middle of the twentieth century, because semiconductors were not yet popular, basically all electronic equipment at that time used vacuum tubes, which formed the demand for vacuum tubes at that time. However, under the development and popularization of semiconductor technology, vacuum tubes were eventually replaced by semiconductors due to high costs, non-durability, large size, and low efficiency. But you can see the vacuum tube in the high-frequency transmitter of the stereo, microwave oven and satellite. In order to prevent damage to electromagnetic pulses caused by nuclear explosions, some fighter aircraft also use vacuum tubes. The structure of the vacuum tube is shown in Figure 1. It includes grid 1, collector 3, emitter 2 and heating resistance wire 5. The electrons 4 flow from the emitter 2 to the collector 3.

Early electronic devices used vacuum tubes to amplify, switch, or regulate electrical signals. However, with the development of semiconductor technology, solid-state devices have replaced vacuum tubes for decades, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), and diodes.

However, vacuum tubes are still used in audio systems and high-power radio base stations. This is because vacuum tubes are more environmentally resistant than solid-state components and can be used in high temperature and various radiation environments. Vacuum is in principle a better transport medium than solid carriers. The speed of electrons in a vacuum is theoretically 3 × 10 ¹⁰ cm / sec, but the speed in a semiconductor is only 5 × 10 ⁷ cm / sec. Therefore, the performance of the vacuum tube is far superior to the solid-state component in some requirements.

An object of the present invention is to provide a method for manufacturing a vacuum tube flash memory structure, which is manufactured by using a semiconductor standard process commonly used in the industry, and has better programming, erasing speed and storage time, and can also improve superior Gate control performance and minimal gate leakage current.

In order to achieve the above object, the method for manufacturing a vacuum tube flash memory structure of the present invention includes providing a substrate; and forming a dielectric layer, a source layer, a second dielectric layer, a gate layer, and a hard curtain on the substrate in order. Cover layer; patterning the second dielectric layer, the gate layer and the hard curtain cover layer to form a gate structure; trimming the second dielectric layer and the gate layer in the gate structure so that the remaining second dielectric layer And the gate layer have a width smaller than the hard curtain layer; heat treatment is performed to form a gate dielectric layer on the side wall of the gate layer; a drain layer is deposited; and an interlayer dielectric layer is deposited on the entire substrate and planarized to A vacuum is formed in the gate.

Further, the manufacturing method of the vacuum tube flash memory structure of the present invention further comprises, after planarizing the interlayer dielectric layer, using high temperature annealing to process the source layer and the drain layer to make them cylindrical.

Further, the gas used for the high-temperature annealing is He, N ₂ , Ar, or H ₂ .

Further, the temperature range of the high-temperature annealing is between 600 and 1000 ° C. between.

Further, the air pressure in the vacuum in the gate electrode ranges from 0.1 torr to 50 torr.

Further, the material of the source layer and the drain layer is Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In, Ti, TiN, TaN, C And combinations.

Further, the material of the gate layer is Al, poly Si, Cu, Ga, In, Ti, Ta, W, Co, Ti, Ta, TiN, TaN, and combinations thereof.

Further, the heat treatment uses a plasma to perform a thermal oxidation or thermal nitridation process of the gate layer under an environment of oxygen, nitrogen, N ₂ O, or NH ₃ .

Further, the material of the hard curtain cover layer is silicon oxide nitride, silicon nitride, and titanium nitride (TiN).

Another object of the present invention is to provide a vacuum flash memory structure including a substrate; a first dielectric layer and a source layer on the substrate; and a gate structure on the source layer The gate structure includes a gate layer and a hard curtain layer, a gate dielectric layer on a side wall of the gate layer, and a hollow vacuum channel, wherein the gate layer in the gate structure The width is smaller than the width of the hard curtain cover layer; and a drain layer is on the gate structure and closes the vacuum channel.

1‧‧‧ grid

2‧‧‧ Emitter

3‧‧‧collector

4‧‧‧ Electronics

5‧‧‧ heating resistance wire

10‧‧‧ substrate

20‧‧‧First dielectric layer

30‧‧‧Source layer

35‧‧‧Second dielectric layer

40‧‧‧ Gate dielectric layer

50‧‧‧Gate layer

60‧‧‧Vacuum channel

70‧‧‧ Drain Layer

80‧‧‧ Hard Curtain Cover

90‧‧‧ interlayer dielectric layer

FIG. 1 is a schematic diagram of the working principle of a vacuum tube in the conventional technology; FIG. 2 is a schematic diagram of the three-dimensional structure of the flash memory structure of the vacuum tube in an embodiment of the present invention; FIG. 3 is a schematic cross-sectional view of an embodiment of the present invention; FIG. 4 is a schematic cross-sectional view of another direction in an embodiment of the present invention; and FIG. 5 is a fabrication of a flash memory structure of a vacuum tube in an embodiment of the present invention Method flowchart; Figures 6 to 13 are schematic cross-sectional views of a vacuum tube flash memory structure in a manufacturing process according to an embodiment of the present invention.

The structure of the vacuum tube flash memory of the present invention and the manufacturing method thereof will be described in more detail with reference to the schematic diagrams, which show the preferred embodiments of the present invention. It should be understood that those skilled in the art can modify the invention described herein, The advantageous effects of the invention are still achieved. Therefore, the following description should be understood as widely known to those skilled in the art, rather than as a limitation on the present invention.

In the interest of clarity, not all features of an actual embodiment are described in this specification. In the following description, well-known functions and structures are not described in detail because they may confuse the present invention with unnecessary details. It should be considered that in the development of any actual embodiment, a large number of implementation details must be made to achieve the developer's specific goals, such as changing from one embodiment to another in accordance with system- or business-related restrictions. In addition, it should be considered that such development work may be complicated and time-consuming, but it is only a simple replacement for those skilled in the art.

The invention is described in more detail by way of example in the following paragraphs with reference to the drawings. The advantages and features of the invention will be apparent from the following description and claims. It should be noted that the drawings are in a very simplified form and all use inaccurate proportions, only for convenience and clarity. Assist in explaining the purpose of the embodiments of the present invention.

Please refer to FIG. 2 to FIG. 4. In this embodiment, an empty tube flash memory structure is proposed, which includes a substrate 10, a dielectric layer 20, a source layer 30, a gate dielectric layer 40, and a gate electrode. 50. A drain electrode 70, a hard mask layer 80, and an interlayer dielectric layer (ILD) 90, wherein the dielectric layer 20 is formed on the substrate 10, the source layer 30, the gate dielectric layer 40, A gate electrode 50 and a drain electrode 70 are formed on the dielectric layer 20. The source layer 30 and the drain electrode 70 are located on both sides of the gate electrode 50. A vacuum channel 60 is provided in the gate electrode 50. The source layer 30 and the drain electrode 70 on both sides are exposed, and the gate dielectric layer 40 is formed on a sidewall of the gate electrode 50 in the vacuum.

Please refer to FIG. 5. In another aspect of this embodiment, a method for manufacturing a vacuum tube flash memory structure is also provided, for preparing the vacuum tube flash memory structure as described above, including steps: S100: provide Substrate; S200: forming a dielectric layer on the substrate; S300: forming a source layer on the dielectric; S400: forming a second dielectric layer on the source layer; S500: forming a second dielectric layer on the source layer A gate layer and a hard mask layer are sequentially formed on the dielectric layer; S600: the second dielectric layer, the gate layer, and the hard mask layer are patterned to form a gate pattern; S700: the gate pattern is trimmed The second dielectric layer and the gate layer, so that the width of the remaining gate layer is smaller than the hard curtain cover layer; S800: the gate dielectric layer is formed on the side wall of the gate by heat treatment; S900: the deposited drain layer; S1000: the inter-deposited layer A dielectric layer is formed on the entire substrate and a planarization process is performed; S1100: Perform high-temperature annealing to form the source and drain layers into a cylindrical source-drain electrode.

Specifically, referring to FIG. 6, a dielectric layer 20 is formed on a substrate 10. The substrate 10 may be a silicon substrate or a general substrate such as silicon on insulator (SOI). The dielectric layer 20 is usually silicon dioxide.

Referring to FIG. 7, a source layer 30, a second dielectric layer 35, a gate layer 50 and a hard curtain cover layer 80 are sequentially deposited on the dielectric layer 20. The source layer 30 is made of Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In, Ti, TiN, TaN, or C. The source layer 30 may be formed by a process such as CVD or PVD. The second dielectric layer 35 is also typically silicon dioxide. The gate layer 50 is a metal gate, and can be formed by CVD, MOCVD, or PVD. In one embodiment, the material of the metal gate is Al, poly Si, Cu, Ga, In, Ti, Ta, W, Co, Ti, Ta, TiN, TaN and other materials. The hard curtain cover layer 80 is made of materials such as silicon oxide nitride, silicon nitride, and titanium nitride (TiN), and can be formed by processes such as CVD, MOCVD, or ALD.

Referring to FIG. 8, the second dielectric layer 35, the gate layer 50, and the hard mask layer 80 are patterned to form a gate structure 31. The specific formation method can be performed by a conventional lithography and etching process.

Referring to FIG. 9, the gate layer 50 and the second dielectric layer 35 in the gate structure 31 are trimmed by selective etching, so that the width of the remaining gate layer 50 a and the second dielectric layer 35 a is smaller than that of the hard mask layer 80. . The selective etching may include (Such as BCl ₃ , Cl ₂ ) plasma trim the gate layer 50, and use BOE or DHF wet etching to trim the second dielectric layer 35 in the gate structure 31.

Referring to FIG. 10, the gate dielectric layer 40 is formed by heat treatment on the exposed side wall of the gate electrode 50 as shown in the figure. The heat treatment may be a process of thermally oxidizing or thermally nitriding a metal gate using a plasma in an environment of oxygen, nitrogen, N ₂ O, or NH ₃ .

Referring to FIG. 11, a drain layer 70 is deposited on the surface of the substrate 10. The material of the drain layer 70 is Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In, Ti, TiN, TaN, or C. The drain layer 70 may be formed by a process such as CVD, PVD, or sputtering. Therefore, the vacuum gate channel 60 is formed by sealing the source electrode 30, the drain electrode 70, and the gate structure 50, and the air pressure in the vacuum ranges from 0.1 torr to 50 torr.

Referring to FIG. 12, an interlayer dielectric layer 90 is deposited on the surface of the substrate 10. The interlayer dielectric layer 90 is also usually silicon dioxide, and can be formed by processes such as CVD, PECVD, and HDP CVD.

Please refer to FIG. 13, after the flattened interlayer dielectric layer 90 is planarized, the source electrode 30 and the drain electrode 70 are processed by a high-temperature annealing process to make them cylindrical, avoiding edges and corners, resulting in subsequent component processing. Problems such as poor reliability may occur at the edges and corners. The planarization may use a process such as chemical mechanical polishing or etch back. The gas used in the high-temperature annealing process is He, N ₂ , Ar, or H ₂ . The temperature range of the high temperature annealing process is 600 degrees Celsius to 1000 degrees Celsius, for example, 800 degrees Celsius.

In summary, in the vacuum tube flash memory structure and the manufacturing method thereof provided in the embodiments of the present invention, a vacuum is formed in the channel, wherein the gate dielectric layer uses a plasma in the presence of oxygen, nitrogen, N ₂ O, or NH ₃ . It is generated by performing thermal oxidation or thermal nitridation of the gate layer in an environment. The structure disclosed by the invention can make the formed component have better programming, erasing speed and storage time, and can also improve superior gate control performance and extremely small gate leakage current.

The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Any person in the technical field, within the scope not departing from the technical solution of the present invention, make any form of equal replacement or modification of the technical solution and technical content disclosed in the present invention, which all belong to the content without departing from the technical solution of the present invention. , Still belongs to the protection scope of the present invention.

Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. In this way, if these modifications and variations of the present invention fall within the scope of the patent application for the present invention and the scope of equivalent technology, the present invention also intends to include these modifications and variations.

S100 ~ S1100 ‧‧‧ Vacuum tube flash memory structure manufacturing process steps

Claims (14)

A manufacturing method of a vacuum tube flash memory structure includes the steps of: providing a substrate; forming a dielectric layer, a source layer, a second dielectric layer, a gate layer, and a hard curtain layer on the substrate in order; Chemically process the second dielectric layer, the gate layer, and the hard curtain layer to form a gate structure; trim the second dielectric layer and the gate layer in the gate structure to make the remaining second dielectric layer and the gate layer The width is smaller than the hard curtain layer; heat treatment is performed to form a gate dielectric layer on the side wall of the gate layer; deposition of a drain layer; deposition of an interlayer dielectric layer on the entire substrate and planarization to the gate A vacuum was formed. The manufacturing method according to claim 1, further comprising, after the interlayer dielectric layer is planarized, the source layer and the drain layer are processed by high-temperature annealing to make them cylindrical. The manufacturing method as claimed in claim 2, wherein said high-temperature annealing gas used was He, N _2, Ar or H _2. The method of claim 2, wherein a temperature range of the high-temperature annealing is between 600 and 1000 ° C. The manufacturing method according to claim 1, wherein an air pressure in a vacuum in the gate electrode ranges from 0.1 torr to 50 torr. The manufacturing method according to claim 1, wherein the heat treatment is performed by performing a thermal oxidation or a thermal nitridation process of the gate layer under an environment of oxygen, nitrogen, N ₂ O, or NH ₃ using a plasma. The manufacturing method according to claim 1, wherein the source layer and the drain layer are made of Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In, Ti, TiN, TaN, C, and combinations thereof. The manufacturing method according to claim 1, wherein the material of the gate layer is Al, poly Si, Cu, Ga, In, Ti, Ta, W, Co, Ti, Ta, TiN, TaN, and combinations thereof. The manufacturing method according to claim 1, wherein a material of the hard curtain cover layer is silicon oxynitride, silicon nitride, or titanium nitride (TiN). A vacuum tube flash memory structure includes: a substrate; a first dielectric layer and a source layer on the substrate; a gate structure on the source layer, the gate structure includes A gate layer and a hard curtain layer, a gate dielectric layer on a side wall of the gate layer, and a hollow vacuum channel, wherein the width of the gate layer in the gate structure is smaller than that of the hard curtain layer The width of the layer; and a drain layer over the gate structure and closing the vacuum channel. The flash memory structure of a vacuum tube according to claim 10, wherein the source and drain layers are made of Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In, Ti, TiN, TaN, C, and combinations thereof. The flash memory structure of a vacuum tube according to claim 10, wherein the material of the gate layer is Al, poly Si, Cu, Ga, In, Ti, Ta, W, Co, Ti, Ta, TiN, TaN and the like. combination. The flash memory structure of a vacuum tube according to claim 10, wherein the gate dielectric layer is formed by using a plasma to perform thermal oxidation of the gate layer in an environment of oxygen, nitrogen, N ₂ O, or NH ₃ or Generated by thermal nitriding. The flash memory structure of a vacuum tube according to claim 10, wherein the material of the hard curtain cover layer is silicon oxide nitride, silicon nitride, and titanium nitride (TiN).