CN105990229B - Semiconductor devices and its manufacturing process - Google Patents

Semiconductor devices and its manufacturing process Download PDF

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Publication number
CN105990229B
CN105990229B CN201510844545.5A CN201510844545A CN105990229B CN 105990229 B CN105990229 B CN 105990229B CN 201510844545 A CN201510844545 A CN 201510844545A CN 105990229 B CN105990229 B CN 105990229B
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layer
conductive
metal silicide
semiconductor devices
dielectric layer
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CN105990229A (en
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龚伯涵
卢盈静
洪奇成
王喻生
张简旭珂
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)

Abstract

The present invention provides a kind of semiconductor devices comprising the dielectric layer on the gate structure of semiconductor devices.Semiconductor devices further includes conductive interconnection part, is configured to connect the area I/O on gate structure and conductive interconnection part.Semiconductor devices further includes the metal silicide layer being arranged between conductive interconnection part and dielectric layer, wherein metal silicide is the silicide form different from the metal of conductive interconnection part.The present invention also provides a kind of methods being used for producing the semiconductor devices.

Description

Semiconductor devices and its manufacturing process
Technical field
This patent disclosure relates generally to semiconductor fields, conductive interconnection part structure more particularly, to semiconductor devices and its Manufacturing process.
Background technique
As semiconductors manufacture and processing industry have been developed to advanced technology node, it is found that integrated level is continuous It improves, device component reduces and constantly enhances the requirements at the higher level of device performance.
In the manufacturing process of semiconductor chip, conductive interconnection part structure is widely used for the different components of electrical connection And/or electrical connection external circuit.With the lasting diminution of characteristic size, the requirement of reliability and performance to conductive interconnection part becomes It obtains tightened up.Advanced manufacturing technology is studied to improve the integrality of conductive interconnection part and the system performance of semiconductor chip.
Summary of the invention
According to an aspect of the invention, there is provided a kind of semiconductor devices, comprising: dielectric layer is located at semiconductor devices Gate structure on；Conductive interconnection part is configured to connect gate structure and the area I/O on conductive interconnection part；With And metal silicide layer, it is arranged between conductive interconnection part and dielectric layer, metal silicide is the gold different from conductive interconnection part The silicide form of category.
Preferably, the semiconductor devices further include: conductive layer is arranged between conductive interconnection part and metal silicide layer, Wherein, conductive layer is metal.
Preferably, semiconductor devices further include: silicon layer is located inside dielectric layer, wherein silicon layer is located at metal silicide Between layer and dielectric layer.
Preferably, silicon layer is additionally arranged at the outer of metal silicide layer and places.
Preferably, the thermal expansion coefficient (CTE) of conductive interconnection part is greater than the CTE of metal silicide layer, and metal silication The CTE of nitride layer is greater than the CTE of dielectric layer.
Preferably, conductive layer includes one in cobalt, nickel, tungsten, molybdenum, titanium, platinum and tantalum.
Preferably, conductive interconnection part includes copper.
Preferably, the ratio of the thickness between dielectric layer and metal silicide layer is between 1 to 200.
According to another aspect of the present invention, a kind of semiconductor devices is provided, comprising: the first dielectric layer；Conductive interconnection part, It is arranged in the first dielectric layer；Metal silicide layer is arranged on conductive interconnection part；Silicon layer is arranged in metal silicide layer Outer place；And second dielectric layer, it is arranged on metal silicide layer and silicon layer.
Preferably, silicon layer is arranged between metal silicide layer and the second dielectric layer.
Preferably, the thermal expansion coefficient (CTE) of conductive interconnection part is greater than the CTE of metal silicide layer, and metal silication The CTE of nitride layer is greater than the CTE of the first dielectric layer and the second dielectric layer.
Preferably, conductive interconnection part includes the first metal, and metal silicide layer is second different from the first metal The silicide form of metal.
Preferably, the second metal includes one in cobalt, nickel, tungsten, molybdenum, titanium, platinum and tantalum.
Preferably, semiconductor devices further include: conductive layer, conductive layer include the second metal, and are arranged conductive mutual Even between part and metal silicide layer.
According to another aspect of the invention, a kind of method being used for producing the semiconductor devices is provided, comprising: provide lining Bottom；Gate structure is formed on the substrate；The first dielectric layer is formed on the gate structure of semiconductor devices；In the first dielectric layer Groove in formed conductive interconnection part, thus expose conductive interconnection part not by the first dielectric layer cover surface；In exposure Conductive material is formed on surface；And by making conductive material and silicon react, metal silicide layer is formed as into conduction material The silicide form of material.
Preferably, metal silicide layer is formed as to the silicide of conductive material by making conductive material and silicon react Form further includes heating substrate.
Preferably, this method further include: the second dielectric layer is formed on conductive material, and in the second dielectric layer phase that formed Between silicon be transferred in metal silicide layer.
Preferably, this method further include: silicon layer is formed on conductive material, wherein silicon layer offer is used to form metallic silicon The silicon of compound layer.
Preferably, this method further include: the second dielectric layer is formed on silicon layer.
Preferably, during forming the second dielectric layer on silicon layer, metal silicide layer is formed as to the silication of conductive material Object form.
Detailed description of the invention
When reading in conjunction with the accompanying drawings, each side that the present invention may be better understood according to the following detailed description Face.It is emphasized that according to the standard practices in industry, being not necessarily to scale all parts.In fact, in order to clearly It discusses, can arbitrarily increased or decrease the size of all parts.
Figure 1A to Fig. 1 L is the sectional view of the operation being used for producing the semiconductor devices according to some embodiments of the present invention.
Fig. 2 is to show the schematic diagram of semiconductor manufacturing platform according to some embodiments of the present invention.
Fig. 3 is to show the flow chart of the operation being used for producing the semiconductor devices according to some embodiments of the present invention.
Fig. 4 is to show the flow chart of the operation being used for producing the semiconductor devices according to some embodiments of the present invention.
Fig. 5 is to show the flow chart of the operation being used for producing the semiconductor devices according to some embodiments of the present invention.
Specific embodiment
Following disclosure provides the different embodiments or example of a variety of different characteristics for realizing provided theme. The particular instance of component explained below and arrangement is to simplify the present invention.Certainly, these are only examples and are not intended to be limited to this Invention.For example, in the following description, above second component or the upper formation first component may include the first component and second The embodiment that part directly contacts also may include that additional component can be formed between the first component and second component and make The embodiment that one component and second component are not directly contacted with.In addition, the present invention can in various embodiments repeated reference symbol and/ Or character.This repetition is for purposes of simplicity and clarity, and itself not indicate each embodiment and/or configuration Between relationship.
In addition, can be used herein such as " ... under ", " in ... lower section ", " below ", " in ... top " and " on Face " etc. spatial relation term, readily to describe an element or component shown in figure and another element (multiple members Part) or component (multiple components) relationship.In addition to orientation shown in figure, spatial relation term is intended to include use or operation In device different orientation.Device can be positioned in other ways and (be rotated by 90 ° or in other orientation), and by This spatial relation description used symbol is interpreted accordingly.
Figure 1A to Fig. 1 L be according to some embodiments of the present invention be used for producing the semiconductor devices 100 operation section Figure.A referring to Fig.1 provides semiconductor substrate 102.Semiconductor substrate 102 includes the semiconductor material of silicon, SiGe etc..Half Conductor substrate 102 can be lightly doped with n-type impurity to become p-type silicon substrate (substrate P).In addition, semiconductor substrate 102 can also be adulterated There is p-type impurity to become n-type silicon substrate (n-substrate).In some embodiments, semiconductor substrate 102 include such as crystalline silicon or The elemental semiconductor of crystal germanium, polycrystalline structure or non crystalline structure.In some embodiments, semiconductor substrate 102 can be such as GaAs (GaAs), gallium phosphide (GaP), silicon carbide (SiC), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb) Compound semiconductor.In other embodiments, semiconductor substrate 102 can be such as SiGe (SiGe), gallium arsenide phosphide (GaAsP), aluminum gallium arsenide (AlGaAs), aluminium indium arsenide (AlInAs), germanium indium arsenide (GaInAs), InGaP (GaInP), And/or the alloy semiconductor or any other suitable material of indium gallium arsenide phoshide (GaInAsP).
In some embodiments, semiconductor substrate 102 can be silicon-on-insulator (SOI) substrate.Skill is isolated using note oxygen Art (SIMOX), wafer engagement, and/or other suitable methods manufacture SOI substrate.In some instances, semiconductor substrate 102 Epitaxial layer or buried layer including doping.In other instances, semiconductor substrate 102 has multilayer compound structure.
In fig. ib, such as various isolated parts 12 of shallow trench isolation (STI) or local oxidation of silicon (LOCOS) formation In the semiconductor substrate 102 to separate each device.It is shown in FIG. 1 each to limit and be electrically isolated to form isolated part 12 Active area.For example, isolated part 12 can limit the region of complementary metal oxide semiconductor (CMOS) device, core N-shaped MOS (NMOS) region of device, the region of core p-type MOS (PMOS) device and for the various microelectronics devices in integrated circuit Other regions of part.It should be understood that following disclosed several techniques form the semiconductor substrate for being used for some other types of devices The corresponding component in some other active areas on 102.Isolated part 12 may include silica (SiOX), silicon nitride (SiN), nitrogen Silica (SiON), air gap, other suitable materials or their combination.
Then, the first doped region 13 is formed in the semiconductor substrate 102.In addition, the second doped region 14 is in semiconductor substrate It is formed in 102 adjacent to some isolated parts 12.First doped region 13 and the second doped region 14 can be PMOS, NMOS or The source area of CMOS transistor or drain region.First doped region 13 and the second doped region 14 include highly enriched dopant and shape As the p-type area with boron or with the n-type area of phosphorus.First doped region 13 and the second doped region 14 can be for example, by thermal expansion day labors The various techniques of skill are formed.First doped region 13 and the second doped region 14 can pass through multiple operation shapes that are known or will developing At these operations are to grow sacrifical oxide such as in semiconductor substrate 102, in the first doped region 13 or the second doped region 14 In position at (multiple positions) form patterns of openings, implanted dopant and annealing.
In some embodiments, according to design specification well known in the prior art, semiconductor substrate 102 may include various traps Area's (not shown).Each well region is formed with p well structure, n well structure or Dual Well Structure.Doping concentration is lower than first in these well regions Doped region 13 or the second doped region 14.P well structure is formed by p-type dopant to mix around the first doped region of N-shaped 13 or N-shaped second Miscellaneous area 14.Optionally, n well structure is formed by n-type dopant around p-type the firstth area 13 or the second doped region 14.
In fig. ib, interlayer dielectric (ILD) layer 104 is formed in semiconductor substrate 102.ILD layer 104 includes MOS crystal Each section of pipe, such as gate structure 15, the first side wall spacer 18 and second sidewall spacer 19 and 21 and of conductive plunger 22。
Gate structure 15 is arranged in semiconductor substrate 102.Gate structure 15 may include being arranged in semiconductor substrate 102 Gate-dielectric 16 and the gate electrode 17 that is arranged on gate-dielectric 16.
Gate-dielectric 16 as the layer being located in semiconductor substrate 102 may include silicon oxide layer.Optionally, grid electricity Medium 16 may be selected to include high-k dielectric material, silica, silicon nitride, silicon oxynitride, other suitable materials or their group It closes.High-g value can be selected from metal oxide, metal nitride, metal silicate, transition metal oxide, transitional metal nitride Object, transition metal silicate, the nitrogen oxides of metal, metal aluminate, zirconium silicate, zirconium aluminate, hafnium oxide or their combination. The example of high dielectric material includes HfO2、HfSiO、HfSiON、HfzrO、LaO、BazrO、HfLaO、HfSiO、LaSiO、 AlSiO, HfTaO, HfTiO, zirconium oxide, aluminium oxide, other suitable high-k dielectric materials and/or their combination.In some realities It applies in example, gate-dielectric 16 can have multilayered structure, such as a silicon oxide layer and another high-k material layer.Grid electricity is situated between Matter 16 can be formed on boundary layer by any appropriate technique.
Gate electrode 17 is arranged on gate-dielectric 16.Gate electrode 17 include conductive material, such as aluminium, copper, titanium, tantalum, tungsten, Molybdenum, tantalum nitride, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloy, other suitable materials and/or they Combination.In some embodiments, the amorphous silicon or polysilicon using heavy doping may be selected.In this case, such as boron or phosphorus High-concentration dopant object can be used to form gate electrode 17.In some embodiments, silicon layer is used as the grid material of gate structure 15. Silicide layer (not shown) is sent out by silicon and such as conductive material of tungsten, Ti, Pt, Ta, Nb, Hf, Mo or other suitable metals Life is reacted and is formed on gate electrode layer 17.
Gate structure 15 has the first side wall spacer 18 of gate structure 15 and the first side relative to gate structure 15 The second sidewall spacer 19 that wall spacer 18 is arranged.The first side wall is formed by the dielectric material of such as silicon nitride or silica Spacer 18 and second sidewall spacer 19.18 He of the first side wall spacer of different shapes can be formed in upper part or slope Second sidewall spacer 19.It can be formed on gate structure 15 and semiconductor substrate 102 by depositing the film of such as silicon nitride The first side wall spacer 18 and second sidewall spacer 19.Then, remain in 102 table of semiconductor substrate using etch process removal Thin-film material on face leaves the first side wall spacer 18 and second sidewall spacer 19.
B referring to Fig.1, ILD layer 104 further include conductive plunger 21 and conductive plunger 22.Conductive plunger 21 may be formed at first The top of doped region 13.First doped region 13 is electrically connected to the conduction that each layer is covered in semiconductor devices 100 by conductive plunger 21 Material.Similarly, the second doped region 14 is electrically connected to the conduction material that each layer is covered in semiconductor devices 100 by conductive plunger 22 Material.Conductive plunger 21 and 22 is formed by such as aluminium, copper, the conductive material of tungsten or other suitable metals.Conductive plunger 21 and 22 It can be formed by the suitable technique of such as low-pressure chemical vapor deposition (LPCVD) or sputtering.
In some embodiments, diffusion barrier layer (not shown) is formed in conductive plunger 21 and 22 and semiconductor substrate 102 Between.For example, titanium, titanium nitride or tungsten-tungsten can be used to form diffusion barrier layer.Diffusion barrier layer can by sputtering, CVD or other Suitable technique is formed.
ILD 104 further includes each component for being electrically isolated in ILD layer 104 and is electrically isolated ILD104 and semiconductor lining The dielectric material at bottom 102.The suitable technique such as deposited can be used to form dielectric material.Then, by flatening process application In ILD layer 104 to be used for further technique.
B referring to Fig.1, dielectric layer 105 are arranged on ILD layer 104.Dielectric layer 105 include some materials, such as silica, Silicon nitride (SiN), silicon oxynitride, silicon oxide carbide (SiOC), silicon carbide, fluorided silica (SiOF), carbon doped silicon oxide (example Such as, SiOCH), spin-coating glass (SOG), noncrystal carbon fluoride, fluorosilicate glass (FSG), polyimides, BCB it is (double to chloromethyl Benzene), pore-free material, porous material and/or their combination.In some embodiments, dielectric layer 105 includes high-density plasma Body (HDP) dielectric material (for example, HDP oxide) and/or high-aspect-ratio technique (HARP) dielectric material are (for example, HARP is aoxidized Object).In some embodiments, dielectric layer 105 is the dielectric film by planarization.
Dielectric layer 105 is formed by suitable depositing operation, and suitable depositing operation may include chemical vapor deposition (CVD), physical vapor deposition (PVD), ionization PVD (IPVD) and atomic layer deposition (ALD).In addition, other techniques include height Density plasma CVD (HDPCVD), metallorganic CVD (MOCVD), remote plasma cvd (RPCVD), plasma increase Strong CVD (PECVD), LPCVD, thermal oxide, UV- ozone oxidation, epitaxial growth method (for example, selective epitaxial growth), sputtering, Plating method, rotary coating, other suitable methods and/or their combination.In one embodiment, dielectric layer 105 has aboutTo aboutBetween suitable thickness range.
In fig. 1 c, groove 107 and groove 108 are formed to be formed by applying suitable etch process to dielectric layer 105 Patterned dielectric layer 106.Groove 108 may include the groove and through-hole structure stacked.In some embodiments, photoresist layer is logical The suitable technique for crossing such as photoetching or other alternative techniques is formed on dielectric layer 105 and by photoengraving pattern appropriate Change method is patterned to form photoetching glue component.Photoresist process can also by such as maskless lithography technique, electron beam be written, Other appropriate methods of ion beam write-in and/or molecule imprinting are implemented or are replaced.In some embodiments, photoresist process can wrap Baking process and formation after including and form photoresist layer on dielectric layer 105, photoresist is exposed to pattern, executing exposure Mask element including photoresist.In one embodiment, dual damascene technology can be used, wherein middle etch stop layer can shape Groove-through-hole structure hard mask as the stacking for groove 18.
Later, reactive ion etching (RIE) technique and/or other etch process etching groove 107 and recessed then can be used Slot 108.Etch process may include dry ecthing, wet etching and/or other engraving methods (for example, reactive ion etching).Etch work Skill can be also pure chemistry (plasma etching), pure physics (ion grinding) and/or their combination.
Dry etching process can be implemented in etching chamber.It can control the thickness of different components by adjusting some technological parameters, Technological parameter include radio frequency (RF) source power, bias power, electrode size, pressure, flow velocity, etching period, wafer temperature, other Suitable technological parameter and/or their combination.The implementable oxygen-containing gas of dry etching process, fluoro-gas are (for example, CF4、SF6、 CH2F2、CHF3And/or C2F6), chlorine-containing gas is (for example, Cl2、CHCl3、CCl4, and/or BCl3), bromine-containing gas (for example, HBr, He and/or CHBr3), gas containing iodine, other suitable gases and/or plasma and/or their combination.In some implementations In example, dry etching process uses O2Corona treatment and/or O2/N2Corona treatment.In addition, dry etching process is executable A period of time appropriate.
The HF solution for hydrofluoric acid (HF) impregnation technology can be used in wet etching process.In some embodiments, wet etching Diluted hydrofluoric acid can be applied to intermediate semiconductor structures by technique.In some embodiments, wet etching process includes being exposed to Hydroxide solution containing ammonium hydroxide, diluted HF, deionized water and/or suitable etchant solutions.
It is formed after groove 107 and groove 108 on patterned dielectric layer 106, hereafter peelable photoresist.Later, Diffusion barrier layer (not shown) may be optionally formed in the bottom and side wall of groove 107 and groove 108.Common diffusion barrier gold Belong to or alloy includes tantalum, nickel, hafnium, niobium, zirconium, vanadium, tungsten, nichrome and titanium tungsten.In addition, it is also possible to consider conductivity ceramics, such as Indium oxide, copper silicide, tungsten nitride and titanium nitride.The appropriate deposition for being used to form diffusion barrier layer discussed above can be used Technique, such as CVD, ALD and PVD.The thickness that diffusion barrier layer has is aboutTo aboutBetween.However, should Understand, the size that the present invention quotes in the whole text is by the bi-directional scaling according to manufacturing technology used.
Fig. 1 D is the step being filled into conductive material in groove 107 and groove 108.Then it conductive interconnection part 112 and leads Electrical interconnection 114 is respectively formed in groove 107 and groove 108.Conductive interconnection part 112 is formed to be electrically connected patterned dielectric Each component in layer 106.Similarly, conductive interconnection part 114, which is formed in, is electrically connected following each layer in groove 108.Some In embodiment, conductive interconnection part 112 and conductive interconnection part 114 are configured to connect gate structure 15 and are located at conductive interconnection part 112 and conductive interconnection part 114 on the area input/output (I/O) (not shown).For conductive interconnection part 112 and conductive interconnection The conductive material of part 114 includes copper, aluminium or other suitable materials.
In one embodiment, it is formed before conductive interconnection part 112 and conductive interconnection part 114, seed layer optionally forms On the wall of groove 107 and groove 108.Common materials for seed layer include the change of Pd or other polymers and organic material Close object.Seed layer can be formed by the appropriate process of such as PVD by deposition.
It is formed after conductive interconnection part 112 and conductive interconnection part 114, uses suitable flatening process.In some implementations In example, patterned dielectric layer 106 and conductive interconnection part 112 and conductive interconnection part 114 are planarized.In addition, dielectric layer 106 with And conductive interconnection part 112 and conductive interconnection part 114 it is coplanar in favor of subsequent technique.Flatening process can be chemical machinery throwing Light (CMP) operation.
E referring to Fig.1, conductive layer 110 are deposited on conductive interconnection part 112 and conductive interconnection part 114.In some embodiments In, conductive layer 110 is formed between conductive interconnection part 112 or 114 and each layer of such as the upper surface of dielectric layer.Conductive layer 110 is used for Prevent the conductive material (such as copper) in conductive interconnection part 112 and conductive interconnection part 114 from diffusing into the dielectric material of surrounding.It leads Electric layer 110 is formed by conductive material, such as cobalt, nickel, tungsten, molybdenum, titanium, platinum, tantalum, other suitable materials and or their combination.
The thickness of conductive layer 110 is aboutTo aboutBetween.It is used to form the suitable deposition work of conductive layer 110 Skill includes CVD, ALD and other suitable techniques.In some embodiments, conductive layer 110 can be selected deposition extremely by depositing operation On the surface of the opening of conductive interconnection part 112 and conductive interconnection part 114, with conductive interconnection part 112 and the conductive interconnection part of being electrically insulated 114.Also, selection deposition provides its in conductive interconnection part 112 and conductive interconnection part 114 and patterned dielectric layer 106 Insulation between his conductive interconnection part.
F referring to Fig.1, silicon layer 116 are deposited on conductive layer 110.In one embodiment, 116 overlay pattern of silicon layer Dielectric layer 106.The thickness of silicon layer 116 is aboutTo aboutBetween.Suitable depositing operation includes using silane (SiH4) or disilane (Si2H6) CVD as silicon precursor.Optionally, silicon layer 116 can be by using silicon as material source (target) PVD process and formed.
G referring to Fig.1 forms metal silicide layer 118 in the interface of silicon layer 116 and conductive layer 110.In one embodiment In, the periphery of metal silicide layer 118 is arranged in silicon layer 116.Silicon layer 116 is to form metal silicide layer 118 to provide silicon.Metal Silicide layer 118 by silicon atom from silicon layer 116 with include that metal in conductive layer 110 is formed and reacting.Gold Belonging to silicide layer 118 may include Co2Si、CoSi、CoSi2、NiSi、NiSi2、WSi2、MoSi2、TiSi2、PtSi、TaSi2, other Suitable material and/or their combination.
Metal silicide layer 118 is formed on conductive interconnection part 112 and conductive interconnection part 114.In one embodiment, When consuming the conductive material contacted with conductive layer 110 in forming metal silicide layer 118, metal silicide layer 118 is by shape At on conductive interconnection part 112 and conductive interconnection part 114.It is arranged in the part of conductive layer 110 in conductive interconnection part 112 and conduction In another embodiment on interconnection piece 114, metal silicide layer 118 is formed between silicon layer 116 and conductive layer 110.One In a embodiment, metal silicide layer 118 is arranged on the surface of conductive interconnection part 112 and conductive interconnection part 114.
H referring to Fig.1, the second dielectric layer 220 are formed on metal silicide layer 118.In one embodiment, the second dielectric Layer 220 is deposited on patterned dielectric layer 106.Second dielectric layer 220 can be deposited on silicon layer 116.In one embodiment, The material for being used to form the second dielectric layer 220 is identical as the material for being used to form patterned dielectric layer 106.In another implementation In example, when consuming the silicon of silicon layer 116 with the metal of the contact silicon in conductive layer 110 simultaneously, metal silicide layer 118 can be formed Between the second dielectric layer 220 and conductive interconnection part 112 and conductive interconnection part 114.The thickness of second dielectric layer 220 is aboutTo aboutBetween.In one embodiment, the thickness between the second dielectric layer 220 and metal silicide layer 118 Ratio is between 1 to 200.
In one embodiment, it executes during forming the second dielectric layer 220 on silicon layer 116 by metal silicide layer 118 The step of being formed as the silicide form of the conductive material of conductive layer 110.
In one embodiment, the thermal expansion coefficient (CTE) of silicon layer 116 is between about 2ppm/ DEG C to about 3.3ppm/ DEG C, For example, 2.6ppm/ DEG C.In another embodiment, the CTE of the second dielectric layer 220 about 0.1ppm/ DEG C to about 5ppm/ DEG C it Between, for example, 1ppm/ DEG C.In some embodiments, the CTE of conductive layer 110 is between about 4.5ppm/ DEG C to about 9ppm/ DEG C, example Such as 6.3ppm/ DEG C, or in about 13ppm/ DEG C to about 14ppm/ DEG C, such as 13.5ppm/ DEG C.In one embodiment, conductive mutual Even the CTE of part 112 or conductive interconnection part 114 is between about 16ppm/ DEG C to about 24ppm/ DEG C.In one embodiment, metallic silicon The CTE of compound layer 118 is between about 6.5ppm/ DEG C to about 9.5ppm/ DEG C or between about 9.5ppm/ DEG C to about 15ppm/ DEG C.
In some instances, the CTE of conductive interconnection part 112 or conductive interconnection part 114 is greater than metal silicide layer 118 CTE.In some instances, the CTE of metal silicide layer 118 is greater than the CTE of silicon layer 116.In some instances, metal silicide The CTE of layer 118 is greater than the CTE of the second dielectric layer 220.In some instances, the CTE of metal silicide layer 118 is greater than patterning Dielectric layer 106 CTE.
In some instances, the ratio of the CTE between metal silicide layer 118 and the second dielectric layer 220 is greater than metallic silicon The ratio of CTE between compound layer 118 and silicon layer 116.In some instances, conductive interconnection part 112 and the second dielectric layer 220 it Between the ratio of CTE be greater than the ratio of CTE between conductive interconnection part 112 and silicon layer 116.
In one embodiment, metal silicide layer 118 can be formed in situ with the second dielectric layer 220.In other words, do not having It destroys under conditions of vacuum, metal silicide layer 118 and the second dielectric layer 220 can be formed in a same indoor or platform. Optionally, by destroying vacuum in another the second dielectric of indoor formation after an indoor formation metal silicide layer 118 Layer 220.
It in common practice, needs in different indoor formation conductive layer 110 and the second dielectric layer 220, therefore destroys The process sequence of vacuum is inevitable.After conductive layer 110 forms and is detached from vacuum environment, it is found that in the second dielectric Before layer 220 is formed on conductive layer 110, metal oxide layer can be formed.Metal oxide layer by oxygen in atmosphere with Conductive layer 110 reacts and is formed.It is believed that metal oxide layer can lead to the defect of such as bubble or peeling.Therefore, Deteriorate the bonding between conductive layer 110 and the second dielectric layer 220.Due to peel off or bubble, will affect device integrality and Reliability.Conversely, in the present invention, before conductive layer 110 is exposed to oxygen, silicon layer 116 is formed on conductive layer 110, this Sample can prevent the formation of metal oxide layer.This improves the bondings between conductive layer 110 and the second dielectric layer 220 Performance.
Fig. 1 I to Fig. 1 J is the sectional view of process for fabrication of semiconductor device in accordance with some embodiments.Fig. 1 I to Fig. 1 J is shown Substitution operating procedure after operating procedure shown in Fig. 1 F.I referring to Fig.1, before forming metal silicide layer 118, the Two dielectric layers 220 are deposited on silicon layer 116.In one embodiment, the second dielectric layer 220 is patterned dielectric layer 106 Covering part.In another embodiment, silicon layer 116 is arranged between patterned dielectric layer 106 and the second dielectric layer 220. In addition, the second dielectric layer 220 is arranged on conductive layer 110.In one embodiment, conductive layer 110 is arranged patterned Between dielectric layer 106 and the second dielectric layer 220.
J referring to Fig.1, metal silicide layer 118 are formed in the second dielectric layer 220 and conductive interconnection part 114 or conductive interconnection Between part 112.In some embodiments, the suitable technique for forming metal silicide layer 118 includes annealing process, such as, is added Hot semiconductor substrate 102.
In one embodiment, metal silicide layer 118 is formed on conductive layer 110.In another embodiment, metal Silicide layer 118 is formed on the surface between silicon layer 116 and conductive layer 110.In yet another embodiment, metal silicide layer 118 are formed between silicon layer 116 and conductive interconnection part 112 and conductive interconnection part 114.
Fig. 1 K to Fig. 1 L is the sectional view of process for fabrication of semiconductor device in accordance with some embodiments.Fig. 1 K to Fig. 1 L is shown The substitution operating procedure after operating procedure shown in Fig. 1 E.The part of K referring to Fig.1, the second dielectric layer 220 are formed in pattern On the dielectric layer 106 of change.In this case, using the second dielectric layer 220 rather than form silicon layer 116 shown in Fig. 1 F and prevent Block gas reacts with the metal in conductive layer 110.In one embodiment, the second dielectric layer 220 is patterned dielectric The covering part of layer 106.Second dielectric layer 220 is arranged on conductive layer 110.In another embodiment, conductive layer 110 is set It sets between patterned dielectric layer 106 and the second dielectric layer 220.
During the operation shown in Fig. 1 K (forming the part of the second dielectric layer 220), also opened from the surface of conductive layer 110 Beginning forms metal silicide layer 118.Due to the second dielectric layer 220, the silicon in the second dielectric layer 220 is forming the second dielectric layer It is transferred into metal silicide layer 118 during 220.In one embodiment, metal silicide layer 118 is formed in the second dielectric layer Between 220 and conductive layer 110.
E and Fig. 1 K referring to Fig.1, in the case where not destroying vacuum, the second dielectric layer 220 and metal silicide layer 118 with Conductive layer 110 is formed in situ.In addition, metal silicide layer 118 is formed as leading by execution during forming the second dielectric layer 220 The step of silicide form of conductive material in electric layer 110.
L referring to Fig.1 forms entire second dielectric layer 220 and entire metal silicide layer 118.
Fig. 2 shows the schematic diagrames of semiconductor manufacturing platform 200 in accordance with some embodiments.Semiconductor manufacturing platform 200 Including the first tool 202, the second tool 204 and channel 206.
First tool (tool) 202 includes the first Room 210 for accommodating the semiconductor crystal wafer for conductive technique.First tool 202 are configured to execute semiconductor crystal wafer the operation of the semiconductors manufacture as shown in Figure 1A to Fig. 1 L.In order to illustrate showing One Room 210, and optionally using the different configurations with more multicell in the first tool 202.Similarly, the second tool 204 Second Room 212 including accommodating semiconductor crystal wafer.In one embodiment, the manufacturing process executed in the first tool 202 can not It is same as the manufacturing process executed in the second tool 204.
Channel 206 is arranged between the first tool 202 and the second tool 204.Channel 206 includes robotic arm 208, is matched Mobile semiconductor crystal wafer is set between the first tool 202 and the second tool 204.In one embodiment, channel 206 is configured Under the conditions of low pressure or vacuum.The air pressure of channel 206 is positively retained at 0.1torr or less.When in the first tool 202 and the second tool When being sequentially performed two or more different process in 204, channel 206 provides virtual vacuum tunnel, by the tunnel, can control The pollution caused by undesirable reactant (such as, oxygen).For example, the operation being sequentially performed in Fig. 1 E and Fig. 1 K can divide It is not carried out in the first tool 202 and the second tool 204.The operation of these sequences needs the working environment without destroying vacuum, To prevent from forming metal oxide layer on conductive layer 110.In this case, after forming conductive layer 110, using ditch Road 206 moves semiconductor crystal wafer without destroying vacuum condition.
Fig. 3 is to show the flow chart of semiconductor fabrication process in accordance with some embodiments.In operation 310, half is provided The semiconductor substrate 102 of conductor device 100.In operation 320, at least one transistor is formed in semiconductor substrate 102.It is brilliant Body pipe includes gate structure, source area and drain region.
In operation 330, dielectric layer 105 is etched to form groove 107 and groove 108, so that patterned dielectric layer 106 It is formed on the gate structure of semiconductor devices 100.Then, in operation 340, conductive interconnection part 112 and conductive interconnection part 114 are respectively formed in groove 107 and groove 108 in patterned dielectric layer 106.It exposes conductive interconnection part 112 or leads The surface that the dielectric layer 106 of electrical interconnection 114 not being patterned covers.In one embodiment, it conductive interconnection part 112 and leads Electrical interconnection 114 includes the conductive material of such as copper or aluminium.
In operation 350, the conductive layer 110 with such as conductive material of cobalt, nickel, tungsten, molybdenum, titanium, platinum and tantalum is formed in On the exposed surface of conductive interconnection part 112 or conductive interconnection part 114.In one embodiment, conductive material is formed in exposed table On face.
In operation 360, silicon layer 116 is formed on conductive layer 110.The offer of silicon layer 116 is used to form metal silicide layer 118 silicon.In operation 370, metal silicide layer 118 is formed as the conduction material of conductive interconnection part 112 or conductive interconnection part 114 The silicide form of material.Metal silicide layer 118 reacts to be formed with silicon by conductive material.In one embodiment, Technique for example, by heating substrate makes conductive material and silicon in conductive layer 110 react to form metal silicide layer 118.
In operation 380, the second dielectric layer 220 is formed on silicon layer 116.In one embodiment, the second dielectric layer 220 It is formed on patterned dielectric layer 106.In one embodiment, it during forming the second dielectric layer 220 on silicon layer 116, holds It is about to the step of metal silicide layer 118 is formed as the silicide form of conductive material.
Fig. 4 is to show the flow chart of semiconductor fabrication process in accordance with some embodiments.Operation in reference Fig. 4, Fig. 4 310 to 360 show in the operation 310 to 360 of Fig. 3.After operation 360, in act 410, the formation of the second dielectric layer 220 On silicon layer 116.In operation 420, metal silicide layer 118 is formed between conductive layer 110 and the second dielectric layer 220.
Fig. 5 is to show the flow chart of semiconductor fabrication process in accordance with some embodiments.Referring to Fig. 5, the operation of Fig. 5 310 to 350 show in the operation 310 to 350 of Fig. 3.After operation 350, in operation 510, the portion of the second dielectric layer 220 Divide and is formed on silicon layer 116.In operation 520, metal silicide layer 118 be formed in conductive layer 110 and the second dielectric layer 220 it Between.Metal silicide layer 118 is formed during forming the second dielectric layer 220.In one embodiment, it is formed in operation 510 During the technique of second dielectric layer 220, metal silicide layer 118 is formed in the position that silicon is transferred to metal silicide layer 118 Place.
Some embodiments of the present invention provide semiconductor devices comprising on the gate structure of semiconductor devices Dielectric layer.Conductive interconnection part is configured to connect gate structure and the area I/O on conductive interconnection part.Metal silicide Layer is arranged between conductive interconnection part and dielectric layer, and metal silicide is the silicide different from the metal of conductive interconnection part Form.
Some embodiments of the present invention provide semiconductor devices comprising the first dielectric layer.The setting of conductive interconnection part exists In first dielectric layer.Metal silicide layer is arranged on conductive interconnection part.The periphery of metal silicide layer is arranged in silicon layer, and And second dielectric layer be arranged on metal silicide layer and silicon layer.
Some embodiments of the present invention provide the method being used for producing the semiconductor devices, and this method includes providing substrate. This method further includes that gate structure is formed on the substrate.This method further includes that is formed on the gate structure of semiconductor devices One dielectric layer.In addition, this method includes the formation conductive interconnection part in the groove of the first dielectric layer, to expose conductive interconnection The surface of part not covered by the first dielectric layer.This method further includes forming conductive material on the exposed surfaces, and pass through anti- Answer conductive material and silicon that metal silicide is formed as to the silicide form of conductive material.
The component of several embodiments is discussed above so that those skilled in the art may be better understood it is of the invention Various aspects.It should be appreciated by those skilled in the art easily can design or change using based on the present invention Other are used to reach purpose identical with embodiment described herein and/or realize the process and structure of same advantage.This field Technical staff it should also be appreciated that this equivalent constructions without departing from the spirit and scope of the present invention, and without departing substantially from this In the case where the spirit and scope of invention, a variety of variations, replacement can be carried out and changed.

Claims (19)

1. a kind of semiconductor devices, comprising:
Dielectric layer, on the gate structure of the semiconductor devices；
Conductive interconnection part is configured to connect the gate structure and the area I/O on the conductive interconnection part；And
Metal silicide layer, be arranged between the conductive interconnection part and the dielectric layer, the metal silicide be different from The silicide form of the metal of the conductive interconnection part；
Conductive layer is arranged between the conductive interconnection part and the metal silicide layer, wherein the conductive layer is the gold Belong to.
2. semiconductor devices according to claim 1, further includes: silicon layer is located inside the dielectric layer, wherein described Silicon layer is between the metal silicide layer and the dielectric layer.
3. semiconductor devices according to claim 2, wherein the silicon layer is additionally arranged at the outer of the metal silicide layer It places.
4. semiconductor devices according to claim 1, wherein the thermal expansion coefficient CTE of the conductive interconnection part is greater than institute The thermal expansion coefficient CTE of metal silicide layer is stated, and the thermal expansion coefficient CTE of the metal silicide layer is greater than the dielectric The thermal expansion coefficient CTE of layer.
5. semiconductor devices according to claim 1, wherein the conductive layer includes cobalt, nickel, tungsten, molybdenum, titanium, platinum and tantalum In one.
6. semiconductor devices according to claim 1, wherein the conductive interconnection part includes copper.
7. semiconductor devices according to claim 1, wherein the thickness between the dielectric layer and the metal silicide layer The ratio of degree is between 1 to 200.
8. a kind of semiconductor devices, comprising:
First dielectric layer；
Conductive interconnection part is arranged in first dielectric layer；
Conductive layer is arranged above the conductive interconnection part；
Metal silicide layer, setting is above the conductive layer；
Silicon layer is arranged in the outer of the metal silicide layer and places；And
Second dielectric layer is arranged on the metal silicide layer and the silicon layer.
9. semiconductor devices according to claim 8, wherein silicon layer setting is in the metal silicide layer and described Between second dielectric layer.
10. semiconductor devices according to claim 8, wherein the thermal expansion coefficient CTE of the conductive interconnection part is greater than institute The thermal expansion coefficient CTE of metal silicide layer is stated, and the thermal expansion coefficient CTE of the metal silicide layer is greater than described first The thermal expansion coefficient CTE of dielectric layer and second dielectric layer.
11. semiconductor devices according to claim 8, wherein the conductive interconnection part includes the first metal, and described Metal silicide layer is the bimetallic silicide form different from first metal.
12. semiconductor devices according to claim 11, wherein second metal includes cobalt, nickel, tungsten, molybdenum, titanium, platinum With one in tantalum.
13. semiconductor devices according to claim 11, wherein the conductive layer includes second metal.
14. a kind of method being used for producing the semiconductor devices, comprising:
Substrate is provided；
Gate structure is formed over the substrate；
The first dielectric layer is formed on the gate structure of the semiconductor devices；
Conductive interconnection part is formed in the groove of first dielectric layer, to expose the not described of the conductive interconnection part The surface of first dielectric layer covering；
Conductive material is formed on the exposed surface；And
By making the conductive material and silicon react, metal silicide layer is formed as to the silicide shape of the conductive material Formula；
The second dielectric layer is formed on the conductive material, wherein second dielectric layer, the metal silicide layer and described Conductive material is formed in situ.
15. the method according to claim 14 being used for producing the semiconductor devices, wherein by make the conductive material and The silicon reacts, and the metal silicide layer is formed as the silicide form of the conductive material further includes described in heating Substrate.
16. the method according to claim 14 being used for producing the semiconductor devices, wherein forming second dielectric layer Silicon described in period is transferred in the metal silicide layer.
17. the method according to claim 14 being used for producing the semiconductor devices, further includes: the shape on the conductive material At silicon layer, wherein the silicon layer provides the silicon for being used to form the metal silicide layer.
18. the method according to claim 17 being used for producing the semiconductor devices, further includes: form on the silicon layer Two dielectric layers.
19. the method according to claim 18 being used for producing the semiconductor devices, wherein described in being formed on the silicon layer During second dielectric layer, the metal silicide layer is formed as to the silicide form of the conductive material.
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