TWI587333B - Ceramic capacitor structure - Google Patents
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- TWI587333B TWI587333B TW104121372A TW104121372A TWI587333B TW I587333 B TWI587333 B TW I587333B TW 104121372 A TW104121372 A TW 104121372A TW 104121372 A TW104121372 A TW 104121372A TW I587333 B TWI587333 B TW I587333B
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本發明係提供一種陶瓷電容結構,尤指利用陶瓷圍牆層生胚堆疊覆蓋於至少一電極層表面,讓介電陶瓷體薄化,且透過陶瓷圍牆層緊密結合於電極層表面以避免產生缺陷,以達到減小厚度、提高電容值及避免電氣跳弧之功效。 The invention provides a ceramic capacitor structure, in particular, a ceramic wall layer is used to cover the surface of at least one electrode layer, so that the dielectric ceramic body is thinned, and the ceramic wall layer is tightly bonded to the surface of the electrode layer to avoid defects. In order to achieve the effect of reducing the thickness, increasing the capacitance value and avoiding electrical arcing.
按,隨著電子產業的蓬勃發展,技術也不斷的精進,而研發都朝著輕薄短小的方向改良,是以,不僅是相關的結構、殼體或散熱構件等都在縮小體積,且在電子元件的領域中也是被客戶要求縮小體積,但對電容產品來說,因為有電容值的要求,所以必須在不減少電容值的狀況下縮小體積,才能有效的減少佔用空間,否則體積與電容值變小後,產品內卻需要裝設更多顆的電容,就沒有減少佔用空間的效果了,此外,因為電容會產生跳弧(Arcing)的問題,便需要解決跳弧的問題,所以研發方向就必須同時具有縮小體積、提高電容值及避免跳弧之功效。 According to the booming development of the electronics industry, technology is constantly improving, and research and development are improving in a light, short, and short direction. Therefore, not only related structures, housings, or heat-dissipating components are being reduced in size, but also in electronics. In the field of components, it is also required by customers to reduce the volume. However, for capacitor products, because of the capacitance value, it is necessary to reduce the volume without reducing the capacitance value, so as to effectively reduce the occupied space, otherwise the volume and capacitance values. After it becomes smaller, more capacitors need to be installed in the product, so there is no effect of reducing the space. In addition, since the capacitor will cause arcing, it is necessary to solve the problem of arc jumping, so the research and development direction It must have the effect of reducing the volume, increasing the capacitance value and avoiding arc jumping.
請參閱第十二圖所示,習知的方式為利用印刷方式在陶瓷層A表面製造電極A0,但容易產生高低不平或是凹陷等缺陷,上述缺陷容易造成後續表面絕緣披覆不完全,而產生氣泡與微小孔洞等問題,而氣泡相對於絕緣材料來說介電係數較低,陶瓷材料的等效電容大於絕緣材料 的等效電容大於氣泡的等效電容,使得電場會集中在氣泡中,且隨著氣體壓力大小或其他因素便會讓氣泡內的電場增強,並使得氣泡內的氣體游離化,當陶瓷電容的電壓升高時,氣泡的等效電容最小所以最容易被破壞而產生跳弧,當氣泡被擊穿後便會瞬間短路,則大量電流就會造成破壞,使得陶瓷電容的耐電壓下降,且會連鎖的造成陶瓷材料及絕緣材料的破壞,甚至會產生陶瓷電容燒毀的問題,尤其是W小於T時的邊緣處更是容易產生跳弧。 Referring to the twelfth figure, the conventional method is to fabricate the electrode A0 on the surface of the ceramic layer A by printing, but it is easy to produce defects such as unevenness or depression, and the above defects are likely to cause incomplete surface insulation coating. Problems such as bubbles and tiny holes are generated, and the dielectric coefficient of the bubbles is relatively low with respect to the insulating material, and the equivalent capacitance of the ceramic material is larger than that of the insulating material The equivalent capacitance is greater than the equivalent capacitance of the bubble, so that the electric field will concentrate in the bubble, and with the gas pressure or other factors, the electric field in the bubble will be enhanced, and the gas in the bubble will be freed, when the ceramic capacitor When the voltage rises, the equivalent capacitance of the bubble is the smallest, so it is most likely to be broken and the arc is generated. When the bubble is broken down, it will be short-circuited instantaneously, and a large amount of current will cause damage, so that the withstand voltage of the ceramic capacitor drops, and The interlocking causes the destruction of ceramic materials and insulating materials, and even the problem of burning ceramic capacitors, especially when the edge is smaller than T, it is more likely to cause arc jumping.
是以,便有廠商研發出一種陶瓷電容,請參閱第十三圖所示,其具有塊狀陶瓷層A,陶瓷層A具有中央部A1及其周圍朝上凸起具較大厚度之增厚部A2,陶瓷層A下表面設有平板狀下電極B,陶瓷層A上表面設有上電極C,上電極C具有位於中央部A1上表面之凹陷部C1,凹陷部C1外側延伸彎曲有位於增厚部A2上表面之凸起部C2,其主要是利用增厚部A2來將下電極B與上電極C凸起部C2之距離增大,以提高耐電壓值之目的,此產品雖可解決耐電壓值的問題並縮小體積,但因為增厚部A2讓下電極B與上電極C之距離增大,所以產品的電容值也會隨之降低,且因下電極B周緣與上電極C凸起部C2外周緣仍然會產生高低不平或凹陷之缺陷。 Therefore, some manufacturers have developed a ceramic capacitor, as shown in Fig. 13, which has a bulk ceramic layer A, and the ceramic layer A has a central portion A1 and its surrounding convex upwards with a thicker thickness. In the portion A2, the lower surface of the ceramic layer A is provided with a flat bottom electrode B, the upper surface of the ceramic layer A is provided with an upper electrode C, and the upper electrode C has a depressed portion C1 on the upper surface of the central portion A1, and the outer portion of the depressed portion C1 is extended and curved. The convex portion C2 on the upper surface of the thickened portion A2 mainly uses the thickened portion A2 to increase the distance between the lower electrode B and the raised portion C2 of the upper electrode C to improve the withstand voltage value. Solving the problem of withstand voltage value and reducing the volume, but since the thickening portion A2 increases the distance between the lower electrode B and the upper electrode C, the capacitance value of the product also decreases, and the peripheral electrode of the lower electrode B and the upper electrode C The outer periphery of the raised portion C2 still produces defects of unevenness or depression.
上述陶瓷電容製作後,會在外部塗佈絕緣材料來形成絕緣體,其絕緣體內部會具有氣泡及雜質,而氣泡及雜質相對於絕緣材料來說介電係數較低,是以,上述的陶瓷電容在塗佈絕緣體後,並無法透過絕緣體來避免產生跳弧。 After the ceramic capacitor is fabricated, an insulating material is externally coated to form an insulator, and the inside of the insulator may have bubbles and impurities, and the bubbles and impurities have a low dielectric constant relative to the insulating material, so that the ceramic capacitor is After the insulator is coated, it is not possible to pass through the insulator to avoid arcing.
上述習用之陶瓷電容,因具有諸多問題與缺失,此即為本 發明人與從事此行業者所亟欲改善之目標所在。 The above-mentioned ceramic capacitors have many problems and are missing. The inventor and the people who work in this industry are aiming to improve.
故,發明人有鑑於上述缺失,乃蒐集相關資料,經由多方評估及考量,並以從事於此行業累積之多年經驗,經由不斷試作及修改,始設計出此種陶瓷電容結構的發明專利者。 Therefore, in view of the above-mentioned shortcomings, the inventors have collected relevant materials, and through multi-party evaluation and consideration, and through years of experience in the industry, through continuous trial and modification, the invention patents of such ceramic capacitor structures have been designed.
本發明之主要目的乃在於利用第一介電陶瓷材料製作介電陶瓷體生胚,將電極層印刷於介電陶瓷體生胚上、下表面,再利用第二介電陶瓷材料製成陶瓷圍牆層生胚,由於陶瓷圍牆層堆疊覆蓋於至少一導電層表面,利用陶瓷圍牆層緊密結合於電極層表面來解決製作時表面產生之缺陷,且其缺陷造成絕緣外層披覆不完全,產生氣泡與微小孔洞而易產生電器跳弧之問題,所以就可以減小介電陶瓷體的厚度,進而達到減小產品厚度、提高電容值及避免電氣跳弧之三重功效。 The main object of the present invention is to fabricate a dielectric ceramic body green body by using a first dielectric ceramic material, printing an electrode layer on the upper and lower surfaces of the dielectric ceramic body, and then using the second dielectric ceramic material to form a ceramic wall. The layered embryos are covered by the ceramic wall layer on the surface of at least one of the conductive layers, and the ceramic wall layer is tightly bonded to the surface of the electrode layer to solve the defects generated on the surface of the electrode layer, and the defects cause the insulation layer to be incompletely covered, and bubbles are generated. The tiny holes are easy to cause the arc jump of the electric appliance, so the thickness of the dielectric ceramic body can be reduced, thereby achieving the triple effect of reducing the thickness of the product, increasing the capacitance value and avoiding electric arc jump.
本發明之次要目的乃在於利用第一介電陶瓷材料製成介電陶瓷體,且利用第二介電陶瓷材料製成陶瓷圍牆層,並將陶瓷圍牆層生胚堆疊覆蓋於至少一電極層表面,因為陶瓷圍牆層具有不易因碰撞產生毀損之優點,即可達到避免產品毀損之目的。 A secondary object of the present invention is to form a dielectric ceramic body by using a first dielectric ceramic material, and to form a ceramic wall layer by using a second dielectric ceramic material, and covering the ceramic wall layer with at least one electrode layer Surface, because the ceramic wall layer has the advantage of not being damaged by collision, the purpose of avoiding product damage can be achieved.
1‧‧‧介電陶瓷體 1‧‧‧dielectric ceramic body
2‧‧‧電極層 2‧‧‧electrode layer
3‧‧‧陶瓷圍牆層 3‧‧‧Ceramic wall layer
30‧‧‧鏤空槽 30‧‧‧ empty slots
4‧‧‧導電層 4‧‧‧ Conductive layer
5‧‧‧接腳 5‧‧‧ pins
51‧‧‧對接部 51‧‧‧Docking Department
52‧‧‧焊錫 52‧‧‧ Solder
6‧‧‧絕緣外層 6‧‧‧Insulating outer layer
A‧‧‧陶瓷層 A‧‧‧ceramic layer
A0‧‧‧電極 A0‧‧‧electrode
A1‧‧‧中央部 A1‧‧‧Central Department
A2‧‧‧增厚部 A2‧‧‧ Thickening Department
B‧‧‧下電極 B‧‧‧ lower electrode
C‧‧‧上電極 C‧‧‧Upper electrode
C1‧‧‧凹陷部 C1‧‧‧Depression
C2‧‧‧凸起部 C2‧‧‧ raised parts
第一圖 係為本發明介電陶瓷體生胚之側視剖面圖。 The first figure is a side cross-sectional view of a dielectric ceramic body blank of the present invention.
第二圖 係為本發明印刷電極層後之側視剖面圖。 The second drawing is a side cross-sectional view of the printed electrode layer of the present invention.
第三圖 係為本發明陶瓷圍牆層堆疊後之側視剖面圖。 The third figure is a side cross-sectional view of the ceramic wall layer of the present invention after stacking.
第四圖 係為本發明二次金屬化後之側視剖面圖。 The fourth figure is a side cross-sectional view of the second metallization of the present invention.
第五圖 係為本發明矩形電容夾腳後之俯視圖。 The fifth figure is a top view of the rectangular capacitor clip of the present invention.
第六圖 係為本發明圓形電容夾腳後之俯視圖。 Figure 6 is a top plan view of the circular capacitor of the present invention.
第七圖 係為本發明矩形電容塗佈絕緣外層後之俯視圖。 The seventh figure is a top view of the rectangular capacitor coated insulating outer layer of the present invention.
第八圖 係為本發明圓形電容塗佈絕緣外層後之俯視圖。 The eighth figure is a plan view of the circular capacitor coated with an insulating outer layer of the present invention.
第九圖 係為本發明較佳實施例之步驟流程圖。 Figure 9 is a flow chart showing the steps of a preferred embodiment of the present invention.
第十圖 係為本發明另一實施例之步驟流程圖。 Figure 11 is a flow chart showing the steps of another embodiment of the present invention.
第十一圖 係為本發明另一實施例堆疊後之立體外觀圖。 Figure 11 is a perspective view showing a stacked appearance of another embodiment of the present invention.
第十二圖 係為習用之側視剖面圖。 Figure 12 is a side cross-sectional view of the prior art.
第十三圖 係為另一習用之側視剖面圖。 Figure 13 is a side cross-sectional view of another conventional use.
為達成上述目的及功效,本發明所採用之技術手段及其構造,茲繪圖就本發明之較佳實施例詳加說明其特徵與功能如下,俾利完全瞭解。 In order to achieve the above objects and effects, the technical means and the configuration of the present invention will be described in detail with reference to the preferred embodiments of the present invention.
請參閱第一、二、三、四、五、六、七、八圖所示,由圖中可以清楚看出,其陶瓷電容包括介電陶瓷體1、二電極層2、二陶瓷圍牆層3、二導電層4、二接腳5及絕緣外層6,介電陶瓷體1可為矩形體或是圓板型等幾何形狀塊體,介電陶瓷體1上表面及下表面分別設有電極層2,且二電極層2外側壁對應於介電陶瓷體1之外側壁,至少一電極層2表面再設有罩覆局部電極層2之環狀陶瓷圍牆層3,陶瓷圍牆層3中央具有露出電極層2之鏤空槽30,且陶瓷圍牆層3外側壁為齊平於介電陶瓷體1及電極層2外側壁,鏤空槽30內設有罩覆於電極層2外表面之導電層4,導電層4未超出陶瓷圍牆層3遠離介電陶瓷體1之表面,再於二 陶瓷圍牆層3之相對外側分別設有接腳5,接腳5一端設有延伸越過陶瓷圍牆層3至外部之對接部51,接腳5另端為延伸至導電層4上表面並設有焊錫52,再於介電陶瓷體1、電極層2、陶瓷圍牆層3、鏤空槽30、導電層4及接腳5外部覆蓋有密閉狀之絕緣外層6,且二接腳5之對接部51露出於絕緣外層6外部。 Please refer to the first, second, third, fourth, fifth, sixth, seventh, and eighth diagrams. It can be clearly seen from the figure that the ceramic capacitor includes dielectric ceramic body 1, two electrode layers 2, and two ceramic wall layers. The second conductive layer 4, the two pins 5 and the insulating outer layer 6, the dielectric ceramic body 1 may be a rectangular body or a circular plate type geometric block, and the upper surface and the lower surface of the dielectric ceramic body 1 are respectively provided with an electrode layer. 2, and the outer sidewall of the two-electrode layer 2 corresponds to the outer sidewall of the dielectric ceramic body 1, and the surface of at least one of the electrode layers 2 is further provided with an annular ceramic wall layer 3 covering the local electrode layer 2, and the center of the ceramic wall layer 3 is exposed. The outer side wall of the ceramic layer 2 is flush with the outer side wall of the dielectric ceramic body 1 and the electrode layer 2, and the conductive layer 4 covering the outer surface of the electrode layer 2 is disposed in the hollow groove 30, The conductive layer 4 does not extend beyond the surface of the ceramic wall layer 3 away from the dielectric ceramic body 1, and then The opposite side of the ceramic wall layer 3 is respectively provided with a pin 5, and one end of the pin 5 is provided with an abutting portion 51 extending across the ceramic wall layer 3 to the outside, and the other end of the pin 5 extends to the upper surface of the conductive layer 4 and is provided with solder. 52, further, the dielectric ceramic body 1, the electrode layer 2, the ceramic wall layer 3, the hollow groove 30, the conductive layer 4 and the pin 5 are covered with a sealed insulating outer layer 6, and the abutting portion 51 of the two pins 5 is exposed. Outside the insulating outer layer 6.
請參閱第一、二、三、四、五、六、七、八、九圖所示,上述陶瓷電容於製造之流程步驟為包括:(700)製作介電陶瓷體1生胚,利用介電係數(k)大於20且小於20000之第一介電陶瓷材料製成預定厚度之介電陶瓷體1生胚,第一介電陶瓷材料可為鈦酸鋇為主體的介電材料。 Please refer to the first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth diagrams. The process steps of the above ceramic capacitors are as follows: (700) fabricating a dielectric ceramic body 1 using a dielectric The first dielectric ceramic material having a coefficient (k) greater than 20 and less than 20,000 is made into a dielectric ceramic body 1 having a predetermined thickness, and the first dielectric ceramic material may be a dielectric material mainly composed of barium titanate.
(701)印刷電極層2,將匹配鈦酸鋇膨脹系數的導電材質之電極層2印刷於介電陶瓷體1生胚之上表面及下表面,電極層2與介電陶瓷體1生胚外側壁之間無間距。 (701) printing the electrode layer 2, printing the electrode layer 2 of the conductive material matching the expansion coefficient of the barium titanate on the upper surface and the lower surface of the dielectric ceramic body 1, the electrode layer 2 and the outside of the dielectric ceramic body 1 There is no gap between the walls.
(702)製作陶瓷圍牆層3生胚,利用第二介電陶瓷材料製成陶瓷圍牆層3生胚,第二介電陶瓷材料可為鈦酸鋇為主體的介電材料。 (702) Making a ceramic wall layer 3 raw embryos, using a second dielectric ceramic material to form a ceramic wall layer 3 raw embryos, and the second dielectric ceramic material may be a dielectric material mainly composed of barium titanate.
(703)堆疊,將陶瓷圍牆層3生胚堆疊覆蓋於至少一電極層2表面,且陶瓷圍牆層3生胚中央具有露出電極層2之鏤空槽30,位於介電陶瓷體1生胚及陶瓷圍牆層3生胚之間的電極層2外側壁呈外露狀。 (703) stacking, stacking the ceramic wall layer 3 on the surface of the at least one electrode layer 2, and the ceramic wall layer 3 has a hollow groove 30 exposing the electrode layer 2 in the center of the green embryo, and is located in the dielectric ceramic body 1 and the ceramic The outer side wall of the electrode layer 2 between the raw layers of the wall layer 3 is exposed.
(704)脫脂,升溫到高分子結合物揮發的溫度(250℃-600℃),且保持溫度一預定時間(約2-10小時)將介電陶 瓷體1生胚及陶瓷圍牆層3生胚中的高分子汽化揮發乾淨。 (704) Degreasing, heating to a temperature at which the polymer conjugate is volatilized (250 ° C - 600 ° C), and maintaining the temperature for a predetermined time (about 2-10 hours) will be dielectric ceramics The polymer in the raw body of the porcelain body 1 and the ceramic wall layer 3 vaporized and evaporated.
(705)燒結,升溫到達陶瓷相變化溫度點(1200℃-1400℃)將介電陶瓷體1生胚及陶瓷圍牆層3生胚燒成陶瓷體,且陶瓷圍牆層3的寬度W與介電陶瓷體1之厚度T的比值大於或等於1。 (705) Sintering, heating up to the ceramic phase change temperature point (1200 ° C - 1400 ° C), dielectric ceramic body 1 raw embryo and ceramic wall layer 3 green embryo firing ceramic body, and ceramic wall layer 3 width W and dielectric The ratio of the thickness T of the ceramic body 1 is greater than or equal to 1.
(706)二次金屬化,於陶瓷圍牆層3之鏤空槽30內露出的電極層2表面形成有耐焊接之導電層4。 (706) Secondary metallization, a solder resistive conductive layer 4 is formed on the surface of the electrode layer 2 exposed in the hollow trench 30 of the ceramic wall layer 3.
(707)夾腳,將二接腳5之一端焊接於鏤空槽30內露出之導電層4,且接腳5越過陶瓷圍牆層3使其一端對接部51位於外部。 (707) The leg is soldered to one end of the two pins 5 to the conductive layer 4 exposed in the hollow groove 30, and the pin 5 is passed over the ceramic wall layer 3 such that the one end abutting portion 51 is located outside.
(708)塗佈絕緣外層6,將樹脂塗佈於介電陶瓷體1、電極層2、陶瓷圍牆層3、鏤空槽30、導電層4及接腳5表面形成絕緣外層6,且二接腳5之對接部51露出於絕緣外層6外部。 (708) coating the insulating outer layer 6, coating the resin on the dielectric ceramic body 1, the electrode layer 2, the ceramic wall layer 3, the hollow groove 30, the conductive layer 4, and the surface of the pin 5 to form an insulating outer layer 6, and two pins The abutting portion 51 of the 5 is exposed to the outside of the insulating outer layer 6.
上述製造之流程步驟中,需利用介電係數(k)大於20且小於20000之第一介電陶瓷材料製成介電陶瓷體1生胚,完成之產品才能具有足夠的電容值,而電極層2為利用調配好匹配鈦酸鋇熱膨脹系數的導電材質所製成,當後續作業中經過燒結處理後,因為電極層2之熱膨脹系數匹配鈦酸鋇(介電陶瓷體1及陶瓷圍牆層3),才不會因為熱漲冷縮產生型變或損壞,以提高生產良率,該介電陶瓷體1生胚及陶瓷圍牆層3生胚,可為乾式製程製作或濕式淋膜方式製作,乾式製程製作為將陶瓷材料調成漿狀,使用塗佈設備將其平鋪於PET膜上製成帶狀,濕式淋膜方式製作為將陶瓷材料調成漿狀直接使用淋膜法製成產品。 In the above process steps, the dielectric ceramic body 1 is prepared by using the first dielectric ceramic material having a dielectric constant (k) of more than 20 and less than 20,000, and the finished product can have sufficient capacitance value and the electrode layer. 2 is made by using a conductive material that is matched with the thermal expansion coefficient of barium titanate. After the sintering process in the subsequent operation, the thermal expansion coefficient of the electrode layer 2 matches the barium titanate (dielectric ceramic body 1 and ceramic wall layer 3). In order to improve the production yield due to heat expansion and contraction, the dielectric ceramic body 1 raw embryo and ceramic wall layer 3 embryos can be produced by dry process or wet lamination. The dry process is made by slurrying the ceramic material into a slurry shape by using a coating device, and laying it on the PET film to form a strip shape, and the wet lamination method is used to prepare the ceramic material into a slurry form directly by using a lamination method. product.
上述之介電陶瓷體1生胚之第一介電陶瓷材料及陶瓷圍牆 層3生胚之第二介電陶瓷材料內,因為要進行塑形而需添加溶劑或黏結劑等高分子結合物,所以在堆疊後,需進行步驟(704)之脫脂作業,在大氣或氮氣的環境下,先升溫到250℃-600℃,並保持溫度約2-10小時,其溫度及保持溫度時間視介電陶瓷體1生胚厚度、陶瓷圍牆層3生胚厚度、第一介電陶瓷材料配方及第二介電陶瓷材料配方改變,讓介電陶瓷體1生胚及陶瓷圍牆層3生胚內之高分子結合物汽化並揮發乾淨;之後再進行步驟(705)之燒結作業,為升溫到1200℃-1400℃,讓介電陶瓷體1生胚及陶瓷圍牆層3生胚燒成陶瓷體以形成介電陶瓷體1及陶瓷圍牆層3。 The first dielectric ceramic material and ceramic wall of the above dielectric ceramic body 1 In the second dielectric ceramic material of the layer 3 raw embryo, since a polymer conjugate such as a solvent or a binder is required to be shaped, after the stacking, the degreasing operation in the step (704) is performed, in the atmosphere or nitrogen. In the environment, first heat up to 250 ° C -600 ° C, and maintain the temperature for about 2-10 hours, its temperature and temperature maintenance time depends on the dielectric ceramic body 1 raw embryo thickness, ceramic wall layer 3 raw embryo thickness, first dielectric The formulation of the ceramic material and the formulation of the second dielectric ceramic material are changed, so that the polymer conjugate of the dielectric ceramic body 1 and the ceramic wall layer 3 is vaporized and evaporated, and then the sintering operation of the step (705) is performed. In order to raise the temperature to 1200 ° C - 1400 ° C, the dielectric ceramic body 1 and the ceramic wall layer 3 are fired into a ceramic body to form a dielectric ceramic body 1 and a ceramic wall layer 3.
燒結後,則進行步驟(706)之二次金屬化作業,其於陶瓷圍牆層3之鏤空槽30內露出的電極層2表面形成有耐焊接之導電層4,導電層4的金屬化作業方法可為沉積或印刷覆蓋方式,沉積方式可為化學沉積法或物理沉積法,化學沉積法為無電解電鍍(例如化學鍍鎳、化學鍍錫或化學鍍銅)或電解電鍍(例如電解鍍鎳、電解鍍錫或電解鍍銅),物理沉積法為濺鍍或離子鍍(例如將Ni(鎳)、Ni-Cr(鎳鉻)、Ti(鈦)、Ti-W(鈦鎢)或Cu(銅)等耐焊金屬沉積於表面),而印刷覆蓋方式為將耐焊材料(例如Ag(銀)、Ag-Pd(銀鈀)、Ag-Pt(銀鉑)、Cu(銅)或Ni(鎳)等金屬或合金)調成膏狀直接二次印刷覆蓋於陶瓷圍牆層3之鏤空槽30內露出的電極層2表面。 After sintering, the secondary metallization operation of step (706) is performed, and a solder resistive conductive layer 4 is formed on the surface of the electrode layer 2 exposed in the hollow trench 30 of the ceramic wall layer 3, and the metallization operation method of the conductive layer 4 is performed. It can be deposited or printed, and the deposition method can be chemical deposition or physical deposition. Electroless deposition is electroless plating (such as electroless nickel plating, electroless tin plating or electroless copper plating) or electrolytic plating (such as electrolytic nickel plating, Electrolytic tin plating or electrolytic copper plating), physical deposition method is sputtering or ion plating (for example, Ni (nickel), Ni-Cr (nickel chromium), Ti (titanium), Ti-W (titanium tungsten) or Cu (copper) ) such as solder resist metal deposited on the surface, and the printing coverage is to apply solder resist material (such as Ag (silver), Ag-Pd (silver palladium), Ag-Pt (silver platinum), Cu (copper) or Ni (nickel) The metal or alloy is adjusted into a paste to directly cover the surface of the electrode layer 2 exposed in the hollow groove 30 of the ceramic wall layer 3.
之後再將二接腳5焊接於鏤空槽30內露出之導電層4,且將樹脂塗佈於介電陶瓷體1、電極層2、陶瓷圍牆層3、鏤空槽30、 導電層4及接腳5表面形成絕緣外層6,接腳5一端越過陶瓷圍牆層3位於外部之對接部51也沒有被絕緣外層6包覆,使用時便可利用二接腳5電性連接於預設電路板上。 Then, the second pin 5 is soldered to the conductive layer 4 exposed in the hollow groove 30, and the resin is applied to the dielectric ceramic body 1, the electrode layer 2, the ceramic wall layer 3, the hollow groove 30, The surface of the conductive layer 4 and the pin 5 is formed with an insulating outer layer 6. The butt portion 51 of the pin 5 that is located outside the ceramic wall layer 3 is not covered by the insulating outer layer 6 and can be electrically connected to the second pin 5 during use. Preset on the board.
請參閱第一、二、三、四、五、六、七、八、十、十一圖所示,上述之陶瓷電容製造之流程步驟,為製造單一陶瓷電容,但另一實施例為同時製造多個陶瓷電容,其製造之流程步驟為包括:(800)製作介電陶瓷體1生胚,利用介電係數(k)大於20且小於20000之第一介電陶瓷材料製成預定厚度之介電陶瓷體1生胚,第一介電陶瓷材料可為鈦酸鋇為主體的介電材料。 Referring to the first, second, third, fourth, fifth, sixth, seventh, eighth, tenth, and eleventh diagrams, the above-described ceramic capacitor manufacturing process steps are for manufacturing a single ceramic capacitor, but another embodiment is simultaneous fabrication. The plurality of ceramic capacitors are manufactured by the steps of: (800) fabricating a dielectric ceramic body 1 and forming a predetermined thickness using a first dielectric ceramic material having a dielectric constant (k) of greater than 20 and less than 20,000. The electric ceramic body 1 is a raw material, and the first dielectric ceramic material may be a dielectric material mainly composed of barium titanate.
(801)印刷電極層2,將匹配鈦酸鋇膨脹系數的導電材質之複數個電極層2陣列狀印刷於介電陶瓷體1生胚之上表面及下表面,電極層2與介電陶瓷體1生胚外側壁之間無間距。 (801) printing the electrode layer 2, printing a plurality of electrode layers 2 of a conductive material matching the expansion coefficient of barium titanate on the upper surface and the lower surface of the dielectric ceramic body 1, the electrode layer 2 and the dielectric ceramic body 1 There is no space between the outer sidewalls of the raw embryo.
(802)製作陶瓷圍牆層3生胚,利用第二介電陶瓷材料製成陶瓷圍牆層3生胚,第二介電陶瓷材料可為鈦酸鋇為主體的介電材料,且陶瓷圍牆層3生胚具有對應各電極層2呈陣列狀之複數鏤空槽30。 (802) fabricating a ceramic wall layer 3 raw embryo, using a second dielectric ceramic material to form a ceramic wall layer 3 raw embryo, the second dielectric ceramic material may be a barium titanate-based dielectric material, and the ceramic wall layer 3 The green embryo has a plurality of hollow grooves 30 corresponding to the electrode layers 2 in an array.
(803)堆疊,將陶瓷圍牆層3生胚堆疊覆蓋於至少一電極層2表面,且陶瓷圍牆層3之鏤空槽30內露出電極層2,位於介電陶瓷體1生胚及陶瓷圍牆層3生胚之間的電極層2外側壁呈外露狀。 (803) stacking, covering the surface of the at least one electrode layer 2 with the ceramic wall layer 3, and exposing the electrode layer 2 in the hollow space 30 of the ceramic wall layer 3, in the dielectric ceramic body 1 and the ceramic wall layer 3 The outer side wall of the electrode layer 2 between the raw embryos is exposed.
(804)切割,使用機械加工方式將介電陶瓷體1生胚及陶瓷圍牆層3生胚依照各電極層2切成陣列之複數個預定形狀,其預定形狀可為方型或是圓形等固定幾何形狀,即產生複數個半成品。 (804) cutting, using a mechanical processing method, the dielectric ceramic body 1 raw embryo and the ceramic wall layer 3 raw embryos are cut into a plurality of predetermined shapes according to the electrode layers 2, and the predetermined shape may be square or circular. Fixed geometry, that is, a plurality of semi-finished products are produced.
(805)脫脂,升溫到高分子結合物揮發的溫度(250℃-600℃),且保持溫度一預定時間(約2-10小時)將複數個半成品之介電陶瓷體1生胚及陶瓷圍牆層3生胚中的高分子汽化揮發乾淨。 (805) Degreasing, heating to the temperature at which the polymer conjugate is volatilized (250 ° C - 600 ° C), and maintaining the temperature for a predetermined time (about 2-10 hours) to form a plurality of semi-finished dielectric ceramic bodies 1 embryo and ceramic fence The polymer in the layer 3 embryo is vaporized and evaporated.
(806)燒結,升溫到達陶瓷相變化溫度點(1200℃-1400℃),以將複數個半成品之介電陶瓷體1生胚及陶瓷圍牆層3生胚燒成陶瓷體,且各半成品之陶瓷圍牆層3的寬度W與介電陶瓷體1的厚度T的比值大於或等於1。 (806) sintering, heating up to the ceramic phase change temperature point (1200 ° C - 1400 ° C), to a plurality of semi-finished dielectric ceramic body 1 raw embryo and ceramic wall layer 3 raw embryos fired into the ceramic body, and each semi-finished ceramic The ratio of the width W of the wall layer 3 to the thickness T of the dielectric ceramic body 1 is greater than or equal to one.
(807)二次金屬化,各半成品於陶瓷圍牆層3之鏤空槽30內露出的電極層2表面形成有耐焊接之導電層4。 (807) Secondary metallization, each semi-finished product is formed with a solder-resistant conductive layer 4 on the surface of the electrode layer 2 exposed in the hollow groove 30 of the ceramic wall layer 3.
(808)夾腳,將二接腳5之一端焊接於各半成品鏤空槽30內露出之導電層4,且接腳5越過陶瓷圍牆層3使其一端對接部51位於外部。 (808) The pin is formed by soldering one end of the two pins 5 to the conductive layer 4 exposed in each of the semi-finished hollow slots 30, and the pins 5 are passed over the ceramic wall layer 3 such that the one end abutting portion 51 is located outside.
(809)塗佈絕緣外層6,將樹脂塗佈於各半成品的介電陶瓷體1、電極層2、陶瓷圍牆層3、鏤空槽30、導電層4及接腳5表面形成絕緣外層6,且二接腳5之對接部51露出於絕緣外層6外部。 (809) coating the insulating outer layer 6, and coating the resin on the surface of the dielectric ceramic body 1, the electrode layer 2, the ceramic wall layer 3, the hollow groove 30, the conductive layer 4, and the pin 5 of each semi-finished product to form an insulating outer layer 6, and The abutting portion 51 of the two pins 5 is exposed outside the insulating outer layer 6.
上述另一實施例製造之流程步驟中,為於介電陶瓷體1生胚之上表面及下表面同時印刷複數個電極層2呈陣列狀,再於陶瓷圍牆層3生胚上形成有對應各電極層2呈陣列狀之複數鏤空槽30,便可單次作業將單一陶瓷圍牆層3生胚堆疊覆蓋於電極層2與介電陶瓷體1生胚上方,之後便可進行切割作業來產生複數個半成品,其切割作業可利用刀具將介電陶瓷體1、複數個電極層2及陶瓷圍牆層3切割成為方型,亦可使用 模具沖壓成為圓型或其他固定的幾何形狀(如三角形或菱形等),由於單一次的作業便可生產複數個陶瓷電容半成品,所以便可節省作業程序且減少作業時間,進而達到大量生產及降低成本之目的。 In the process step of manufacturing the other embodiment, a plurality of electrode layers 2 are simultaneously printed on the upper surface and the lower surface of the green ceramic body 1 in an array, and then formed on the green ceramic layer 3 The electrode layer 2 is in the form of an array of a plurality of hollow slots 30, so that a single ceramic wall layer 3 raw embryo stack can be overlaid on the electrode layer 2 and the dielectric ceramic body 1 in a single operation, and then the cutting operation can be performed to generate a plurality of The semi-finished product can be cut into a square shape by using a cutter to cut the dielectric ceramic body 1, the plurality of electrode layers 2 and the ceramic wall layer 3, and can also be used. The die is stamped into a round shape or other fixed geometry (such as triangle or diamond). Since a single ceramic capacitor semi-finished product can be produced in a single operation, the operation procedure can be saved and the operation time can be reduced, thereby achieving mass production and reduction. The purpose of cost.
由於電容計算公式為C=ε*A/d,C為電容量,單位為法拉(F),ε為介電係數,A為面積,單位為平方公尺(m2),d為距離,單位為公尺(m),距離d即為二電極層2及二導電層4之間的介電陶瓷體1厚度,所以介電陶瓷體1薄化後便可讓產品的電容值增高,而在介電陶瓷體1厚度變小之後,二導電層4之間的距離變短而容易在高壓狀況下由外部空氣中產生電氣跳弧(Arcing)的問題,又因為利用了陶瓷圍牆層3罩覆了電極層2,而僅由陶瓷圍牆層3中央之鏤空槽30內露出導電層4,便可利用介電陶瓷體1、電極層2及陶瓷圍牆層3一起在高溫下共燒,藉由陶瓷特性讓陶瓷圍牆層3緊密結合於電極層2表面,絕緣外層6則是披覆在陶瓷圍牆層3表面,即可避免因電極層2表面產生的缺陷(如高低不平或凹陷)讓絕緣外層6塗佈時產生披覆不完全,而產生氣泡與微小孔洞等問題,便會避免產生電氣跳弧之情況,所以產品就不容易損壞。 Since the capacitance calculation formula is C=ε*A/d, C is the capacitance, the unit is Farah (F), ε is the dielectric coefficient, A is the area, the unit is square meters (m 2 ), and d is the distance, the unit In the meter (m), the distance d is the thickness of the dielectric ceramic body 1 between the two electrode layers 2 and the two conductive layers 4, so that the dielectric ceramic body 1 is thinned to increase the capacitance of the product. After the thickness of the dielectric ceramic body 1 becomes smaller, the distance between the two conductive layers 4 becomes shorter, which is liable to cause electrical arcing in the outside air under high pressure conditions, and is covered by the ceramic wall layer 3 The electrode layer 2 is exposed, and only the conductive layer 4 is exposed in the hollow groove 30 in the center of the ceramic wall layer 3, and the dielectric ceramic body 1, the electrode layer 2 and the ceramic wall layer 3 can be co-fired at a high temperature by ceramics. The characteristic is that the ceramic wall layer 3 is tightly bonded to the surface of the electrode layer 2, and the insulating outer layer 6 is coated on the surface of the ceramic wall layer 3, so as to avoid defects (such as unevenness or depression) caused by the surface of the electrode layer 2, so that the insulating outer layer 6 Avoiding electrical generation when coating is incomplete, and bubbles and tiny holes are generated. Arc of the situation, so the product is not easily damaged.
再者,當電極層2表面因燒結凸起或不平時,容易產生較強的電場,而使得表面電場不均,但電極層2燒結後,又於陶瓷圍牆層3之鏤空槽30內露出的電極層2表面形成有耐焊接之導電層4,所以表面就不會因燒結產生凸起或不平,即可讓電場均勻,以降低於外部空氣中產生電氣跳弧之情形,進而達到提升產品壽命及使用安全之目的。 Furthermore, when the surface of the electrode layer 2 is sintered or uneven, a strong electric field is easily generated, and the surface electric field is uneven, but after the electrode layer 2 is sintered, it is exposed in the hollow groove 30 of the ceramic wall layer 3. The surface of the electrode layer 2 is formed with a solder-resistant conductive layer 4, so that the surface does not cause bumps or unevenness due to sintering, so that the electric field can be made uniform to reduce the occurrence of electrical arcing in the outside air, thereby improving product life. And the purpose of using security.
此外,因為介電係數(k)大於20且小於20000之 第一介電陶瓷材料製成預定厚度之介電陶瓷體1生胚,所以產品的介電陶瓷體1便可具有較高的電容值,再者,又利用第二介電陶瓷材料製作陶瓷圍牆層3生胚,位於外層之陶瓷圍牆層3具有較大強度也會讓產品不易碰撞毀損。 In addition, since the dielectric constant (k) is greater than 20 and less than 20,000 The first dielectric ceramic material is made into a dielectric ceramic body 1 with a predetermined thickness, so that the dielectric ceramic body 1 of the product can have a higher capacitance value, and further, the second dielectric ceramic material is used to make the ceramic wall. Layer 3 raw embryos, the ceramic wall layer 3 located on the outer layer has greater strength and will also make the product less likely to collide and damage.
故,本發明為主要針對陶瓷電容結構,而可於第一介電陶瓷材料製作之介電陶瓷體生胚上、下表面印刷電極層,再利用第二介電陶瓷材料製成陶瓷圍牆層生胚堆疊覆蓋於至少一電極層表面,之後依序進行脫脂及燒結,以降低介電陶瓷體厚度及利用陶瓷圍牆層緊密結合於電極層表面以避免產生缺陷為主要保護重點,並具有減小產品厚度、提高電容值及避免電氣跳弧之優勢,惟,以上所述僅為本發明之較佳實施例而已,非因此即侷限本發明之專利範圍,故舉凡運用本發明說明書及圖式內容所為之簡易修飾及等效結構變化,均應同理包含於本發明之專利範圍內,合予陳明。 Therefore, the present invention is mainly directed to a ceramic capacitor structure, and the electrode layer can be printed on the upper and lower surfaces of the dielectric ceramic body preform made of the first dielectric ceramic material, and the second dielectric ceramic material is used to form the ceramic wall layer. The embryo stack covers the surface of at least one electrode layer, and then degreased and sintered sequentially to reduce the thickness of the dielectric ceramic body and to closely bond the surface of the electrode layer to the surface of the electrode layer to avoid defects, and has a reduced product. The advantages of the present invention and the contents of the drawings are as follows. The simple modification and the equivalent structural change are all included in the scope of the patent of the present invention and are combined with Chen Ming.
綜上所述,本發明上述之陶瓷電容結構於實施、操作時,為確實能達到其功效及目的,故本發明誠為一實用性優異之發明,為符合發明專利之申請要件,爰依法提出申請,盼 審委早日賜准本案,以保障發明人之辛苦研發,倘若 鈞局貴審委有任何稽疑,請不吝來函指示,發明人定當竭力配合,至感德便。 In summary, the above-mentioned ceramic capacitor structure of the present invention can achieve its efficacy and purpose during implementation and operation. Therefore, the present invention is an invention with excellent practicability, and is an application for conforming to the invention patent, and is proposed according to law. To apply, I hope that the trial committee will grant this case as soon as possible to protect the intensive research and development of the inventor. If there is any doubt in the bureau, please do not hesitate to give instructions to the inventor, and the inventor will try his best to cooperate with him.
1‧‧‧介電陶瓷體 1‧‧‧dielectric ceramic body
2‧‧‧電極層 2‧‧‧electrode layer
3‧‧‧陶瓷圍牆層 3‧‧‧Ceramic wall layer
30‧‧‧鏤空槽 30‧‧‧ empty slots
4‧‧‧導電層 4‧‧‧ Conductive layer
Claims (9)
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TW104121372A TWI587333B (en) | 2015-07-01 | 2015-07-01 | Ceramic capacitor structure |
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TW104121372A TWI587333B (en) | 2015-07-01 | 2015-07-01 | Ceramic capacitor structure |
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TWI711058B (en) * | 2017-08-09 | 2020-11-21 | 日商新烯控股有限公司 | Manufacturing method and device of electronic component and electronic component |
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TW201510010A (en) * | 2013-06-18 | 2015-03-16 | Toray Industries | Biaxially-oriented laminated polyester film for mold release applications |
TWI490899B (en) * | 2012-12-03 | 2015-07-01 | Samsung Electro Mech | Multilayered ceramic capacitor and board for mounting the same |
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TWI490899B (en) * | 2012-12-03 | 2015-07-01 | Samsung Electro Mech | Multilayered ceramic capacitor and board for mounting the same |
TW201510010A (en) * | 2013-06-18 | 2015-03-16 | Toray Industries | Biaxially-oriented laminated polyester film for mold release applications |
Cited By (1)
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TWI711058B (en) * | 2017-08-09 | 2020-11-21 | 日商新烯控股有限公司 | Manufacturing method and device of electronic component and electronic component |
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