TWI585976B - 閘極空乏型汲極延伸式ｍｏｓ電晶體 - Google Patents

閘極空乏型汲極延伸式ｍｏｓ電晶體 Download PDF

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TWI585976B
TWI585976B TW100113528A TW100113528A TWI585976B TW I585976 B TWI585976 B TW I585976B TW 100113528 A TW100113528 A TW 100113528A TW 100113528 A TW100113528 A TW 100113528A TW I585976 B TWI585976 B TW I585976B
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gate
mos transistor
implant
doping
extension
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TW100113528A
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TW201218381A (en
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雷那爾 赫本霍茲
路朵維克 歐朵亞特
大衛 維吉爾
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高通技術國際有限公司
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    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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Description

閘極空乏型汲極延伸式MOS電晶體
此發明有關於汲極延伸式MOS電晶體。
發明背景
CMOS技術之定標不僅使裝置密度增大而且使閘極氧化物厚度減小，因此電晶體電源電壓減小。然而，晶片電源電壓並未與電晶體電源電壓一致地減小。
汲極延伸式MOS(DE-MOS)電晶體已被設計成允許汲極電壓增大，但是裝置之閘極的電壓不容許變化。限制閘極電壓典型地導致使用閘極驅動電路，但是因為閘極驅動電路可能與DE-MOS電晶體同樣大，此類電路大幅增加電路面積。
另一方法為利用專用的高電壓電晶體，例如，在一習知的雙閘極氧化物製程中添加另一閘極氧化物。然而，此類系統增加製造成本及週期時間且因此是不理想的。
因此，需要一CMOS技術來使電晶體閘極供應電壓增大。下文所述實施例並不限於解決上述任一或全部缺點的實施。
發明概要
提供此概要是為了以簡化形式引入一些概念，這些概念在下文之詳細說明中進一步描述。此概要不欲識別所申請專利之標的之關鍵特徵或實質特徵，也不欲用作決定所 申請專利之標的範圍的一輔助。
本發明提供包含至少一閘極空乏型汲極延伸式MOS電晶體及極性相同的至少另一MOS電晶體的一半導體裝置，其中該至少一閘極空乏型汲極延伸式MOS電晶體及該至少另一MOS電晶體各包含具有一相同厚度的一閘極氧化物及一多晶矽閘極，且該至少一閘極空乏型汲極延伸式MOS電晶體之該多晶矽閘極有明顯低於該至少另一MOS電晶體之多晶矽閘極的摻雜程度。
該至少一閘極空乏型汲極延伸式MOS電晶體之該多晶矽閘極之摻雜程度可能為該至少另一MOS電晶體之摻雜程度的大約1/5至1/50。
本發明還提供包含至少一閘極空乏型汲極延伸式MOS電晶體及極性相同的至少另一MOS電晶體的一半導體裝置，其中該至少一閘極空乏型汲極延伸式MOS電晶體及該至少另一MOS電晶體各包含具有一相同厚度的一閘極氧化物及一多晶矽閘極，且該至少另一MOS電晶體之多晶矽閘極有一與該電晶體之源極區及汲極區類似的摻雜程度，且該至少一閘極空乏型汲極延伸式MOS電晶體之多晶矽閘極有一明顯低於該電晶體之源極區及汲極區的摻雜程度。
該至少一閘極空乏型汲極延伸式MOS電晶體之多晶矽閘極之摻雜程度可能為該電晶體之源極區及汲極區之摻雜程度的大約1/5至1/50。
本發明還提供關於上述半導體裝置的一設計。
本發明還提供用以製造上述半導體裝置的一遮罩組。
本發明還提供一種製造包含至少一閘極空乏型汲極延伸式MOS電晶體及極性相同的至少另一MOS電晶體的一半導體裝置的方法，其包含以下步驟：在相同的製程步驟中針對此二電晶體形成一閘極氧化物層，在相同的製程步驟中針對此二電晶體界定一多晶矽閘極，沈積及圖案化一光阻層，使得該至少另一MOS電晶體之多晶矽閘極被暴露且該至少一閘極空乏型汲極延伸式MOS電晶體之多晶矽閘極不被暴露，及對晶圓應用一佈植步驟使得受暴露之閘極被摻雜且被遮蔽閘極不被摻雜。
該至少另一MOS電晶體之多晶矽閘極及源極區及汲極區，及該至少一閘極空乏型汲極延伸式MOS電晶體之源極區及汲極區可以被暴露，該至少一閘極空乏型汲極延伸式MOS電晶體之多晶矽閘極可以被遮蔽，且該佈植步驟也可在該等電晶體中形成源極區及汲極區。
本發明還提供一種製造包含各具有一相同閘極氧化物厚度的至少一閘極空乏型汲極延伸式MOS電晶體及極性相同的至少另一MOS電晶體的一半導體裝置的方法，其包含以下步驟：對該至少另一電晶體應用第一或第二源極延伸佈植類型，及對該閘極空乏型汲極延伸式MOS電晶體應用第一及第二源極延伸佈植類型。
對熟於此技者顯而易見的是，較佳特徵可被適當組合，且可與本發明任一層面組合。
圖式簡單說明
本發明之實施例將參照以下圖式藉由舉例方式被描 述，其中：第1圖繪示一汲極延伸式NMOS電晶體；第2圖繪示在Vsb=0情況下，電容對閘極電壓之一圖式；第3圖繪示一閘極空乏型汲極延伸式NMOS電晶體；第4圖繪示用以製造一閘極空乏型汲極延伸式NMOS電晶體之被選製程步驟；第5圖繪示在矽化物形成前的一閘極空乏型汲極延伸式NMOS電晶體之源極區；第6圖繪示在矽化物形成後的一閘極空乏型汲極延伸式NMOS電晶體之源極區；第7圖繪示習知的汲極延伸式NMOS電晶體及閘極空乏型汲極延伸式NMOS電晶體的臨界電壓對通道長度圖；第8圖繪示習知的汲極延伸式PMOS電晶體及閘極空乏型汲極延伸式PMOS電晶體的臨界電壓對通道長度圖；第9圖繪示一NMOS閘極空乏型汲極延伸式電晶體的一輸出特性圖；以及第10圖繪示閘極氧化物厚度為52A的一PMOS閘極空乏型汲極延伸式電晶體的一輸出特性圖。
詳細說明
本發明之實施例僅藉由舉例方式在下文中描述。這些範例代表本案申請人當前已知的將本發明付諸實施的最佳方式，雖然它們不是可實現本發明的唯一方式。
本說明闡述範例的功能及用以構建及運作該範例的步 驟之順序。然而，相同或等效的功能及順序也可藉由不同的範例來達成。
第1圖繪示一習知的DE-NMOS裝置。高摻雜的N++源極10、閘極11及汲極12區域與由特定製程提供之一標準厚度的氧化物層13一起被利用。一漂移區14被提供以使該電晶體能夠耐受比標準的NMOS裝置更高的汲極電壓。
由於閘極氧化物在高電場強度下發生故障，故容許閘極電壓依該閘極氧化物上的電場強度而定。電場強度與閘極電容成比例，後者復與閘極氧化物厚度成反比。因此，增加閘極氧化物厚度，閘極電容減小且容許閘極電壓增大。然而，如上所述者，在製程中加入一較厚的氧化物層是不理想的。
第2圖繪示在閘極摻雜(NP)改變情況下，CGB對VGB之一圖。處於導通狀態時，在高摻雜程度下，CGB隨著VGB的增大而維持相對恆定，但是在較低的摻雜程度下，CGB隨著VGB的增大而明顯減小。閘極電容的減小是由於閘極氧化物介面附近的閘極之空乏，增加閘極氧化物之有效厚度。此效應一般而言是不理想的，因為相較於對其所設計的特性，這降低了跨導。
然而，在下文所述實施例中，利用閘極空乏來增加容許閘極電壓的DE-MOS裝置連同用於利用習知的雙氧化物製程的此類裝置的製造技術一起描述。
第3圖繪示一閘極空乏型DE-NMOS電晶體。相較於第1圖之DE-NMOS裝置，閘極30僅為輕摻雜的，然而閘極氧化 物13及源極佈植及汲極佈植10、12則是如同第1圖之裝置中所使用者。源極延伸佈植包含一核心電晶體LDD佈植31，包括環形佈植32，及一I/O電晶體LDD佈植33。所有佈植及沈積類型均利用被選擇製程中的習知步驟。
在使用一標準的雙氧化物製程所形成的一習知裝置中，多晶矽閘極與源極區及汲極區有一類似的摻雜程度，而在第3圖之裝置中，多晶矽閘極之摻雜程度大幅低於源極區及汲極區之摻雜程度。一示範性裝置之多晶矽閘極摻雜程度為習知裝置的1/5至1/50，為該裝置之源極區及汲極區之摻雜的大約1/5至1/50。在一特定範例中，多晶矽閘極摻雜程度可以為習知裝置的1/5，為該裝置之源極區及汲極區之摻雜的大約1/5。
由於輕摻雜閘極及一空乏層在較高的閘極電壓下形成，故所產生的裝置容許更高的閘極電壓。核心及I/O源極延伸佈植的使用將在下文中討論。
第4圖繪示用於第3圖之閘極空乏型DE-NMOS電晶體的一製程連同用於一習知的I/O DE-NMOS電晶體之一製程。第4圖僅描繪製程中的示範性步驟且不欲反映製造所需的每一製程步驟。同樣地，該等步驟之排序僅為舉例且可依據所利用的特定製程而更改。所有製程步驟均是習知的，唯一的修改是在於用來圖案化各種不同光阻層的遮罩圖案。因此，習知的製程可用於新的裝置類型，只有對遮罩的適當修改是必要的。
在習知的製程中，在沈積多晶矽層之後，N+多晶矽佈 植被利用來摻雜該多晶矽閘極。在閘極空乏型裝置製程中，裝置在此步驟期間被光阻遮蔽，使得將成為閘極空乏型裝置之閘極的多晶矽中無佈植。
對一習知的I/O電晶體而言，整個區域針對核心NLDD佈植步驟被遮蔽，但是在閘極空乏型裝置中，此佈植覆蓋整個區域，包括多晶矽閘極。此步驟還形成環形佈植。除此之外，I/O NLDD佈植也覆蓋整個區域，如同習知的製程中一樣。此佈植組合導致I/O及核心電晶體源極與汲極延伸區存在，原因在下文中說明。
在習知的製程中，另一N+摻雜步驟在整個區域上執行，以形成源極區及汲極區，且進一步摻雜閘極。在閘極空乏製程中，閘極區域被光阻遮蔽以限制N+摻雜到達源極區/汲極區，使得未進一步摻雜閘極。
所產生的裝置為第3圖中所示者，其具有核心及I/O LDD源極/汲極延伸區二者連同一輕摻雜閘極。
第5圖繪示第4圖中所示之方法之最終N+佈植步驟的圖案化光阻層50之後，閘極之源極端之一放大圖。光阻被圖案化以延伸超過閘極52之邊緣一距離51以允許遮罩及層對層對準製程中的容差。對在範圍32-65nm內的製程節點而言，距離51可能在範圍60-140nm內。這導致源極佈植與閘極之間以該距離相間隔。
第6圖繪示在矽化物層60形成之後，閘極之源極端之一放大圖。由於矽化物層60形成於裝置整個區域上，故其朝向閘極52延伸到源極佈植61之邊緣外。若僅淺核心LDD佈 植62被利用，則由於核心LDD區域62與P井63之間的pn接面相較於矽化物層60之底部深度不足，漏流可能出現在裝置之矽化物層60與塊狀矽63之間。因此，較深的I/O NLDD佈植64被利用以在矽化物層60下提供充足的深度來防止漏流。
在以上實施例中，一I/O NLDD佈植與一核心LDD佈植組合以設定所需的多晶矽摻雜，但是若摻雜程度對多晶矽而言是適當的，則I/O NLDD佈植可被單獨使用。
若I/O LDD佈植不能反摻雜口袋(pocket)，則大量漏流也可能出現。由於LDD佈植不夠深或摻雜不足以克服環形佈植而遭受大量漏流的裝置可以一具有零反向偏壓的配置被利用。
在可供選擇的製程中，一遮罩製程可被利用來防止矽化物形成超過源極佈植之邊緣，從而避免上述漏流問題。然而，此類製程需要一增大的佈局區域來容納矽化物阻隔且增大源極的串聯電阻，這二者都是不理想的。
以下表格1繪示製造一習知的DE-MOS裝置與製造一閘極空乏型DE-MOS裝置時的示範性製程步驟之比較。如上所述，該等步驟對於一雙氧化物CMOS製程的是習知的，只是新裝置藉由改變遮罩佈局而形成。將理解的是，一旦上述NMOS裝置及製程被理解，以上與NMOS裝置相關的揭露即可依據已知原理被擴展到以下表格中的PMOS裝置。在表格1中，「是」指示電晶體之整個區域在佈植步驟中被暴露，「否」指示電晶體完全未在佈植步驟中被暴露(例如，其被 一光阻層遮蔽)，「相同的」指示相同的遮罩圖案及製程步驟被利用，且「局部的」指示電晶體的一部分在佈植步驟中被暴露(例如，其被一圖案化光阻層局部遮蔽)。
因此，本文所述之方法提供使用習知製程但無需先前技術所需之額外處理而形成增大容許閘極電壓的閘極空乏 型DE-MOS裝置的製程。閘極空乏型裝置相較於使用特定的CMOS製程所形成的其他裝置有一減小的閘極摻雜，導致閘極空乏及因此而產生的較高閘極電壓下容差。
如上文所指出者，新裝置需要修正過的遮罩佈局，這可能需要修改一製程之設計規則以允許設計及使用新佈局。
將瞭解到的是，若佈植步驟不能使用現有步驟的組合而被實現，則它們可被加入到習知的製程流中以實現所欲程度的多晶矽空乏，同時仍避免添加一實際上較厚的閘極氧化物的製程複雜性。
第7圖繪示關於使用上述方法而構成的(a)一習知的DE-NMOS裝置及(b)一使用上文中所描述方法建構之閘極空乏型DE-NMOS裝置的臨界電壓對通道長度圖。可以看出，臨界電壓已增大至1.4V，1.4V，其為此一電晶體將被利用的一可工作值且有助於在較高的閘極電壓下維持足夠的熱載子性能。
第8圖繪示與第7圖同等但關於PMOS裝置之圖，其同樣證明臨界電壓之幅值增大。
第9及10圖繪示分別依據以上揭露製成的ID對VDS資料NMOS裝置及PMOS裝置。
將瞭解到的是，以上揭露與裝置之源極區及閘極區有關且與電晶體之特定的漂移區設計無關，因而可被應用於任一種適合的汲極延伸式MOS電晶體設計。當不存在漂移區的情況下，該等技術也可應用於習知的MOS電晶體設 計，但因容許汲極電壓可能被限制成小於容許閘極電壓，故此類電晶體的應用有限。
將顯而易見的是，比較用語諸如「較大的」及「較少的」被使用時，依每一字的恰當使用它們是用來指值的大小而非絕對值。
在已將習知裝置與閘極空乏型裝置作成比較之處，將理解的是，那些比較是在相同極性的裝置之間-亦即，NMOS與NMOS相比較且PMOS與PMOS相比較。
本文所用之「半導體裝置」一詞指包含至少一半導體組件的半導體材料之任一部分，且不欲被限制成一完整的封裝式裝置。例如，該用語可適用於一晶圓之一區域、切割自一晶圓之晶粒、或一封裝式晶粒。
對熟於此技者顯而易見的是，本文所提出的任一範圍或裝置值可在不喪失追求效果的情況下被擴大或修改。
將理解的是，上述益處及優勢可能有關於一實施例或可能有關於若干個實施例。該等實施例並不限於解決任一或所有陳述問題的那些實施例、或具有任一或所有陳述益處及優勢的那些實施例。
提及「一」項目指一或一以上之該項目。「包含」一詞在本文中使用意指包括所指認的方法區塊或元件，但是此類區塊或元件不包含一排他列表且一方法或設備可包含額外區塊或元件。
本文所述方法之步驟可以任一種適合的順序來實施，或在適當的情況下同時實施。此外，個別區塊可在不背離 本文所述標的之精神及範圍的情況下從任一種方法中刪除。在不喪失追求效果的情況下，上述任一範例之層面可與任一其他所述範例之層面組合以形成其他範例。
10‧‧‧源極/源極佈植
11‧‧‧閘極
12‧‧‧汲極/汲極佈植
13‧‧‧標準厚度的氧化物層/閘極氧化物
14‧‧‧漂移區
30‧‧‧閘極
31‧‧‧核心電晶體LDD佈植
32‧‧‧環形佈植
33‧‧‧I/O電晶體LDD佈植
50‧‧‧光阻層
51‧‧‧距離
52‧‧‧閘極
60‧‧‧矽化物層
61‧‧‧源極佈植
62‧‧‧核心LDD區域
63‧‧‧塊狀矽/P井
64‧‧‧較深的I/O NLDD佈植
第1圖繪示一汲極延伸式NMOS電晶體；第2圖繪示在Vsb=0情況下，電容對閘極電壓之一圖式；第3圖繪示一閘極空乏型汲極延伸式NMOS電晶體；第4圖繪示用以製造一閘極空乏型汲極延伸式NMOS電晶體之被選製程步驟；第5圖繪示在矽化物形成前的一閘極空乏型汲極延伸式NMOS電晶體之源極區；第6圖繪示在矽化物形成後的一閘極空乏型汲極延伸式NMOS電晶體之源極區；第7圖繪示習知的汲極延伸式NMOS電晶體及閘極空乏型汲極延伸式NMOS電晶體的臨界電壓對通道長度圖；第8圖繪示習知的汲極延伸式PMOS電晶體及閘極空乏型汲極延伸式PMOS電晶體的臨界電壓對通道長度圖；第9圖繪示一NMOS閘極空乏型汲極延伸式電晶體的一輸出特性圖；以及第10圖繪示閘極氧化物厚度為52A的一PMOS閘極空乏型汲極延伸式電晶體的一輸出特性圖。
10‧‧‧源極/源極佈植
12‧‧‧汲極/汲極佈植
13‧‧‧標準厚度的氧化物層/閘極氧化物
14‧‧‧漂移區
30‧‧‧閘極
31‧‧‧核心電晶體LDD佈植
32‧‧‧環形佈植
33‧‧‧I/O電晶體LDD佈植

Claims (7)

  1. 一種半導體裝置，其包含至少一閘極空乏型汲極延伸式MOS電晶體及具有相同極性的至少另一MOS電晶體，其中：該至少一閘極空乏型汲極延伸式MOS電晶體及該至少另一MOS電晶體各包含具有一相同厚度的一閘極氧化物及一多晶矽閘極，及該至少一閘極空乏型汲極延伸式MOS電晶體之該多晶矽閘極具有明顯低於該至少另一MOS電晶體之該多晶矽閘極的一摻雜程度，及該至少一閘極空乏型汲極延伸式MOS電晶體包含一源極側核心延伸佈植、一源極側輸入/輸出(I/O)延伸佈植、及一環形佈植，其中該I/O延伸佈植具有一充足的深度及一足夠的摻雜來克服該環形佈植，以便防止大量漏流，且其中該I/O延伸佈植之一摻雜程度係與該核心延伸佈植之另一摻雜程度組合，以設定明顯較低的該至少一閘極空乏型汲極延伸式MOS電晶體之該多晶矽閘極的該摻雜程度。
  2. 如請求項1所述之半導體裝置，其中該至少一閘極空乏型汲極延伸式MOS電晶體之該多晶矽閘極之該摻雜程度為該至少另一MOS電晶體之該摻雜程度的大約1/5至1/50。
  3. 一種儲存媒體，其儲存用於如請求項1所述之半導體裝置的設計。
  4. 一種用以製造如請求項1所述之半導體裝置的遮罩組。
  5. 一種用以製造半導體裝置的方法，該半導體裝置包含至少一閘極空乏型汲極延伸式MOS電晶體及具有相同極性的至少另一MOS電晶體，該方法包含以下步驟：在相同的製程步驟中針對該等二電晶體形成一閘極氧化物層，在相同的製程步驟中針對該等二電晶體界定一多晶矽閘極，沈積及圖案化一光阻層，使得該至少另一MOS電晶體之該多晶矽閘極被暴露且該至少一閘極空乏型汲極延伸式MOS電晶體之該多晶矽閘極未被暴露，及對晶圓施用一佈植步驟，使得受暴露的該閘極被摻雜且被遮蔽的閘極未被摻雜，該佈植步驟造成核心、輸入/輸出(I/O)及環形源極延伸佈植的存在，該I/O源極延伸佈植具有充足的深度及一足夠的摻雜來克服該環形佈植，以便防止大量漏流，且其中該I/O延伸佈植之一摻雜程度係與該核心延伸佈植之另一摻雜程度組合，以設定明顯較低的該至少一閘極空乏型汲極延伸式MOS電晶體之該多晶矽閘極的該摻雜程度。
  6. 如請求項5所述之方法，其中：該至少另一MOS電晶體之該多晶矽閘極及該等源極區與汲極區，及該至少一閘極空乏型汲極延伸式MOS電晶體之該等源極區及汲極區被暴露，該至少一閘極空乏型汲極延伸式MOS電晶體之該 多晶矽閘極被遮蔽，且該佈植步驟也形成該等電晶體中之源極區及汲極區。
  7. 一種用以製造半導體裝置的方法，該半導體裝置包含各具有一相同閘極氧化物厚度的至少一閘極空乏型汲極延伸式MOS電晶體及具有相同極性的至少另一MOS電晶體，該方法包含以下步驟：對該至少另一電晶體施用第一、第二及第三源極延伸佈植類型，及對該閘極空乏型汲極延伸式MOS電晶體施用該第一、第二及第三源極延伸佈植類型，其中該第三源極延伸佈植具有足以藉該第一及該第二佈植來克服的一摻雜，以便防止大量漏流。
TW100113528A 2010-04-30 2011-04-19 閘極空乏型汲極延伸式ｍｏｓ電晶體 TWI585976B (zh)

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