TWI567710B - Display device and gate driver on array - Google Patents

Description

Display device and gate drive circuit on array

The present invention relates to a device and a driving circuit, and more particularly to a display device and an array of gate driving circuits.

In order to respond to consumers' demand for electronic products, thinning has become the trend of current electronic products. The display panel industry has followed the current trend and developed gate driver on Array (GOA) to make the panel thinner. . The so-called GOA is to arrange the gate driving circuit on the array substrate to replace the driving wafer fabricated by the external germanium wafer. Since the GOA technology can be directly disposed around the panel, the production process is simplified, the integration of the display panel is improved, and the panel is made thinner.

With the advancement of technology, the display panel industry has developed a dual-drive GOA circuit, which is to arrange two sets of GOA circuits on both sides of the panel. If a short circuit occurs between the driving signal line and the output node of the GOA circuit on either side of the display panel, and the operation is abnormal, the signal line of the short-circuited GOA circuit can be cut off to repair the display panel. However, due to the floating node of the GOA circuit on the repair side, the voltage stabilizing circuit abnormally forms a leakage path, and the voltage level of the gate line is lowered. Therefore, the repaired display panel still has no brightness. Both, even the GOA circuit is operating abnormally.

It can be seen that the above existing methods obviously have inconveniences and defects, and need to be improved. In order to solve the above problems, the relevant fields have not tried their best to find a solution, but for a long time, no suitable solution has been developed.

SUMMARY OF THE INVENTION The Summary of the Disclosure is intended to provide a basic understanding of the present disclosure. This Summary is not an extensive overview of the disclosure, and is not intended to be an

It is an object of the present invention to provide an on-grid gate drive circuit for improving the problems of the prior art.

In order to achieve the above object, a first aspect of the present invention relates to an array upper gate driving circuit including a driving circuit, a control circuit, and a voltage stabilizing circuit. The driving circuit is used to generate the scanning signal of the current level. The control circuit includes an output, a pull up unit, and a pull down unit. The pull-up unit is configured to provide a pull-up control signal to the output end according to the pre-X-level scan signal, and the pull-down unit is configured to provide a pull-down control signal to the output end according to the post-stage scan signal, and the output end is configured to be controlled according to the pull-up control signal or the pull-down control The signal is output and the control signal is output, where X, Y are positive integers. The voltage stabilizing circuit is coupled between the driving circuit and the output end for regulating the scan signal according to the control signal.

In still another embodiment, the pull-up unit includes a first end, a control end, and a second end. The first end is for receiving the first X-level scan signal. The control end is coupled to the first end. The second end is coupled to the output end.

In an embodiment, the pull down unit includes a first end, a control end, and a second end. The first end is coupled to the output end. The control terminal is configured to receive the post Y-level scan signal. The second end is coupled to the ground end.

In another embodiment, the gate drive circuit on the array further includes a capacitor. The capacitor is coupled to the output terminal and configured to pull up the voltage level of the output terminal according to the first scan signal, so that the output terminal outputs the second high level control signal.

In still another embodiment, the pull-up control signal is a first high level control signal, and the voltage level of the second high level control signal is higher than a voltage level of the first high level control signal.

In still another embodiment, the first scan signal is generated after the pre-X scan signal.

In an embodiment, the post Y-level scan signal is generated after the first scan signal.

In another embodiment, the control circuit further includes a voltage stabilizing unit coupled to the output end and configured to output a low level control signal to the output terminal according to the driving signal provided by the voltage stabilizing circuit.

In yet another embodiment, the drive signal includes a first drive signal and a second drive signal. The voltage stabilizing unit includes a first switch and a second switch, wherein the first switch and the second switch are respectively configured to ground the output according to the first driving signal and the second driving signal, wherein the first driving signal and the second driving signal have opposite Phase.

In an embodiment, the first switch includes a first end coupled to the output end, the control end is configured to receive the first driving signal, and the second end is coupled to the ground end, and the second switch includes the first end coupled to the The output end and the control end are used to receive the second The driving signal and the second end are coupled to the ground.

In order to achieve the above object, a second aspect of the present invention relates to a display device including at least one scan line, a first driver, and a second driver. The first driver is located at one end of the scan line and the second driver is located at the other end of the scan line. One of the first driver and the second driver includes the on-off gate driver circuit of the first technical aspect.

In still another embodiment, the upper pull-up unit of the gate drive circuit on the array includes a first end, a control end, and a second end. The first end is for receiving the first X-level scan signal. The control end is coupled to the first end. The second end is coupled to the output end.

In an embodiment, the gate driving circuit of the gate has a first end, a control end and a second end. The first end is coupled to the output end. The control terminal is configured to receive the post Y-level scan signal. The second end is coupled to the ground end.

In another embodiment, the gate drive circuit on the array further includes a capacitor. The capacitor is coupled to the output terminal and configured to pull up the voltage level of the output terminal according to the first scan signal, so that the output terminal outputs the second high level control signal.

In still another embodiment, the pull-up control signal is a first high level control signal, and the voltage level of the second high level control signal is higher than a voltage level of the first high level control signal.

In still another embodiment, the first scan signal is generated after the pre-X scan signal.

In an embodiment, the post Y-level scan signal is generated after the first scan signal.

In another embodiment, the control circuit of the gate driving circuit on the array further includes a voltage stabilizing unit coupled to the output end and configured to be regulated according to The drive signal provided by the circuit outputs a low level control signal to the output.

In yet another embodiment, the drive signal includes a first drive signal and a second drive signal. The voltage stabilizing unit includes a first switch and a second switch, wherein the first switch and the second switch are respectively configured to ground the output according to the first driving signal and the second driving signal, wherein the first driving signal and the second driving signal have opposite Phase.

In one embodiment, the first switch of the voltage stabilizing unit includes a first end coupled to the output end, a control end for receiving the first driving signal, and a second end coupled to the ground end, and the second switch includes the first end The second terminal is coupled to the ground. The second terminal is coupled to the ground.

Therefore, according to the technical content of the present invention, an embodiment of the present invention provides a display device and an upper gate driving circuit for improving the brightness of the repaired display panel, and even the problem of abnormal operation of the GOA.

The basic spirit and other objects of the present invention, as well as the technical means and implementations of the present invention, will be readily apparent to those skilled in the art of the invention.

100, 100A‧‧‧ Array gate drive circuit

110‧‧‧Drive circuit

112, 114, 116‧‧‧ pull-up unit

118‧‧‧ Pulldown unit

120, 120A‧‧‧ control circuit

G(n-X)‧‧‧ pre-scanning signal

G(n+Y)‧‧‧ post-scanning signal

G(n-R), G(n+S)‧‧‧ scan signals

LC1, LC2‧‧‧ signal source

HC(n)‧‧‧ drive signal

122‧‧‧Stabilizer

130‧‧‧Variable circuit

600‧‧‧ display device

610‧‧‧First drive

620‧‧‧second drive

630‧‧‧Photo area

C‧‧‧ capacitor

G1~Gn‧‧‧ scan line

G(n)‧‧‧ scan signal

G(z)‧‧‧ scan signal

M‧‧‧ control signal

N1, N2‧‧‧ nodes

P(n), K(n)‧‧‧ drive signals

Out‧‧‧ output

During the period of P1~P3‧‧

ST(n-R)‧‧‧ starting signal

T32~T33, T42~T43, T51~T54, T61~T64, T71~T74‧‧‧ switch

Vss‧‧‧ grounding terminal

The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood.

FIG. 1 is a schematic diagram of a gate driving circuit on an array according to an embodiment of the invention.

FIG. 2 is a schematic diagram showing a connection relationship between circuits of each stage according to another embodiment of the present invention.

FIG. 3 is a schematic diagram showing a waveform according to still another embodiment of the present invention.

4 is a schematic diagram showing a gate driving circuit on an array according to still another embodiment of the present invention.

FIG. 5 is a schematic diagram showing a waveform according to another embodiment of the invention.

FIG. 6 is a schematic diagram of a display device according to an embodiment of the invention.

The various features and elements in the figures are not drawn to scale, and are in the In addition, similar elements/components are referred to by the same or similar element symbols throughout the different drawings.

The description of the embodiments of the present invention is intended to be illustrative and not restrictive. The features of various specific embodiments, as well as the method steps and sequences thereof, are constructed and manipulated in the embodiments. However, other specific embodiments may be utilized to achieve the same or equivalent function and sequence of steps.

The scientific and technical terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the invention pertains, unless otherwise defined herein. In addition, the singular noun used in this specification covers the plural of the noun in the case of no conflict with the context; the plural noun of the noun is also included in the plural noun used.

In addition, the term "coupled" as used herein may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, or that two or more elements are interoperable. Or action.

When the display panel adopts the structure of the gate driver on Array (GOA) on the dual-drive array, that is, the GOA drive circuit is respectively disposed at opposite ends of the scan line, and the drive signal line of the GOA circuit on either side A short circuit between the output nodes may cause the GOA circuit to output a multi-pulse driving signal to cause an abnormal operation. Therefore, the signal line of the short-circuited GOA circuit is cut by laser cutting to repair the display panel. The GOA circuit structure provided by the present invention can be operated normally after being repaired, and the scanning signal can still be output normally without being subjected to laser cutting without being repaired by the laser. The effect of the floating node generated by the side GOA circuit maintains the normal operation of the GOA circuit structure, and further improves the voltage regulation capability of the GOA circuit.

Please refer to FIG. 1 , which is a schematic diagram of an nth-level GOA circuit according to an embodiment of the present invention. If the signal line HC(n) of the GOA circuit is laser-cut, the GOA voltage regulator circuit 130 on the repair side is Node Q will assume a floating state. However, even in this case, when the normal side GOA circuit (not shown) outputs a scan signal, the patch side GOA circuit of the present embodiment does not cause the voltage stabilizing circuit 130 to be turned on due to the floating state described above, resulting in a scan line. A leakage path is generated through the voltage stabilizing circuit 130, thereby lowering the level of the scanning signal G(n) outputted by the normal side and the repair side GOA circuit. In order to improve the problem that the scanning signal G(n) level output by the conventionally repaired GOA circuit is lowered, the present invention proposes an improved GOA circuit which improves the conventional one without adding additional signal lines and the total number of transistors is not increased. The voltage regulation mechanism, detailed improvement means as described later.

As shown in FIG. 1, the nth stage GOA circuit 100 of the present embodiment includes a driving circuit 110, a control circuit 120, and a voltage stabilizing circuit 130. In operation, drive The driving circuit 110 is configured to generate a scanning signal G(n) to drive a panel (not shown). In order to avoid the laser cutting of the signal line HC(n) of the GOA circuit, the node Q of the driving circuit 110 of the GOA circuit on the conventional repair side may assume a floating state and cause the voltage stabilizing circuit 130 to be abnormal. The circuit 120 is in the GOA circuit, and the voltage stabilizing circuit 130 is coupled between the driving circuit 110 and the control node Out of the control circuit 120. The control circuit 120 is configured to use the pre-X-level scanning signal G(nX) and/or the rear Y-level. The signal G(n+Y) is scanned to output a control signal M to the voltage stabilizing circuit 130 to avoid the loss of the voltage stabilizing circuit 130 of the conventional GOA circuit due to the node Q connected to the floating state. Furthermore, the voltage stabilizing circuit 130 can be used to regulate the scan signal G(n).

Referring to FIG. 1, the X-stage scan signal G(nX) and the post-Y-level scan signal G(n+Y) received by the control circuit 120 are the first X-stage GOA circuit and the Y-stage GOA circuit of the GOA circuit 100. For the overall structure of the GOA circuit 100 and the above-mentioned front and rear stage circuits, please refer to FIG. 2, where the difference between the front and rear stage circuits and the GOA circuit 100 is four. As shown in FIG. 2, the GOA circuit 100 belongs to an nth stage circuit, which can be used to receive the previous 4-level scan signal G(n-4) provided by the (n-4)th stage circuit of the first 4 stages, and can also be used for receiving. The fourth (n+4)th stage circuit of the last four stages provides the subsequent four levels of scan signal G(n+4). In addition, the nth stage circuit can also provide the scan signal G(n) to the first (n-4)th stage circuit of the first 4 stages and the (n+4)th stage circuit of the last 4 stages.

In order to make the operation of the GOA circuit 100 shown in FIG. 1 easy to understand, please refer to FIG. 3, which is a schematic diagram of a waveform according to an embodiment of the invention. As shown in FIG. 1, the control circuit 120 includes a pull-up unit T71 and a pull-down unit T74, and has an output terminal Out. For operation, please refer to Figure 1 and Figure 3. In the figure P1, the front X-stage scan signal G(nX) is a high level signal, and the Y-stage scan signal G(n+Y) is a low level signal. At this time, the control circuit 120 pull-up unit T71 is used according to Before the high level, the X-level scan signal G(nX) outputs the high level control signal M to the output terminal Out, and the output terminal Out is pulled up. The switches T52 and T54 of the voltage stabilizing circuit 130 are turned on according to the high level control signal M to pull down the node N1. At this time, the node N1 outputs the low level driving signal P(n), and the switches T32 and T42 of the voltage stabilizing circuit 130 are turned off according to the low level driving signal P(n).

During the period P2, the front X-level scan signal G(n-X) is converted into a low level signal, and the Y-stage scan signal G(n+Y) is maintained at a low level signal. At this time, the output end Out continues to maintain a high level state. The switches T52 and T54 of the voltage stabilizing circuit 130 are continuously turned on according to the high level control signal M, and the node N1 is pulled down. At this time, the node N1 outputs the low level driving signal P(n), and the voltage regulating circuit 130 switches T32 and T42. The driving signal P(n) is turned off according to the low level, and the leakage paths of the switches T32 and T42 through which the circuit is transmitted are prevented, thereby maintaining the high level of the scanning signal G(n).

During the period P3, the front X-stage scan signal G(nX) maintains the low level signal, and then the Y-stage scan signal G(n+Y) is converted into the high level signal, and the pull-down unit T74 is used to scan the signal G according to the high level after the Y level ( n+Y) The output terminal Out is pulled down. Therefore, the output terminal Out outputs a low level control signal M. The switches T52 and T54 of the voltage stabilizing circuit 130 are turned off according to the low level control signal M. At this time, the node N1 can be pulled up to the high level according to the high level signal LC1, the node N1 outputs the high level driving signal P(n), and the switches T32 and T42 of the voltage stabilizing circuit 130 are driven according to the high level. The signal P(n) is turned on. It should be noted that The other voltage stabilizing structure shown in Figure 1 (including switches T33, T43 and T61~T64) operates in a similar manner to the above-mentioned voltage stabilizing structure (including switches T32, T42 and T51~T54), in order to simplify the description of the invention. This will not be repeated.

In summary, referring to FIG. 1, the switches T71 and T74 of the control circuit 120 of the GOA circuit 100 can be generated according to two sets of signals of the pre-X-level scan signal G(nX) and the post-Y-level scan signal G(n+Y). The control signal is used to control the voltage stabilizing control circuit (such as switches T51~T54 and T61~T64) in the voltage stabilizing circuit 130, thereby ensuring that the control node Q floating after the laser cutting does not affect the normal side GOA circuit (not shown in the figure) Show) the resulting output waveform. In still another embodiment, the parameters n, R, S, X, and Y shown in the GOA circuit 100 may each be a positive integer, where R, S, X, and Y are, for example, 4, but are not limited. Furthermore, the signal width of the control signal M can be adjusted depending on the scanning signal.

Please refer to FIG. 1 in detail. In detail, the pull-up unit T71 of the control circuit 120 includes a first end, a control end and a second end, and the first end of the pull-up unit T71 is configured to receive the front X-level scan signal G (nX). The control terminal of the pull-up unit T71 is coupled to the first end, and the second terminal of the pull-up unit T71 is coupled to the output terminal Out. Furthermore, the control unit 120 pull-down unit T74 also includes a first end, a control end and a second end. The first end of the pull-down unit T74 is coupled to the output terminal Out, the control end of the pull-down unit T74 is configured to receive the post-Y scan signal G(n+Y), and the second end of the pull-down unit T74 is coupled to the ground. End Vss. In an embodiment, the driving circuit 110 includes pull-up units 112, 114, 116 and a pull-down unit 118, and the pull-up units 112, 114, 116 can respectively scan the signal G(nR) according to the signal, the start signal ST(nR), The clock signal HC(n) pulls up the scan signal G(n), and the pull-down unit 118 pulls the scan signal G(n) according to the scan signal G(n+s).

4 is a schematic diagram showing a gate driving circuit on an array according to still another embodiment of the present invention. Compared with the GOA circuit 100 of FIG. 1 , the GOA circuit 100A further includes a capacitor C. The capacitor C is coupled to the output terminal Out and used to pull up the voltage of the output terminal Out according to the scan signal G(n). The bit causes the output terminal Out to output a control signal M having a higher level.

In order to make the operation of the GOA circuit 100A shown in FIG. 4 easy to understand, please refer to FIG. 5, which is a schematic diagram of a waveform according to another embodiment of the present invention. During the period P1, the control circuit 120 outputs the control signal M of the first high level L1 according to the X-level scan signal G(n-X) before the high level. During the period P2, the capacitor C is used to pull up the output terminal Out again according to the high level scan signal G(z), so that the output terminal Out outputs the control signal M of the second high level L2. As shown, the level of the control signal M of the second high level L2 is higher than the level of the control signal M of the first high level L1.

In summary, please refer to FIG. 4, except that the switches T71 and T74 of the control circuit 120 of the GOA circuit 100 can be based on the first X-level scan signal G(nX) and the latter Y-level scan signal G(n+Y). A control signal M is generated to control the voltage stabilization control circuit (such as switches T51~T54 and T61~T64) in the voltage stabilization circuit 130, and another capacitor C is connected between the output terminals Out and G(z), wherein G (z) represents any gate pulse (Gate Pulse) between the pre-X scan signal G(nX) and the post Y scan signal G(n+Y), that is, Z is between nX and n A positive integer between +Y. The purpose of additionally configuring the capacitor C is to increase the voltage of the output terminal Out by coupling to increase the gate voltage of the switches T52, T54, T62, and T64 to improve the pull-down capability. In this way, the design size of the Thin-Film Transistor (TFT) can be reduced.

In another embodiment, please continue to refer to FIG. 4, the high-level scan signal G(z) is generated after the high-level pre-X-level scan signal G(nX), and the high-level post-Y-level scan signal G is generated. (n+Y) is generated after the high level of the scanning signal G(z). In other words, the scan signal G(z) may be a scan signal in the interval from the pre-X-stage scan signal G(n-X) to the post-Y-stage scan signal G(n+Y), such as the local-level scan signal G(n).

In another embodiment, the control circuit 120A further includes a voltage stabilizing unit 122 coupled to the output terminal Out, which can be used according to at least one driving signal provided by the voltage stabilizing circuit 130 (eg, the driving signal K(n) ), P(n)) outputs a low level control signal M to the output terminal Out. In this embodiment, the voltage stabilizing unit includes switches T72 and T73, and the switches T72 and T73 are respectively used to ground the output terminal Out according to the driving signal K(n) and the driving signal P(n), thereby enabling the output terminal Out. The output control signal M is stably maintained at a low level.

In order to make the operation of the voltage stabilizing unit 122 shown in FIG. 4 easy to understand, please refer to FIG. 5, before or after the period P1, the control signal M outputted by the output terminal Out is a low level signal, and the voltage stabilizing circuit 130 The switches T52, T54 or switches T62, T64 are turned off according to the low level control signal M. At this time, the node N1 or N2 outputs a high level driving signal P(n) or K(n) according to the signal source LC1 or LC2, respectively, and the switch T72 or T73 drives the signal P(n) or K(n) according to the high level. And turned on to ground the output terminal Out, thereby stably maintaining the control signal M at a low level. In this way, the output terminal Out can be controlled by the components inside the control circuit 120A at any stage, thereby ensuring that the output terminal Out does not have a floating condition.

In an embodiment, the drive signals P(n), K(n) are respectively received by the letter The sources LC1, LC2 are controlled, and the signals provided by the signal sources LC1, LC2 are opposite in phase. Referring to FIG. 5, before or during the period P1, the switches T52, T54 or the switches T62 and T64 of the voltage stabilizing circuit 130 are turned off according to the low level control signal M. At this time, the node N1 is provided according to the signal source LC1. The high level signal outputs a high level of the drive signal P(n). At the same time, the signal source LC2 provides a low level signal opposite to the signal source LC1, and the node N2 outputs a low level drive signal K(n) according to the low level signal provided by the signal source LC2. Therefore, before or during the period P1, the drive signal P(n) has an opposite phase to the drive signal K(n).

In another embodiment, referring to FIG. 4, the switch T72 includes a first end, a control end, and a second end. The first end is coupled to the output end Out, and the control end is configured to receive the driving signal K(n). The second end is coupled to the ground terminal Vss. In addition, the switch T73 includes a first end, a control end, and a second end, the first end of which is coupled to the output end Out, the control end is configured to receive the driving signal P(n), and the second end is coupled to the ground end Vss.

FIG. 6 is a schematic diagram of a display device according to an embodiment of the invention. As shown, the display device 600 includes at least one scan line (such as one of the scan lines G1 G Gn), a first driver 610, a second driver 620, and a pixel area 630. In the configuration, the first driver 610 is located at one end of the scan line (such as the scan line G1), and the second driver 620 is located at the other end of the scan line (such as the scan line G1). One of the first driver 610 and the second driver 620 includes the GOA circuit 100 shown in FIG. 1 or the GOA circuit 100A shown in FIG. It can be seen that the GOA circuits 100 and 100A shown in FIGS. 1 and 4 can be applied to the architecture of the gate driving circuit on the dual-drive array. It should be noted that Figures 1 and 4 show The basic architecture of the illustrated GOA circuits 100, 100A has been described above and will not be described herein.

It will be apparent from the above-described embodiments of the present invention that the application of the present invention has the following advantages. The embodiment of the present invention provides a display device and a GOA circuit. The voltage stabilization circuit of the GOA circuit is coupled to a control node of the control circuit, and the control circuit is configured to output a control signal to the voltage stabilization circuit according to the scan signals of each level to avoid The voltage stabilizing circuit of the conventional GOA circuit is coupled to the missing node Q that exhibits the floating state. In addition, the control circuit of the GOA circuit additionally configures a capacitor to increase the voltage at the output of the control circuit by coupling a high level of the scan signal to increase the gate voltage of the transistor to improve its pull-down capability. In this way, the design size of the TFT can be reduced.

Although the embodiments of the present invention are disclosed in the above embodiments, the present invention is not intended to limit the invention, and the present invention may be practiced without departing from the spirit and scope of the invention. Various changes and modifications may be made thereto, and the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Array gate drive circuit

110‧‧‧Drive circuit

112, 114, 116‧‧‧ pull-up unit

118‧‧‧ Pulldown unit

120‧‧‧Control circuit

130‧‧‧Variable circuit

G(n)‧‧‧ scan signal

G(n-X)‧‧‧ pre-scanning signal

G(n+Y)‧‧‧ post-scanning signal

G(n-R), G(n+S)‧‧‧ scan signals

LC1, LC2‧‧‧ signal source

HC(n)‧‧‧ drive signal

M‧‧‧ control signal

N1, N2‧‧‧ nodes

P(n), K(n)‧‧‧ drive signals

Q(n)‧‧‧ signal

Out‧‧‧ output

ST(n-R)‧‧‧ starting signal

T32~T33, T42~T43, T51~T54, T61~T64, T71, T74‧‧‧ switch

Vss‧‧‧ grounding terminal

Claims (18)

An array upper gate driving circuit comprising: a driving circuit for generating a scanning signal of a level; a control circuit comprising an output end, a pull-up unit and a pull-down unit, wherein the pull-up unit is used according to The first X-level scan signal provides a pull-up control signal to the output terminal, and the pull-down unit is configured to provide a pull-down control signal to the output terminal according to a post-Y-level scan signal, and the output terminal is configured to use the pull-up control signal according to the pull-up control signal Or a pull-down control signal to output a control signal, wherein X, Y are positive integers; and a voltage stabilizing circuit coupled between the driving circuit and the output terminal for stabilizing the scan signal according to the control signal The pull-up unit includes: a first end for receiving the front X-level scan signal; a control end coupled to the first end; and a second end coupled to the output end. The gate driving circuit of the array of claim 1, wherein the pull-down unit comprises: a first end coupled to the output end; a control end for receiving the post Y-level scan signal; and a second The end is coupled to a ground end. The gate driving circuit on the array according to claim 1 or 2, further comprising: a capacitor coupled to the output terminal for pulling up the voltage level of the output terminal according to a first scan signal, and causing the output terminal to output a second high level control signal. The gate upper gate driving circuit of claim 3, wherein the pull-up control signal is a first high level control signal, and the voltage level of the second high level control signal is higher than the first high level control signal Voltage level. The on-array gate driving circuit of claim 3, wherein the first scan signal is generated after the pre-X-level scan signal. The gate upper gate driving circuit of claim 5, wherein the rear Y-level scanning signal is generated after the first scanning signal. The gate drive circuit of the array of claim 3, wherein the control circuit further comprises: a voltage stabilizing unit coupled to the output terminal for driving a signal according to the voltage regulator circuit to output the output terminal A low level control signal is output. The gate driving circuit of the array of claim 7, wherein the driving signal comprises a first driving signal and a second driving signal, the voltage stabilizing unit comprises: a first switch and a second switch, respectively According to the first driving signal And the second driving signal to ground the output terminal, wherein the first driving signal and the second driving signal have opposite phases. The gate drive circuit of the array of claim 8, wherein the first switch includes a first end coupled to the output end, a control end for receiving the first drive signal, and a second end coupled to the second end A grounding end, the second switch includes a first end coupled to the output end, a control end for receiving the second driving signal, and a second end coupled to a ground end. A display device comprising: at least one scan line; a first driver at one end of the scan line; and a second driver at the other end of the scan line, wherein one of the first driver and the second driver The gate drive circuit on the array as described in claim 1 is included. The display device of claim 10, wherein the pull-down unit of the gate driving circuit of the array comprises: a first end coupled to the output end; and a control end configured to receive the post Y-level scan signal; And a second end for coupling to a ground. The display device of claim 10 or 11, wherein the gate driving circuit on the array further comprises: a capacitor coupled to the output terminal for pulling up the voltage level of the output terminal according to a first scan signal, and causing the output terminal to output a second high level control signal. The display device of claim 12, wherein the pull-up control signal is a first high level control signal, and the voltage level of the second high level control signal is higher than a voltage level of the first high level control signal. The display device of claim 12, wherein the first scan signal is generated after the pre-X scan signal. The display device of claim 14, wherein the subsequent Y-level scan signal is generated after the first scan signal. The display device of claim 12, wherein the control circuit of the gate driving circuit of the array further comprises: a voltage stabilizing unit coupled to the output terminal for driving a signal according to a voltage provided by the voltage stabilizing circuit A low level control signal is output to the output. The display device of claim 16, wherein the driving signal comprises a first driving signal and a second driving signal, the voltage stabilizing unit comprises: a first switch and a second switch, respectively, according to the first Driving a signal and the second driving signal to ground the output, wherein the first driving signal is The second drive signal has an opposite phase. The display device of claim 17, wherein the first switch includes a first end coupled to the output end, a control end for receiving the first driving signal, and a second end coupled to a ground end, The second switch includes a first end coupled to the output end, a control end for receiving the second driving signal, and a second end coupled to a ground end.