TWI460702B - Display device and shift register thereof - Google Patents

Display device and shift register thereof Download PDF

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Publication number
TWI460702B
TWI460702B TW101126019A TW101126019A TWI460702B TW I460702 B TWI460702 B TW I460702B TW 101126019 A TW101126019 A TW 101126019A TW 101126019 A TW101126019 A TW 101126019A TW I460702 B TWI460702 B TW I460702B
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Taiwan
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unit
voltage
end
electrically coupled
control
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TW101126019A
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Chinese (zh)
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TW201405508A (en
Inventor
Jyu Yu Chang
jun wei Lai
Po Yuan Shen
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Au Optronics Corp
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Publication of TWI460702B publication Critical patent/TWI460702B/en

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Description

Display device and shift register circuit thereof

The present invention relates to a scan driving circuit, and more particularly to a shift register circuit and a display device therefor.

With the current demand for a narrow bezel of a display device on the market, it may be desirable to reduce the volume/area of the shift temporary storage circuit inside the display device (for example, a liquid crystal display device) to conform to the thinner and wider border of the display device. A narrower appeal. However, the conventional shift register circuit cannot reduce the components in order to maintain circuit stability, and therefore still occupies a considerable volume/area in the display device, and it is difficult to reduce the thickness of the display device and the size of the frame of the display device.

In the current manufacturing process of the display device, the technology of the built-in scan driver circuit (Gate driver on Array, GOA) is used to fabricate the shift temporary storage circuit, so as to conform to the trend of light, thin and short design.

However, when the current gate driving circuit substrate is in an off state, it is usually 0 volts as a switching voltage of a switching element (for example, an α-Si TFT or an IGZO TFT, etc.), but sometimes because of a switching element. The characteristic causes the shutdown voltage to drift and cause leakage current, and in severe cases, the output temporary circuit may cause output failure.

The invention provides a shift temporary storage circuit and a display device thereof, which can improve the leakage current caused by the drift of the switching element due to the off voltage, and further reduce the circuit layout area of the shift temporary storage circuit.

Therefore, the shift register circuit of the present invention includes: a pull-up unit, a driving unit, a first control unit, a first pull-down unit, a second control unit, a second pull-down unit, and a voltage adjusting unit. The pull-up unit is configured to output a first driving voltage according to the first clock signal, the third scan signal, and the second driving voltage. The driving unit has a first end receiving a second clock signal opposite to the phase of the first clock signal, a control end electrically coupled to the pull-up unit, and a second outputting the first scan signal end. The first control unit is electrically coupled to the control end of the driving unit and the voltage source for pulling down the potential of the control terminal of the driving unit to the first voltage according to the first system clock signal. The first pull-down unit has a first end electrically coupled to the second end of the driving unit, a second end electrically coupled to the output end of the voltage adjusting unit, and a control for receiving the second scanning signal end. The second control unit is electrically coupled to the control end of the driving unit and the voltage source for pulling down the potential of the control end of the driving unit to the first voltage according to the second system clock signal. The second pull-down unit has a first end electrically coupled to the control end of the driving unit, a second end electrically coupled to the output end of the voltage adjusting unit, and a control end receiving the second scanning signal. The voltage adjustment unit is electrically coupled to the voltage source for outputting the second voltage.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

Please refer to FIG. 1A. FIG. 1A is a schematic diagram of a shift temporary storage circuit according to an embodiment of the present invention. As shown in FIG. 1A, the Nth stage shift register unit 100 of the embodiment of the present invention includes a pull-up unit 10, a driving unit 20, a first control unit 30, a first pull-down unit 33, and a second control unit 40. Second pull-down unit 43 and voltage Adjustment unit 50.

The pull-up unit 10 is configured to output the first driving voltage Q(n) according to the first clock signal HC1, the third scanning signal G(n-1), and the second driving voltage Q(n-1). More specifically, the pull-up unit 10 includes a switching element 10a and a switching element 10b. The switching element 10a and the switching element 10b can be formed, for example, of an N-type thin film transistor. The first end of the switching element 10a receives the first clock signal HC1, and the control end of the switching element 10a receives the second driving of the output of the pull-up unit of the N-1th stage shift register unit (not shown). Voltage Q(n-1). The first end of the switching element 10b receives the third scanning signal G(n-1) outputted by the N-1th stage shifting unit, and the control end of the switching element 10b is electrically coupled to the second end of the switching element 10a. The second end of the switching element 10b is for outputting the first driving voltage Q(n).

The driving unit 20 has a first end 21 for receiving the second clock signal HC2, a control end 23 electrically coupled to the pull-up unit 10, and a second end 25 for outputting the first scanning signal G(n). More specifically, the driving unit 20 includes a switching element 20a, which may be formed, for example, by an N-type thin film transistor, and the first end 21 of the switching element 20a receives the first clock signal. The second clock signal HC2 of the opposite phase of the HC1, the control terminal 23 of the switching element 20a is electrically coupled to the pull-up unit 10. When the switching element 20a is in the conducting state, the second terminal 25 of the switching element 20a outputs the first scanning signal. G(n).

The first control unit 30 is electrically coupled to the control terminal 23 of the driving unit 20 and the voltage source VSS, and pulls down the potential of the control terminal 23 of the driving unit 20 to the voltage source VSS according to the first system clock signal LC1. The first voltage. The first control unit 30 includes switching elements 30a to 30f. The switching elements 30a to 30f may be formed, for example, of an N-type thin film transistor. The first end of the switching element 30f is electrically coupled to the second end of the driving unit 20 and the first end of the energy storage unit C. The second end of the energy storage unit C is electrically coupled to the first drive Dynamic voltage Q(n). The second end of the switching element 30f is electrically coupled to the output of the voltage adjusting unit 50 to receive the second voltage output by the voltage adjusting unit 50. It is worth noting that the potential of the second voltage is higher than the potential of the first voltage. For example, the potential of the second voltage can be -6 volts, and the potential of the first voltage can be -9 volts. The control end of the switching element 30f is electrically coupled to the control end of the switching element 30e. The first end of the switching element 30e is electrically connected to the second end of the switching element 10b of the pull-up unit 10. The second end of the switching element 30e is electrically coupled to the voltage source VSS to receive the first voltage. The control end and the first end of the switching element 30a are configured to receive the first system clock signal LC1.

As shown in FIG. 1A, the first end of the switching element 30b is electrically coupled to the second end of the switching element 30a, and the control end of the switching element 30b is configured to receive the first driving voltage Q(n), and the switching element 30b The two ends are electrically coupled to the voltage source VSS to receive the first voltage. The first end of the switching element 30c is electrically coupled to the first end of the switching element 30a, the control end of the switching element 30c is electrically coupled to the second end of the switching element 30a, and the second end of the switching element 30c is electrically coupled. Connected to the control terminal of the switching element 30e. The first end of the switching element 30d is electrically coupled to the second end of the switching element 30c, the control end of the switching element 30d is electrically coupled to the first driving voltage Q(n), and the second end of the switching element 30d is electrically The voltage source VSS is coupled to receive the first voltage.

The first pull-down unit 33 has a first end electrically coupled to the second end 25 of the driving unit 20, and a second end electrically coupled to the output end of the voltage adjusting unit 50 for receiving the second voltage. And receiving a control end of the second scan signal G(n+1). The first pull-down unit 33 is configured to pull down the potential of the second terminal 25 of the driving unit 20 to the second voltage according to the second scanning signal G(n+1). More specifically, the first pull-down unit 33 includes a switching element 33a, which may be formed, for example, of an N-type thin film transistor. The switching element 33a The first end is electrically coupled to the second end of the switching element 20a of the driving unit 20, and the control end of the switching element 33a receives the second scanning signal output by the N+1th stage shifting unit (not shown) G(n+1), and the second end of the switching element 33a is electrically coupled to the output of the voltage adjusting unit 50 for receiving the second voltage.

The second control unit 40 is electrically coupled to the control terminal 23 of the driving unit 20 and the voltage source VSS, and pulls down the potential of the control terminal 23 of the driving unit 20 to the voltage source VSS according to the second system clock signal LC2. The first voltage. The second control unit 40 includes switching elements 40a-40f. The switching elements 40a-40f can be formed, for example, of an N-type thin film transistor. The first end of the switching element 40f is electrically coupled to the second end of the driving unit 20, and the second end of the switching element 40f is electrically coupled to the output end of the voltage adjusting unit 50 to receive the second voltage. The control end of the switching element 40f is electrically coupled to the control end of the switching element 40e. The first end of the switching element 40e is electrically connected to the second end of the switching element 10b of the pull-up unit 10, and the second end of the switching element 40e is electrically coupled to the voltage source VSS to receive the first voltage. The control end and the first end of the switching element 40a are configured to receive the second system clock signal LC2.

As shown in FIG. 1A, the first end of the switching element 40b is electrically coupled to the second end of the switching element 40a, the control end of the switching element 40b is configured to receive the first driving voltage Q(n), and the first of the switching element 40b The two ends are electrically coupled to the voltage source VSS to receive the first voltage. The first end of the switching element 40c is electrically coupled to the first end of the switching element 40a, the control end of the switching element 40c is electrically coupled to the second end of the switching element 40a, and the second end of the switching element 40c is electrically coupled. Connected to the control terminal of the switching element 40e. The first end of the switching element 40d is electrically coupled to the second end of the switching element 40c, the control end of the switching element 40d is electrically coupled to the first driving voltage Q(n), and the second end of the switching element 40d is electrically The voltage source VSS is coupled to receive the first voltage.

The second pull-down unit 43 has a first end electrically coupled to the control end 23 of the driving unit 20, a second end electrically coupled to the output end of the voltage adjusting unit 50, for receiving the second voltage, and a Receiving the control end of the second scan signal G(n+1). The second pull-down unit 43 is configured to pull down the potential of the control terminal of the driving unit 20 to the second voltage according to the second scanning signal G(n+1). More specifically, the second pull-down unit 43 includes a switching element 43a, which may be formed, for example, of an N-type thin film transistor. The first end of the switching element 43a is electrically coupled to the control end of the switching element 20a of the driving unit 20, and the control end of the switching element 43a receives the output of the (N+1)th shifting temporary storage unit (not shown). The second scan signal G(n+1), and the second end of the switching element 43a is electrically coupled to the output of the voltage adjusting unit 50 to receive the second voltage.

The voltage adjustment unit 50 is electrically coupled to the voltage source VSS to receive the first voltage. The voltage adjustment unit 50 is configured to convert the first voltage into a second voltage and output the second voltage to the first pull-down unit 33 and the second pull-down unit 43.

Please refer to FIG. 1B. FIG. 1B is a schematic circuit diagram of a voltage adjustment unit according to an embodiment of the present invention. As shown in FIG. 1B, the voltage adjustment unit 50 of the shift register unit 101 includes a switching element T1. The switching element T1 has a control terminal 13 , a control terminal 13 electrically coupled to the switching element T1 , a first end 11 of the first control unit 30 and the second control unit 40 , and an electrical coupling voltage The second end 15 of the source VSS. More specifically, the switching element T1 can be, for example, an N-type thin film transistor. The first end 11 of the switching element T1 is electrically coupled to the second end of the switching element 30f and the second end of the switching element 40f. The second end 15 of the switching element T1 is configured to receive the first voltage and be electrically coupled. To the first control unit 30 and the second control unit 40.

It is worth mentioning that the shift register unit 100 of the present invention uses the voltage adjusting unit 50 to provide the required second voltage, so the shift register unit 100 is shifted. It is only necessary to receive the first voltage supplied from the voltage source VSS outside the shift register circuit without additionally receiving the second voltage. In this way, the circuit wiring area of the power line can be reduced.

Next, please refer to FIG. 1C. FIG. 1C is another schematic diagram of a circuit of a voltage adjustment unit according to an embodiment of the present invention. As shown in FIG. 1C, the voltage adjustment unit 50 of the shift register unit 102 includes a diode D1. The diode D1 has a positive terminal (not shown) and a negative terminal (not shown). The negative terminal of the diode D1 is electrically coupled to the voltage source VSS for receiving the first voltage, and the positive terminal of the diode D1 is configured to output the second voltage.

Next, please refer to FIG. 2. FIG. 2 is a schematic diagram of control timing according to an embodiment of the present invention, wherein a horizontal axis is represented as time and a vertical axis is represented as a voltage. As shown in FIG. 2, the first clock signal HC1 is opposite in phase to the second clock signal HC2. When the first system clock signal LC1 is at a high level and the first driving voltage Q(n) is at a low level, the first control unit 30 outputs a high level signal, thereby opening the first pull down unit 33 and the second The pull-down unit 43 pulls down the first drive control voltage Q(n) through the second voltage, thereby turning off the drive unit 20. When the first driving voltage Q(n) is at a high level, the first control unit 30 is pulled to the first voltage to present a low level, and the first pull-down unit 33 and the second pull-down unit 43 are turned off to make the first scan. The signal G(n) does not cause leakage through the pull-down unit, ensuring that the first scan signal G(n) has the correct waveform. In addition, the first system clock signal LC1 is opposite to the second system clock signal LC2. When the second system clock signal LC2 is at a high level, and the first system clock signal LC1 is at a low level, the first system can be used alternately. The second control unit 40 and the first control unit 30 thereby extend the life of the switch.

Please refer to FIG. 1A and FIG. 3 together. FIG. 3 is a schematic diagram of a display device according to an embodiment of the present invention. As shown in FIG. 3, the display device 300 of the embodiment of the present invention includes a display unit 310, a data driving unit 320, and a scan driving unit 330. Timing control unit 340. The display device is, for example, a liquid crystal display device, a plasma display panel (PDP), an electroluminescent display device, an electrophorec display device, and a field emission display device ( Field emission display), etc., but not limited thereto, any display device requiring timing output is encompassed by the scope of the embodiments of the present invention.

The display unit 310 includes a plurality of scan lines and a plurality of data lines (not shown) for respectively receiving the plurality of scan signals output by the scan driving unit 330, and the plurality of data signals output by the data driving unit 320. Display the screen. The data driving unit 320 is electrically coupled to the data line in the display unit 310 to provide the data signal to the data line. The scan driving unit 330 is electrically coupled to the scan line in the display unit 310 to provide the scan signal to the scan line.

As shown in FIG. 3, the scan driving unit 330 includes a plurality of stages of shift register units, such as the shift register unit 100, the shift register unit 110, ... to the shift register unit 190. The shift register unit 110... to the shift register unit 190 may have the same or similar architecture to the shift register unit 100. The output of the Nth stage shift register unit 100 is electrically coupled to the display unit 310 and the shift register unit 110 of the (N+1)th stage. The output of the N+1th stage shift register unit 110 is electrically coupled to the display unit 310 and the N+2 stage shift register unit, and so on to the shift register unit. 190.

As described above, the shift register unit 100, the shift register unit 110, and the shift register unit 190 receive the first voltage through the voltage source VSS, respectively, and the pass voltage adjustment unit 50 acquires the required second voltage. As shown in FIG. 3, the timing control unit 340 is electrically coupled to the data driving unit 320 and the scan driving unit 330 to control the data driving unit 320 and the scan driving unit 330.

In summary, the shift register unit of the present invention and the display device thereof are designed such that the switching elements of the driving unit can be maintained in a closed state during the output pull-down period, thereby improving the switching elements of the driving unit. The problem of leakage current is caused by the drift of the off voltage. In addition, the shift register unit of the present invention further reduces the circuit layout area of the shift register circuit through the voltage adjusting unit.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

10‧‧‧Upper pull unit

11‧‧‧ first end

13‧‧‧Control terminal

15‧‧‧second end

100‧‧‧Shift register unit

101‧‧‧Shift register unit

102‧‧‧Shift register unit

110‧‧‧Shift register unit

190‧‧‧Shift register unit

20‧‧‧Drive unit

21‧‧‧ first end

23‧‧‧Control terminal

25‧‧‧ second end

30‧‧‧First Control Unit

300‧‧‧ display device

310‧‧‧Display unit

320‧‧‧Data Drive Unit

330‧‧‧Scan Drive Unit

340‧‧‧Sequence Control Unit

33a‧‧‧First pulldown unit

40‧‧‧Second control unit

43a‧‧‧Secondary pull-down unit

50‧‧‧Voltage adjustment unit

C‧‧‧ Energy storage unit

D1‧‧‧ diode

G(n)‧‧‧ first scan signal

G(n+1)‧‧‧second scan signal

G(n-1)‧‧‧ third scan signal

HC1‧‧‧ first clock signal

HC2‧‧‧ second clock signal

LC1‧‧‧ first system clock signal

LC2‧‧‧Second system clock signal

T1‧‧‧ switching components

10a‧‧‧Switching elements

10b‧‧‧Switching elements

20a‧‧‧Switching elements

33a‧‧‧Switching elements

43a‧‧‧Switching elements

30a~30f‧‧‧Switching elements

40a~40f‧‧‧Switching elements

Q(n)‧‧‧First drive voltage

Q(n-1)‧‧‧second drive voltage

VSS‧‧‧voltage source

FIG. 1A is a schematic diagram of a shift temporary storage circuit according to an embodiment of the present invention.

FIG. 1B is a schematic circuit diagram of a voltage adjustment unit according to an embodiment of the present invention.

FIG. 1C is a schematic diagram of another circuit of a voltage adjustment unit according to an embodiment of the present invention.

2 is a schematic diagram of control timing according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a display device according to an embodiment of the invention.

10‧‧‧Upper pull unit

100‧‧‧Shift register unit

20‧‧‧Drive unit

21‧‧‧ first end

23‧‧‧Control terminal

25‧‧‧ second end

30‧‧‧First Control Unit

33‧‧‧First pulldown unit

40‧‧‧Second control unit

43‧‧‧Secondary pull-down unit

50‧‧‧Voltage adjustment unit

G(n)‧‧‧ first scan signal

G(n+1)‧‧‧second scan signal

G(n-1)‧‧‧ third scan signal

HC1‧‧‧ first clock signal

HC2‧‧‧ second clock signal

LC1‧‧‧ first system clock signal

LC2‧‧‧Second system clock signal

10a‧‧‧Switching elements

10b‧‧‧Switching elements

20a‧‧‧Switching elements

33a‧‧‧Switching elements

43a‧‧‧Switching elements

30a~30f‧‧‧Switching elements

40a~40f‧‧‧Switching elements

Q(n)‧‧‧First drive voltage

Q(n-1)‧‧‧second drive voltage

VSS‧‧‧voltage source

Claims (10)

  1. A shift register circuit includes a plurality of shift register units, wherein each of the shift register units includes: a pull-up unit for performing a third scan signal according to a first clock signal, and a second driving voltage, outputting a first driving voltage; a driving unit having a first end for receiving a second clock signal opposite to the phase of the first clock signal, and a control terminal electrically coupled to the The pull-up unit and the second end are configured to output a first scan signal; a voltage adjustment unit having an input electrically coupled to a voltage source and an output outputting a second voltage; a control unit electrically coupled to the control terminal of the driving unit and the voltage source for causing a potential of the control terminal of the driving unit to be pulled down to a first voltage of the voltage source according to a first system clock signal a first pull-down unit having a first end electrically coupled to the second end of the drive unit, a second end electrically coupled to the output of the voltage adjustment unit, and a control end for receiving a second scan signal; a second control And electrically coupled to the control end of the driving unit and the voltage source for causing the potential of the control end of the driving unit to be pulled down to the first voltage according to a second system clock signal; and a second pulldown The unit has a first end electrically coupled to the control end of the driving unit, a second end electrically coupled to the output end of the voltage adjusting unit, and a control end for receiving the second scanning signal.
  2. The shift register circuit of claim 1, wherein the first scan signal is an Nth scan signal, and the second scan signal is an N+1 The level scan signal, and the third scan signal is the N-1th scan signal.
  3. The shift register circuit of claim 2, wherein the voltage adjusting unit is a switching element having a first end electrically coupled to the voltage source and a second end outputting the first The second voltage is electrically coupled to the second end of the switching element.
  4. The shift register circuit of claim 2, wherein the voltage adjusting unit is a diode having a positive terminal and a negative terminal, and the negative terminal of the diode is electrically coupled to the diode A voltage source, the positive terminal of the diode is used to output the second voltage.
  5. The shift register circuit of claim 3, wherein the potential of the second voltage is higher than the potential of the first voltage.
  6. A display device includes: a display unit for receiving a plurality of scan signals and a plurality of data signals respectively for displaying a picture; a data driving unit electrically coupled to the display unit, the data driving unit for providing The data is transmitted to the plurality of data lines in the display unit; the scan driving unit is electrically coupled to the display unit, and the scan driving unit is configured to provide the scan signals to the plurality of scan lines in the display unit a timing control unit electrically coupled to the data driving unit and the scan driving unit for controlling the data driving unit and the scan driving unit; wherein the scan driving unit comprises a plurality of shift register units, Each of the shift register units includes: a pull-up unit for outputting a first driving voltage according to a first clock signal, a third scan signal, and a second driving voltage; a driving unit having a first end for receiving a second clock signal having a phase opposite to a clock signal, electrically coupled to the control terminal of the pull-up unit, and a second end of the output first scan signal; a voltage adjustment unit, an electrical coupling An input terminal connected to a voltage source and an output terminal for outputting a second voltage; a first control unit electrically coupled to the control terminal of the driving unit and the voltage source for using a first system a pulse signal, the potential of the control terminal of the driving unit is pulled down to a first voltage of the voltage source; a first pull-down unit having a first end electrically coupled to the second end of the driving unit, a second end connected to the output end of the voltage adjusting unit, and a control end receiving a second scanning signal; a second control unit electrically coupled to the control end of the driving unit and the voltage source, Based on a second system clock signal The potential of the control terminal of the driving unit is pulled down to the first voltage; and a second pull-down unit has a first end electrically coupled to the control end of the driving unit, and is electrically coupled to the voltage adjusting unit The second end of the output end and a control end that receives the second scan signal.
  7. The display device of claim 6, wherein the Nth scan line is electrically connected to the first scan signal, and the (N+1)th scan line is electrically connected to the second scan signal, and the Nth One scan line is electrically connected to the third scan signal.
  8. The display device of claim 7, wherein the voltage is adjusted The whole unit is a switching element having a first end electrically coupled to the voltage source, a second end outputting the second voltage, and a second end electrically coupled to the control end of the second end of the switching element.
  9. The display device of claim 7, wherein the voltage adjustment unit is a diode having a positive terminal and a negative terminal, and the negative terminal of the diode is electrically coupled to the voltage source. The positive terminal of the diode is used to output the second voltage.
  10. The display device of claim 8 or 9, wherein the potential of the second voltage is higher than the potential of the first voltage.
TW101126019A 2012-07-19 2012-07-19 Display device and shift register thereof TWI460702B (en)

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TW101126019A TWI460702B (en) 2012-07-19 2012-07-19 Display device and shift register thereof
CN201210337984.3A CN102903321B (en) 2012-07-19 2012-09-13 Display device and shift register circuit thereof

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CN102903321B (en) 2016-01-20
CN102903321A (en) 2013-01-30
TW201405508A (en) 2014-02-01

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