TWI544461B - Gate-driving circuit - Google Patents

Description

Gate drive circuit

The present invention relates to a driving circuit, and more particularly to a gate driving circuit.

The conventional gate drive circuit architecture is usually implemented with four transistors and one capacitor (4T1C). 1 is a circuit diagram of a conventional gate drive circuit. As shown in FIG. 1, the gate driving circuit 100 includes a transistor 10, a transistor 20, a transistor 30, a transistor 40, and a capacitor 50. One end of the transistor 10 and the control terminal jointly receive the start signal ST, and the other end of the transistor 10 inputs the start signal ST to the node Q. One end of the transistor 30 receives the clock signal CK, and the other end of the transistor 30 The gate signal G _[N] is output according to the clock signal CK. The transistor 20 and the control terminal of the transistor 40 collectively receive the gate signal G _{[N+1] of the} next stage, and the transistor 40 resets the node Q and the transistor 30 according to the gate signal G _{[N+1] of the} next stage. The potential of one end of the output gate signal G _[N] .

The gate driving circuit 100 of the 4T1C described above generally receives only one start signal during the display of a screen (not shown), and correspondingly outputs a gate signal to one of the scan lines of the display (Fig. Not shown). Specifically, since the potential of the node Q is reset by the transistor 40 and the transistor 30 cannot be turned on when the gate signal G _{[N+1] of the} next stage is generated, the transistor 30 cannot be turned on at this point of time. The gate signal G _{[N] is} output again.

In addition, since the gate driving circuit 100 does not have a voltage stabilizing function, after the transistor 30 outputs the gate signal G _[N] , the output terminals of the node Q and the gate signal G _[N] are substantially in a floating state. Therefore, the potential may be unstable due to the influence of the clock signal CK, resulting in unstable waveform of the output signal G _[N] .

In addition, in order to be able to output the gate signal G _[N] quickly and efficiently, the size of the transistor 30 is generally large, and in order to be able to be generated in the next stage of the gate signal G _[N+1] , The potential of the node Q and the output of the gate signal G _{[N] is} reset, so the size of the transistor 40 must correspond to the transistor 30, which causes two large-sized electrodes to be used simultaneously in the same gate driving circuit 100. The crystal makes it difficult to reduce the area of the circuit.

The present invention provides a gate drive circuit that can improve various disadvantages of the conventional gate drive circuit described above.

The invention provides a gate driving circuit for providing a gate signal to a display, and the display is used for displaying a plurality of display screens. The gate driving circuit includes a gate signal generating circuit, a voltage stabilizing control circuit, and a voltage stabilizing circuit. The gate signal generating circuit receives the start signal, the first timing signal and the second timing signal, and outputs the gate signal to one of the scan lines according to the start signal, the first timing signal and the second timing signal. The voltage stabilization control circuit receives the first potential, the second potential, and the first timing signal, and outputs the voltage stabilization control signal according to the first potential, the second potential, and the first timing signal. The voltage stabilizing circuit receives the first potential and the voltage stabilization control signal, and according to the first potential and the voltage stabilization control signal And output the voltage regulator signal to the gate signal generating circuit, so that the gate signal generating circuit is in a regulated state when the gate signal is not output. The gate signal generating circuit receives the plurality of start signals during the display of each display screen, and correspondingly outputs the plurality of gate signals to one of the scan lines during each display screen.

In a preferred embodiment of the invention, the gate signal generating circuit includes a first transistor, a second transistor, and a capacitor. The first transistor has a control end, a first end, and a second end. The control end of the first transistor is configured to receive the first timing signal, and the second end of the first transistor is configured to receive the start signal. The second transistor has a control end, a first end, and a second end. The control end of the second transistor is electrically connected to the first end of the first transistor, the first end of the second transistor outputs a gate signal, and the second end of the second transistor receives the second timing signal. The capacitor is electrically connected between the control terminal of the second transistor and the first end of the second transistor.

In a preferred embodiment of the invention, the voltage stabilizing control circuit includes a third transistor and a fourth transistor. The third transistor has a control end, a first end, and a second end. The control terminal of the third transistor is electrically connected to the control terminal of the second transistor, and the first terminal of the third transistor receives the first potential. The fourth transistor has a control end, a first end, and a second end. The control end of the fourth transistor receives the first timing signal, the first end of the fourth transistor is electrically connected to the second end of the third transistor and outputs a voltage stabilizing control signal, and the second end of the fourth transistor receives the second end Potential.

In a preferred embodiment of the invention, the voltage stabilizing circuit includes a fifth transistor and a sixth transistor. The fifth transistor has a control end, a first end and a second end, and the control end of the fifth transistor is electrically connected to the first end of the fourth electro-crystal to receive the voltage stabilization control signal, and the first end of the fifth transistor receives First electricity The second end of the fifth transistor is electrically connected to the control end of the second transistor, and the fifth transistor outputs the voltage stabilizing signal to the control end of the second transistor according to the voltage stabilization control signal. The sixth transistor has a control end, a first end and a second end, and the control end of the sixth transistor is electrically connected to the first end of the fourth electro-crystal to receive the voltage stabilization control signal, and the first end of the sixth transistor receives The first potential, the second end of the sixth transistor is electrically connected to the first end of the second transistor, and the sixth transistor outputs the voltage stabilization signal to the first end of the second transistor according to the voltage stabilization control signal.

According to the present invention, since the gate driving circuit is realized by using a circuit structure of six transistors and one capacitor (6T1C), it is possible to generate a plurality of corresponding signals by inputting a plurality of start signals during a period in which one screen is displayed on the display. The gate signal is to one of the scan lines of the display, and the potential of the gate signal output terminal is stabilized by the voltage stabilization control circuit and the voltage stabilization circuit. In addition, in the present invention, the gate signal can be generated only by the second transistor and the gate signal generated by the gate signal can be reset, that is, the gate signal can be used only by the second transistor. The output is charged and discharged, so only a larger size transistor is required, which reduces the circuit area.

100, 200, 300‧‧‧ gate drive circuit

10, 20, 30, 40‧‧‧ transistors

ST‧‧‧ start signal

Q, A‧‧‧ nodes

CK‧‧‧ clock signal

G _[N+1] ‧‧‧The next level of gate signal

G _[N] ‧‧‧ gate signal

CK1‧‧‧ first timing signal

CK2‧‧‧ second timing signal

V _H ‧‧‧first potential

V _L ‧‧‧second potential

P _[N] ‧‧‧ Regulator control signal

Q _[N] ‧‧‧Stabilization signal

201‧‧‧gate signal generation circuit

202‧‧‧Regulator control circuit

203‧‧‧Variable circuit

21‧‧‧First transistor

22‧‧‧Second transistor

23‧‧‧ Third transistor

24‧‧‧ Fourth transistor

25‧‧‧ Fifth transistor

26‧‧‧ sixth transistor

27‧‧‧ Capacitance

21-1, 22-1, 23-1, 24-1, 25-1, 26-1, 27-1‧‧‧ first end

21-2, 22-2, 23-2, 24-2, 25-2, 26-2, 27-2‧‧‧ second end

21-3, 22-3, 23-3, 24-3, 25-3, 26-3‧‧‧ control end

XCK‧‧‧ first timing signal

CK‧‧‧ second timing signal

G _[N] ‧‧‧ gate signal

P _[N] ‧‧‧ Regulator control signal

Q _[N] ‧‧‧Stabilization signal

V _H ‧‧‧first potential

V _L ‧‧‧second potential

The first starting period of T1‧‧

T2‧‧‧First charging period

T3‧‧‧First discharge period

T4‧‧‧ second starting period

T5‧‧‧Second charging period

T6‧‧‧second discharge period

T7‧‧‧ Regulatory period

1 is a circuit diagram of a conventional gate driving circuit; FIG. 2 is a block diagram of a gate driving circuit according to an embodiment of the present invention; FIG. 3 is a circuit diagram of a gate driving circuit according to an embodiment of the present invention; A timing diagram of a gate driving circuit according to an embodiment of the invention; and FIG. 5 is a timing chart of a gate driving circuit according to another embodiment of the present invention.

2 is a block diagram of a gate driving circuit in accordance with an embodiment of the present invention. As shown in FIG. 2, the gate driving circuit 200 includes a gate signal generating circuit 201, a voltage stabilizing control circuit 202, and a voltage stabilizing circuit 203. The gate driving circuit 200 is configured to provide a gate signal G _[N] to a display (not shown), and the display is used to display a plurality of display screens, and the display includes a plurality of scan lines (not shown). The gate signal generating circuit 201 receives the start signal ST, the first timing signal CK1, and the second timing signal CK2, and outputs a gate according to the received start signal ST, the first timing signal CK1, and the second timing signal CK2. The pole signal G _{[N] is} one of the scan lines in the above display. The voltage stabilizing control circuit 202 receives the first potential V _H , the second potential V _L and the first timing signal CK1, and outputs the voltage stabilization control according to the first potential V _H , the second potential V _L and the first timing signal CK1 Signal P _[N] . The voltage stabilizing circuit 203 receives the first potential V _H and the voltage stabilizing control signal P _[N] , and outputs the voltage stabilizing signal Q _[N] to the gate according to the received first potential V _H and the voltage stabilizing control signal P _[N] The pole signal generating circuit 201 is such that the gate signal generating circuit 201 is in a regulated state when the gate signal G _[N] is not output. In addition, during the display of each display screen, the gate signal generating circuit 201 can receive a plurality of start signals ST and correspondingly output a plurality of gate signals G _[N] during each display screen period. _] to one of the scan lines of the above display. The specific circuit diagrams of the gate signal generating circuit 201, the voltage stabilizing control circuit 202, and the voltage stabilizing circuit 203 will be described in detail below.

3 is a circuit diagram of a gate driving circuit according to an embodiment of the present invention. The same reference numerals in Fig. 3 as those in Fig. 2 denote the same elements and signals. As shown in FIG. 3, the gate driving circuit 300 includes a first transistor 21, a second transistor 22, a third transistor 23, a fourth transistor 24, a fifth transistor 25, a sixth transistor 26, and a capacitor 27. . The gate driving circuit 300 includes a gate signal generating circuit 201, a voltage stabilizing control circuit 202, and a voltage stabilizing circuit 203. The gate signal generating circuit 201 includes a first transistor 21, a second transistor 22, and a capacitor 27. The first transistor 21 has a first end 21-1, a second end 21-2, and a control end 21-3. The control terminal 21-3 of the first transistor 21 is configured to receive the first timing signal CK1, and the second terminal 21-2 of the first transistor 21 is configured to receive the start signal ST. The second transistor 22 has a first end 22-1, a second end 22-2, and a control end 22-3. The control terminal 22-3 of the second transistor 22 is electrically connected to the first end 21-1 of the first transistor 21, and the first terminal 22-1 of the second transistor 22 outputs the gate signal G _[N] , the second The second terminal 22-2 of the transistor 22 receives the second timing signal CK2. The capacitor 27 is electrically connected between the control terminal 22-3 of the second transistor 22 and the first terminal 22-1 of the second transistor 22.

As described above, as shown in FIG. 3, the voltage stabilizing control circuit 202 includes a third transistor 23 and a fourth transistor 24. The third transistor 23 has a first end 23-1, a second end 23-2, and a control end 23-3. The control terminal 23-3 of the third transistor 23 is electrically connected to the control terminal 22-3 of the second transistor 22, and the first terminal 23-1 of the third transistor 23 receives the first potential V _H , and the third transistor 23 The control terminal 23-3 is electrically connected to the control terminal 22-3 of the second transistor 22. The fourth transistor 24 has a first end 24-1, a second end 24-2, and a control end 24-3. The control terminal 24-3 of the fourth transistor 24 receives the first timing signal CK1, and the first terminal 24-1 of the fourth transistor 24 is electrically connected to the second terminal 23-2 of the third transistor 23 and outputs a voltage regulation control. The signal P _[N] , the second terminal 24-2 of the fourth transistor 24 receives the second potential V _L .

As described above, as shown in FIG. 3, the voltage stabilizing circuit 203 includes a fifth transistor 25 and a sixth transistor 26. The fifth transistor 25 has a first end 25-1, a second end 25-2, and a control end 25-3. The control terminal 25-3 of the fifth transistor 25 is electrically connected to the first terminal 24-1 of the fourth transistor 24 to receive the voltage stabilization control signal P _[N] , and the first terminal 25-1 of the fifth transistor 25 receives The first potential V _H , the second end 25 - 2 of the fifth transistor 25 is electrically connected to the control terminal 22-3 of the second transistor 22, and the fifth transistor 25 is output stably according to the voltage stabilization control signal P _[N] The voltage signal Q _{[N] is} to the control terminal 22-3 of the second transistor 22. The sixth transistor 26 has a first end 26-1, a second end 26-2, and a control end 26-3. The control terminal 26-3 of the sixth transistor 26 is electrically connected to the first terminal 24-1 of the fourth transistor 24 to receive the voltage stabilization control signal P _[N] , and the first terminal 26-1 of the sixth transistor 26 is received. The first potential V _H , the second end 26 - 2 of the sixth transistor 26 is electrically connected to the first end 22 - 1 of the second transistor 22 , and the sixth transistor 26 is output according to the voltage stabilizing control signal P _[N] The voltage regulator Q _{[N] is applied} to the first terminal 22-1 of the second transistor 22.

In particular, the first timing signal CK1 and the second timing signal CK2 are mutually inverted and the enabling periods of the two do not overlap each other, and preferably, the first timing signal CK1 and the second timing are The duty cycle CK2 of the signal is substantially less than 50%, for example, between 10% and 50%, that is, after the first timing signal CK1 is disabled and a predetermined period of time elapses, the second timing signal CK2 was only enabled. In addition, the gate driving circuit 300 of the present embodiment is implemented by a P-type transistor, but the invention is not limited thereto, and those skilled in the art can also implement the gate of the present invention by using an N-type transistor. Drive circuit 300.

4 is a timing diagram of a gate driving circuit according to an embodiment of the present invention. As shown in FIG. 4, the duty cycles of the first timing signals CK1 and CK2 in this embodiment are less than 50%, and the enabling periods of the two do not overlap each other. However, the present invention is not limited thereto. The sequence signal CK1 and the second timing signal CK2 can also adopt a 50% duty cycle when actually applied, for reasons which will be described later. Referring to FIG. 3 and FIG. 4, when the gate signal generating circuit 201 receives the second start signal ST during the display of one frame (one screen), and correspondingly outputs the secondary gate signal G _[N] , The gate driving circuit 201 sequentially operates in the first start period T1, the first charging period T2, the first discharging period T3, the second starting period T4, the second charging period T5, the second discharging period T6, and the voltage stabilization period. T7. When operating in the first initial period T1, the first transistor 21, the second transistor 22, the third transistor 23, and the fourth transistor 24 are turned on, and the fifth transistor 25 and the sixth transistor 26 are turned off. The potential of the control terminal 22-3 of the second transistor 22 has a first level. Specifically, during the first start period T1, the first timing signal CK1 turns on the first transistor 21 and the fourth transistor 24. The first transistor 21 is turned on and thus transmits the start signal ST to the node A. The potential of the node A is substantially the same as the potential of the control terminal 22-3 of the second transistor 22, and thus can be grounded by the potential of the node A. The second transistor 22 and the third transistor 23 are turned on. Since the third transistor 23 and the fourth transistor 24 are turned on, the voltage regulation control signal P _{[N] is} disabled at this time, and thus the fifth transistor 25 and the sixth transistor 26 are turned off.

When operating in the first charging period T2, the first transistor 21, the fourth transistor 24, the fifth transistor 25, and the sixth transistor 26 are turned off, and the second transistor 22 and the third transistor 23 are turned on. The potential of the control terminal 22-3 of the second transistor 22 is switched to the second level by the coupling of the capacitor 27, and the first terminal 22-1 of the second transistor 22 outputs the gate signal G _{[N ]} . Specifically, during the period of the first charging period T2, since the second transistor 22 is turned on, the potential of the second timing signal CK2 received by the second terminal 22-2 of the second transistor 22 is Passing to the first end 22-1 of the second transistor 22, and then the coupling of the capacitor 27 causes the potential of the node A to be switched from the first level to the second level, thus causing the second transistor The channel of 22 is enlarged to fully charge the potential of the first terminal 22-1 of the second transistor 22 to the second timing signal CK2, and the gate signal G is outputted through the first terminal 22-1 of the second transistor 22. _[N] .

When operating in the first discharge period T3, the first end 22-1 of the second transistor 22 stops outputting the gate signal G _[N] , and the control terminal 22 of the second transistor 22 is coupled by the coupling of 27 capacitors. The potential of -3 returns to the first level. Specifically, during the period of the first discharge period T3, the second timing signal CK2 is disabled so that the first end 22-1 of the second transistor 22 is no longer charged, and during this period, the first The timing signal CK1 is not yet enabled, so the potential of the node A is restored from the second level to the first level by the coupling of the capacitor 27. It should be noted that, since the duty ratios of the first timing signal CK1 and the second timing signal CK2 used in this embodiment are less than 50% and the enabling periods do not overlap each other, the first discharging period T3 can be made during the first discharging period T3. The first end 22-1 of the second transistor 22 is rapidly discharged to stop the output gate signal G _[N] . However, the first timing signal CK1 and the second timing signal CK2 may also have a duty cycle of 50%, but the enabling periods still do not overlap each other.

When operating in the second initial period T4, the first transistor 21, the second transistor 22, the third transistor 33, and the fourth transistor 24 are turned on, and the fifth transistor 25 and the sixth transistor are turned off. The potential of the control terminal 22-3 of the second transistor 22 is maintained at the first level. The first timing signal CK1 turns on the first transistor 21 and the fourth transistor 24 during the second start period T2, as in the first start period T1. The first transistor 21 is turned on and thus transmits the start signal ST to the node A. The potential of the node A is substantially the same as the potential of the control terminal 22-3 of the second transistor 22, and thus can be grounded by the potential of the node A. The second transistor 22 and the third transistor 23 are turned on. Since the third transistor 23 and the fourth transistor 24 are turned on, the voltage regulation control signal P _{[N] is} disabled at this time, and thus the fifth transistor 25 and the sixth transistor 26 are turned off.

When operating in the second charging period T5, the first transistor 21, the fourth transistor 24, the fifth transistor 25, and the sixth transistor 26 are turned off, and the second transistor 22 and the third transistor 23 are turned on. The potential of the control terminal 22-3 of the second transistor 22 is switched to the second level by the coupling of the capacitor 27, and the first terminal 22-1 of the second transistor 22 is again outputting the gate signal G _{[ N]} . Same as the first charging period T2, during the period of the second charging period T5, since the second transistor 22 is turned on, the second timing signal CK2 received by the second terminal 22-2 of the second transistor 22 The potential is transferred to the first end 22-1 of the second transistor 22, and then the potential of the node A is switched from the first level to the second level by the coupling of the capacitor 27, thus The channel of the second transistor 22 is enlarged to fully charge the potential of the first terminal 22-1 of the second transistor 22 to the second timing signal CK2, and by the first end 22-1 of the second transistor 22. The gate signal G _{[N] is} output again.

When operating in the second discharge period T6, the first terminal 22-1 of the second transistor 22 stops outputting the gate signal G _[N] , and the control terminal 22 of the second transistor 22 is coupled by the coupling of the capacitor 27. The potential of -3 returns to the first level. Same as the first discharge period T3, during the period of operation of the second discharge period T6, the second timing signal CK2 is disabled such that the first end 22-1 of the second transistor 22 is no longer charged, and during this period The first timing signal CK1 is not yet enabled, so the potential of the node A is restored from the second level to the first level by the coupling of the capacitor 27. It should be noted that, since the duty ratios of the first timing signal CK1 and the second timing signal CK2 used in this embodiment are less than 50% and the enabling periods do not overlap each other, the second discharging period T6 can be made during the second discharging period T6. The first end 22-1 of the second transistor 22 is rapidly discharged to stop the output gate signal G _[N] . However, the first timing signal CK1 and the second timing signal CK2 may also have a duty cycle of 50%, but the enabling periods still do not overlap each other, but in this case, the size of the second transistor 22 may have to be Increased to enable faster discharge.

When operating in the voltage stabilization period T7, the first transistor 21, the fourth transistor 24, the fifth transistor 25, and the sixth transistor 26 are turned on, and the second transistor 22 and the third transistor 23 are turned off. The second transistor 22 does not output the gate signal G _[N] , and the control terminal 22-3 of the second transistor 22 and the first terminal 22-1 receive the voltage stabilization signal Q _[N] and are in a regulated state. Specifically, during the period of the voltage stabilization period T7, the first timing signal CK1 turns on the first transistor 21 and the fourth transistor 24, and during this period, the start signal ST is disabled, so the node The potential of A cannot turn on the second transistor 22 and the third transistor 23, so that the first end 24-1 of the fourth transistor 24 is received according to the second end 24-2 of the fourth transistor 24. The second potential V _L outputs a voltage stabilizing control signal P[N] and turns on the fifth transistor 25 and the sixth transistor 26. When the fifth transistor 25 and the sixth transistor 26 are turned on, the first transistor 26-1 of the fifth transistor 25 and the sixth transistor 26 respectively output a voltage stabilization signal according to the received first potential V _H . Q _[N] to the control terminal 22-3 of the second transistor 22 and the first terminal 22-1 of the second transistor 22 to ensure the control terminal 22-3 of the second transistor 22 and the first terminal 22-1 It is not in the floating state, so even if the first timing signal CK1 and the second timing signal CK2 are continuously changed in potential, the potential of the first end 22-1 of the transistor 22 is not affected, and the second is made. The first end 22-1 of the transistor 22 is in a regulated state.

In the above embodiment, the gate driving circuit 300 receives two start signals ST and correspondingly outputs two gate signals G _[N] to one of the gates of the display while the display (not shown) displays one screen. The description of the line, however, it is also known to those skilled in the art that when the gate driving circuit 300 receives only one start signal ST during the display of one picture, the operation sequence of the gate driving circuit 300 is as shown in FIG. The timing will be the first start period T1, the first charging period T2, and the first discharge period T3 followed by the voltage stabilization period T7. Of course, the second start period T4 may be used as the first operation period, followed by the second charging period T5, the second discharge period T6, and the voltage stabilization period T7, and the methods of operation are the same as described above, only in the The number of times the start signal ST received by the gate driving circuit 300 is different during the period in which the display displays one screen.

FIG. 5 is a timing diagram of a gate driving circuit according to another embodiment of the present invention. 5 is different from FIG. 4 only in that the gate driving circuit 300 receives the second start signal ST at different time points and correspondingly outputs the gate signal G _[N] , and outputs two scanning signals G _[ The time interval of _N] can be adjusted by the time interval of the two received start signals ST, and the rest of the operation methods are the same as those of FIG. 4, and therefore will not be described again. Although in the present invention, only the embodiment in which the gate driving circuit 300 receives one start signal and two start signals ST during the display of one picture is shown, the present invention is not limited thereto, and the received start The number and spacing of the signals ST can be adjusted by those skilled in the art as needed, and are all within the scope of protection of the present invention.

In summary, the present invention implements a gate driving circuit by using a circuit structure of 6T1C, and operates with two timing signals whose duty cycles are less than 50% and do not overlap each other during the enabling period, thereby making the present The gate driving circuit of the invention can generate a corresponding gate signal to one of the gate lines of the display according to a plurality of initial signals during a period in which the display displays a picture, and only by a larger-sized transistor The output of the gate signal can be quickly charged and discharged, and the time interval of the outputted plurality of scan signals can be adjusted by the time interval of the received multiple start signals. The 4T1C gate drive circuit is more widely used at the application level.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

200‧‧‧ gate drive circuit

201‧‧‧gate signal generation circuit

202‧‧‧Regulator control circuit

203‧‧‧Variable circuit

ST‧‧‧ start signal

XCK‧‧‧ first timing signal

CK‧‧‧ second timing signal

G _[N] ‧‧‧ gate signal

P _[N] ‧‧‧ Regulator control signal

Q _[N] ‧‧‧Stabilization signal

V _H ‧‧‧first potential

V _L ‧‧‧second potential

Claims (10)

A gate driving circuit for providing a gate signal to a display for displaying a plurality of display screens, the display comprising a plurality of scan lines, the gate drive circuit comprising: a gate signal generating circuit, receiving a start signal, a first timing signal, and a second timing signal, and outputting the gate signal to the scan lines according to the start signal, the first timing signal, and the second timing signal One of the voltage regulation control circuits receives a first potential, a second potential, and the first timing signal, and outputs a voltage regulator according to the first potential, the second potential, and the first timing signal a control signal; and a voltage stabilizing circuit receiving the first potential and the voltage stabilizing control signal, and outputting a voltage stabilizing signal to the gate signal generating circuit according to the first potential and the voltage stabilizing control signal, so that the The gate signal generating circuit is in a regulated state when the gate signal is not output; wherein the gate signal generating circuit receives the plurality of times during the display of each display screen Starting signal, and outputs the plurality of gate signals corresponding to the screen in each period to display from among the plurality of scanning lines wherein a. The gate driving circuit of claim 1, wherein the gate signal generating circuit comprises: a first transistor having a control end, a first end and a second end, the first electric The control end of the crystal is configured to receive the first timing signal, and the second end of the first transistor is configured to receive the start signal; a second transistor having a control end, a first end and a second end, the control end of the second transistor being electrically connected to the first end of the first transistor, the second transistor The first end outputs the gate signal, the second end of the second transistor receives the second timing signal, and a capacitor electrically connected to the control end of the second transistor and the second Between the first ends of the crystal. The gate driving circuit of claim 2, wherein the voltage stabilizing control circuit comprises: a third transistor having a control terminal, a first terminal and a second terminal, the third transistor The control terminal is electrically connected to the control end of the second transistor, the first end of the third transistor receives the first potential; and a fourth transistor has a control end, a first end, and a second end, the control end of the fourth transistor receives the first timing signal, the first end of the fourth transistor is electrically connected to the second end of the third transistor and outputs the voltage stabilization control The signal, the second end of the fourth transistor receives the second potential. The gate driving circuit of claim 3, wherein the voltage stabilizing circuit comprises: a fifth transistor having a control end, a first end and a second end, the fifth transistor The control terminal is electrically connected to the first end of the fourth electric crystal to receive the voltage stabilizing control signal, the first end of the fifth transistor receives the first potential, and the second end of the fifth transistor Electrically connected to the control end of the second transistor, the fifth transistor outputs the voltage stabilizing signal to the control end of the second transistor according to the voltage stabilizing control signal; and a sixth transistor having a a control end, a first end, and a second end, The control terminal of the sixth transistor is electrically connected to the first end of the fourth transistor to receive the voltage stabilization control signal, and the first terminal of the sixth transistor receives the first potential, the sixth The second end of the crystal is electrically connected to the first end of the second transistor, and the sixth transistor outputs the voltage stabilizing signal to the first end of the second transistor according to the voltage stabilizing control signal. The gate driving circuit of claim 4, wherein when the gate signal generating circuit receives the start signal once during a display of the frame, and correspondingly outputs the gate signal, The gate driving circuit sequentially operates in a first initial period, a first charging period, a first discharging period, and a voltage stabilizing period, and when operating in the first starting period, the first transistor, the second The transistor, the third transistor, and the fourth transistor are turned on, and the fifth transistor and the sixth transistor are turned off, and the potential of the control terminal of the second transistor has a first level. When operating in the first charging period, the first transistor, the fourth transistor, the fifth transistor, and the sixth transistor are turned off, and the second transistor and the third transistor are turned on. When the potential of the control terminal of the second transistor is converted to a second level by the coupling of the capacitor, and the first end of the second transistor outputs the gate signal, when operating in the first a second period of time during a discharge period The first end of the body stops outputting the gate signal, and the potential of the control terminal of the second transistor is returned to the first level by the coupling of the capacitor, when operating in the voltage regulation period, The first transistor, the fourth transistor, the fifth transistor, and the sixth transistor are turned on, and the second transistor and the third transistor are turned off, and the second transistor does not output the gate a pole signal, and the control terminal of the second transistor and the first terminal receive the voltage stabilization signal to be in the regulated state. The gate driving circuit of claim 5, wherein the gate signal generating circuit receives the second start signal during a period in which the display displays one frame, and outputs the gate signal correspondingly twice. The gate driving circuit operates in a second initial period, a second charging period, and a second discharging period after the first discharging period and before the voltage regulation period, when operating in the In the second initial period, the first transistor, the second transistor, the third transistor, and the fourth transistor are turned on, and the fifth transistor and the sixth transistor are turned off. The potential of the control terminal of the two transistors is maintained at the first level, and when operating in the second charging period, the first transistor, the fourth transistor, the fifth transistor, and the sixth transistor are cut off The second transistor and the third transistor are turned on, and the potential of the control terminal of the second transistor is converted to the second level by the coupling of the capacitor, and the second transistor is turned on. The first end outputs the gate again a signal, when operating in the second discharge period, the first end of the second transistor stops outputting the gate signal, and the potential of the control terminal of the second transistor is restored by the coupling of the capacitor The first level. The gate driving circuit of claim 6, wherein the first timing signal and the second timing signal have a duty cycle of less than 50%, and the first timing signal and the second timing signal are Work cycles do not overlap each other. The gate driving circuit of claim 7, wherein when the first timing signal and the second timing signal are not simultaneously turned on, when the first timing signal is turned off and a predetermined time passes After that, the second timing signal is turned on. The gate driving circuit of claim 7, wherein the first timing signal and the second timing signal have a duty cycle of between 10% and 50%. The gate driving circuit of claim 1, wherein the first timing signal and the second timing signal have a duty cycle of 50%.