TWI563504B - Delay line circuit, delay locked loop and tester system including the same - Google Patents

Delay line circuit, delay locked loop and tester system including the same

Info

Publication number
TWI563504B
TWI563504B TW101146105A TW101146105A TWI563504B TW I563504 B TWI563504 B TW I563504B TW 101146105 A TW101146105 A TW 101146105A TW 101146105 A TW101146105 A TW 101146105A TW I563504 B TWI563504 B TW I563504B
Authority
TW
Taiwan
Prior art keywords
delay
same
system including
locked loop
line circuit
Prior art date
Application number
TW101146105A
Other languages
English (en)
Other versions
TW201411621A (zh
Inventor
Wen Chang Cheng
Original Assignee
Nanya Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanya Technology Corp filed Critical Nanya Technology Corp
Publication of TW201411621A publication Critical patent/TW201411621A/zh
Application granted granted Critical
Publication of TWI563504B publication Critical patent/TWI563504B/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
TW101146105A 2012-09-07 2012-12-07 Delay line circuit, delay locked loop and tester system including the same TWI563504B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/606,019 US8593197B1 (en) 2012-09-07 2012-09-07 Delay line circuit, delay locked loop and tester system including the same

Publications (2)

Publication Number Publication Date
TW201411621A TW201411621A (zh) 2014-03-16
TWI563504B true TWI563504B (en) 2016-12-21

Family

ID=49596641

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101146105A TWI563504B (en) 2012-09-07 2012-12-07 Delay line circuit, delay locked loop and tester system including the same

Country Status (3)

Country Link
US (1) US8593197B1 (zh)
CN (1) CN103684435B (zh)
TW (1) TWI563504B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI732558B (zh) * 2020-05-18 2021-07-01 華邦電子股份有限公司 延遲鎖相迴路裝置及其操作方法
TWI769328B (zh) * 2017-10-19 2022-07-01 韓商愛思開海力士有限公司 半導體裝置及使用其的半導體系統

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US9939883B2 (en) 2012-12-27 2018-04-10 Nvidia Corporation Supply-voltage control for device power management
US9602083B2 (en) 2013-07-03 2017-03-21 Nvidia Corporation Clock generation circuit that tracks critical path across process, voltage and temperature variation
US9766649B2 (en) 2013-07-22 2017-09-19 Nvidia Corporation Closed loop dynamic voltage and frequency scaling
US10103719B2 (en) 2013-07-22 2018-10-16 Nvidia Corporation Integrated voltage regulator with in-built process, temperature and aging compensation
US10466763B2 (en) * 2013-12-02 2019-11-05 Nvidia Corporation Dynamic voltage-frequency scaling to limit power transients
CN103986443B (zh) 2014-05-29 2017-08-25 上海兆芯集成电路有限公司 延迟线电路及半导体集成电路
KR20160046259A (ko) * 2014-10-20 2016-04-28 에스케이하이닉스 주식회사 테스트 경로 보상 회로 및 테스트 경로 보상 시스템
US10254783B2 (en) * 2017-06-28 2019-04-09 Western Digital Technologies, Inc. External clock based clock generator
CN111030679B (zh) * 2018-10-09 2023-03-07 华邦电子股份有限公司 延迟锁相回路电路及其单位粗延迟选择方法
CN111510137A (zh) * 2020-06-04 2020-08-07 深圳比特微电子科技有限公司 时钟电路、计算芯片、算力板和数字货币挖矿机
US11495534B2 (en) * 2021-04-12 2022-11-08 Nanya Technology Corporation Semiconductor device with test pad and method for fabricating the same

Citations (3)

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US6995590B1 (en) * 2003-09-22 2006-02-07 Altera Corporation Hybrid phase/delay locked loop circuits and methods
US20060164139A1 (en) * 2004-01-16 2006-07-27 Yan Chong Loop circuitry with low-pass noise filter
US20100327982A1 (en) * 2009-06-30 2010-12-30 Sun Microsystems, Inc. Inverting difference oscillator

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US6958634B2 (en) * 2003-12-24 2005-10-25 Intel Corporation Programmable direct interpolating delay locked loop
US7629856B2 (en) * 2006-10-27 2009-12-08 Infineon Technologies Ag Delay stage, ring oscillator, PLL-circuit and method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6995590B1 (en) * 2003-09-22 2006-02-07 Altera Corporation Hybrid phase/delay locked loop circuits and methods
US20060164139A1 (en) * 2004-01-16 2006-07-27 Yan Chong Loop circuitry with low-pass noise filter
US20100327982A1 (en) * 2009-06-30 2010-12-30 Sun Microsystems, Inc. Inverting difference oscillator

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Abadian, A.; Lotfizad, M.; Majd, N.E.; Ghoushchi, M.B.G.; Mirzaie, Hossein, "A new low-power and low-complexity all digital PLL (ADPLL) in 180nm and 32nm," Electronics, Circuits, and Systems (ICECS), 2010年12月, pp.305-310 *
Gierkink, S.L.J., "Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump," on IEEE Journal of Solid-State Circuits, vol.43, no.12, 2008年12月, pp.2967-2976 *
Young-Shig Choi; Hyuk-Hwan Choi; Tae-Ha Kwon, "A fast locking DLL clock synthesizer," Science and Technology, 2005年6月, pp.830-833 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI769328B (zh) * 2017-10-19 2022-07-01 韓商愛思開海力士有限公司 半導體裝置及使用其的半導體系統
TWI732558B (zh) * 2020-05-18 2021-07-01 華邦電子股份有限公司 延遲鎖相迴路裝置及其操作方法

Also Published As

Publication number Publication date
TW201411621A (zh) 2014-03-16
CN103684435A (zh) 2014-03-26
US8593197B1 (en) 2013-11-26
CN103684435B (zh) 2019-03-05

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