TWI556411B - Manufacturing method and structure of non-volatile memory - Google Patents

Description

Non-volatile memory structure and manufacturing method thereof

The present invention relates to a non-volatile memory structure and a method of fabricating the same, and more particularly to a non-volatile memory structure and a method of fabricating the same in a semiconductor process.

Non-volatile memory is a multiple-times-programmable (MTP) that can retain its stored data memory components when the power is turned off. ) Widely used in today's digital products.

The memory unit in the multi-programmable non-volatile memory that can write data multiple times is mainly composed of a floating gate and a control gate, wherein the floating gate stores the charge written by the data. The non-volatile memory cells that can be written multiple times have different component structures depending on the process. The common process classifications include three-layer polysilicon process technology, two-layer polysilicon process technology, and single-layer polysilicon process technology, in which single-layer polysilicon is used. The process technology has the advantage of simplifying the steps, but the completed single polycrystalline non-volatile memory has insufficient retention ability for charge stored in the floating gate, for example, baking at a high temperature of 250 ° C. In the high temperature deterioration experiment, the charge in the floating gate will be seriously lost, and the current between the source and the drain will be greatly reduced to the state of erroneous interpretation. Therefore, how to improve the data retention capability of a single polycrystalline non-volatile memory is the main purpose of the development of this case.

In order to improve the data retention capability of a single polycrystalline non-volatile memory, a non-volatile memory manufacturing method has been developed in the present invention, which comprises the steps of: providing a substrate on which a polysilicon gate structure has been formed; Forming a contact etch stop layer over the polysilicon gate structure, the contact etch stop layer comprising at least a tantalum nitride layer and a first hafnium oxide layer, wherein the tantalum nitride layer is located below the first hafnium oxide layer; An inner dielectric layer is formed over the contact etch stop layer, wherein the first ruthenium oxide layer is adjacent to the inner dielectric layer and has a density greater than a density of the inner dielectric layer.

According to the above concept, the non-volatile memory manufacturing method of the present invention, wherein the method of forming the contact etch stop layer comprises the steps of: forming a second ruthenium oxide layer over the polysilicon gate structure; above the second ruthenium oxide layer Forming the tantalum nitride layer; and forming the first tantalum oxide layer over the tantalum nitride layer.

According to the above concept, the non-volatile memory manufacturing method of the present invention, wherein the method of forming the first ruthenium oxide layer in the contact etch stop layer comprises the steps of: plasma-reinforced with tetraethyl phthalate as a raw material; The first ruthenium oxide layer is formed by chemical vapor deposition, and the first ruthenium oxide layer has a thickness ranging from about 300 angstroms to 2000 angstroms.

According to the above concept, the non-volatile memory manufacturing method of the present invention, wherein the method of forming the inner dielectric layer comprises the step of depositing the inner dielectric layer by atmospheric pressure chemical vapor deposition.

Another aspect of the present invention is a non-volatile memory structure comprising: a substrate; a polysilicon gate structure formed over the substrate; and a contact etch stop layer formed over the polysilicon gate structure, the contact etch stop layer being at least And comprising a tantalum nitride layer and a first tantalum oxide layer, wherein the tantalum nitride layer is located below the first tantalum oxide layer; and an inner dielectric layer is formed on the surface of the first tantalum oxide layer, wherein the first The density of the ruthenium oxide layer is greater than the density of the inner dielectric layer.

According to the above concept, the non-volatile memory structure of the present invention, wherein the polysilicon gate structure comprises at least a single polycrystalline germanium conductor, and the single polycrystalline germanium conductor is a floating gate of the non-volatile memory.

According to the above concept, the non-volatile memory structure of the present invention, wherein the contact etch stop layer further comprises a second ruthenium oxide layer formed between the polysilicon gate structure and the tantalum nitride layer.

According to the above concept, the non-volatile memory structure of the present invention, wherein the first ruthenium oxide layer has a compressive stress characteristic, and has a thickness ranging from about 300 angstroms to 2000 angstroms.

According to the above concept, the non-volatile memory structure of the present invention, wherein the material of the inner dielectric layer is yttrium oxide.

Please refer to FIG. 1A , which is a schematic structural view of a single polycrystalline non-volatile memory as proposed in the present invention. The structure is mainly divided into two parts. The first part is the floating gate area 11 and the second part. It is a control gate region 12 in which a single polysilicon conductor 13 passes through two regions, and the single polysilicon conductor 13 has a source contact electrode 141 and a drain contact electrode 142 on both sides of the first portion 131 of the floating gate region 11, respectively. The single polysilicon conductor 13 passes through a side of the second portion 132 of the control gate region 12 to have a control electrode 143.

Referring again to FIG. 1B, which is a schematic diagram showing a combined view of the cross-section taken along the broken line A--B and the broken line A--C in FIG. 1A, wherein the floating gate region 11 and the control gate region 12 are below the single polycrystalline germanium conductor 13. A P-type well region 151 is formed, and an N-type well region 152 is formed below the second portion 132 of the control gate region 12, above the P-type well region 151 in the control gate region 12. The N-type well region 152 is used to play the role of a control gate. Selecting whether a carrier such as an electron or a hole is injected into the single polysilicon conductor 13 by a channel hot carrier effect is used to change the threshold voltage of the floating gate, thereby determining the memory unit. When the current measured by the source contact electrode 141 and the drain contact electrode 142 is in the on or off state, it can be judged that the data stored in the memory unit is "1" or "0".

In order to ensure the charge retention capability of the floating gate completed by the single polysilicon conductor 13, a single polycrystalline germanium conductor 13 is surrounded by a film composed of various dielectric materials, for example, a dielectric is formed on the lower surface of the single polycrystalline germanium conductor 13. In the layer 1310, the sidewalls of the single polycrystalline germanium conductor 13 are formed with a spacer 1311, and the upper surface of the single polycrystalline germanium conductor 13 is formed with a contact etching stop layer (CESL) 19 and an inner surface in addition to the metal germanide 1312. An Inter-Layer Dielectric (ILD) 16 is used to provide a subsequent contact hole etching process, and can prevent the charge remaining in the floating gate 131 from escaping.

In the present embodiment, the contact etch stop layer (CESL) 19 is mainly formed by a multilayer structure, and is formed over the surface of the single polysilicon conductor 13 mainly in the form of a conformal film. For example, as shown in the figure, a contact etch stop layer (CESL) 19 is formed by a three-layer structure of a hafnium oxide layer 191, a tantalum nitride layer 192, and another hafnium oxide layer 193. The thickness of the yttrium oxide layer 191 ranges from about 100 angstroms to 500 angstroms, and can be deposited by using Tetraethyl orthosilicate (Si(OC2H5)4, referred to as TEOS) as a raw material. The yttrium oxide layer 193 is formed by plasma enhanced chemical vapor deposition using tetraethyl phthalate (TEOS) as a raw material. The yttrium oxide layer 193 has a thickness ranging from about 300 angstroms to about 2,000 angstroms. The yttria layer 193 may have a compressive stress characteristic, and its density is higher than that of the inner dielectric layer 16 which is subsequently completed by atmospheric pressure chemical vapor deposition (APCVD). Therefore, the problem of poor data retention capability of the previous single polycrystalline germanium conductor 13 can be effectively improved, for example, after 48 hours of high-temperature baking at 250 ° C, the source contact electrode 141 and the drain of this example are used. The current measured between the contact electrodes 142 will be reduced from 33.3 microamperes to only 33 microamperes, whereby the enhancement achieved by this embodiment is apparent.

In addition, if the contact etch stop layer (CESL) 19 is formed only by the two-layer structure of the tantalum nitride layer 192 and the tantalum oxide layer 193 (that is, the yttrium oxide layer 191 in FIG. 1B is omitted), the charge retention can be improved. Poor question. The yttrium oxide layer 193 is also formed by plasma-enhanced chemical vapor deposition using tetraethyl phthalate (TEOS) as a raw material. The yttrium oxide layer 193 has a thickness ranging from about 300 angstroms to about 2,000 angstroms. This can also effectively improve the problem of poor data retention capability of the previous single polycrystalline germanium conductor 13, for example, the source contact electrode 141 and the germanium of this example after 48 hours of high temperature baking at 250 °C. The current measured between the pole contact electrodes 142 will be reduced from only 29.3 microamperes to only 24.2 microamperes, whereby the enhancement achieved by this embodiment is apparent.

However, if the contact etch stop layer (CESL) is formed only by the single layer structure of the tantalum nitride layer 192, the experimentally measured data shows that after 48 hours of high temperature baking at 250 ° C, this example The current measured between the source contact electrode 141 and the drain contact electrode 142 can be reduced from 27.6 microamperes to 0.4 microamperes, and it is apparent that the single layer structure of the tantalum nitride layer 192 will not meet the demand.

Further, if the contact etch stop layer (CESL) is formed by the two-layer structure of the yttrium oxide layer 191 and the tantalum nitride layer 192, the experimentally measured data shows that the temperature is baked at 250 ° C for 48 hours. After (baking), the current measured between the source contact electrode 141 and the drain contact electrode 142 of this example can be reduced from 28.16 microamperes to 0.88 microamperes, whereby the hafnium oxide layer 191 and nitride are also apparent. The two-layer structure of the 矽 layer 192 also fails to meet the demand.

When the contact etch stop layer (CESL) 19 is completed by a multilayer structure, the contact hole etching process for completing the contact holes of the subsequent source contact electrode 141, the drain contact electrode 142 and the control electrode 143 can be performed by using different etching recipes. Multiple etchings are performed.

In summary, after the technology of the present invention is improved, the problem of the conventional means can be effectively improved. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

11. . . Floating gate area

12. . . Control gate area

13. . . Single polycrystalline germanium conductor

131. . . first part

141. . . Source contact electrode

142. . . Bungee contact electrode

132. . . Second part

143. . . Control electrode

151. . . P-well area

152. . . N-well area

1310. . . Dielectric layer

1311. . . Clearance wall

1312. . . Metal telluride

19. . . Contact etch stop layer

16. . . Inner dielectric layer

191. . . Cerium oxide layer

192. . . Tantalum nitride layer

193. . . Cerium oxide layer

FIG. 1A is a schematic top view showing the structure of a single polycrystalline non-volatile memory as proposed in the present invention.

FIG. 1B is a schematic cross-sectional view showing the structure of a single polycrystalline non-volatile memory as proposed in the present invention.

13. . . Single polycrystalline germanium conductor

131. . . first part

141. . . Source contact electrode

142. . . Bungee contact electrode

132. . . Second part

143. . . Control electrode

151. . . P-well area

152. . . N-well area

1310. . . Dielectric layer

1311. . . Clearance wall

1312. . . Metal telluride

19. . . Contact etch stop layer

16. . . Inner dielectric layer

191. . . Cerium oxide layer

192. . . Tantalum nitride layer

193. . . Cerium oxide layer

Claims (12)

A non-volatile memory manufacturing method comprising the steps of: providing a substrate having a polysilicon gate structure formed thereon; forming a contact etch stop layer over the substrate and the polysilicon gate structure, the contact etch stop layer being at least a tantalum nitride layer and a first tantalum oxide layer, wherein the tantalum nitride layer is under the first tantalum oxide layer; and an inner dielectric layer is formed over the contact etch stop layer, wherein the first layer The hafnium oxide layer is adjacent to the inner dielectric layer and has a density greater than the density of the inner dielectric layer. The non-volatile memory manufacturing method according to claim 1, wherein the polysilicon gate structure comprises at least a single polycrystalline germanium conductor. The method for fabricating a non-volatile memory according to claim 2, wherein the method for forming the polysilicon gate structure comprises the steps of: forming a dielectric layer over the substrate; forming the single polysilicon over the dielectric layer a conductor; a spacer formed on a sidewall of the single polysilicon conductor; and a metal halide formed on a surface of the single polysilicon conductor. The non-volatile memory manufacturing method of claim 1, wherein the method of forming the contact etch stop layer comprises the steps of: forming a second ruthenium oxide layer over the polysilicon gate structure; Forming the tantalum nitride layer over the tantalum layer; and forming the first tantalum oxide layer over the tantalum nitride layer. The non-volatile memory manufacturing method according to claim 1, wherein the method for forming the first ruthenium oxide layer in the contact etch stop layer comprises the steps of: using a tetraethyl phthalate as a raw material for plasma treatment The first ruthenium oxide layer is formed by reinforced chemical vapor deposition, and the first ruthenium oxide layer has a thickness ranging from about 300 angstroms to about 2,000 angstroms. The non-volatile memory manufacturing method according to claim 1, wherein the method of forming the inner dielectric layer comprises the step of depositing the inner dielectric layer by atmospheric pressure chemical vapor deposition. A non-volatile memory structure comprising: a substrate; a polysilicon gate structure formed over the substrate; a contact etch stop layer formed over the polysilicon gate structure, the contact etch stop layer comprising at least a nitride a germanium layer and a first tantalum oxide layer, wherein the tantalum nitride layer is located under the first tantalum oxide layer; and an inner dielectric layer is formed on the surface of the first tantalum oxide layer, wherein the first oxide The density of the tantalum layer is greater than the density of the inner dielectric layer. The non-volatile memory structure of claim 7, wherein the polysilicon gate structure comprises at least a single polycrystalline germanium conductor, and the single polycrystalline germanium conductor is a floating gate of the non-volatile memory. The non-volatile memory structure of claim 8, wherein the polysilicon gate structure further comprises: a dielectric layer formed over the substrate and between the lower surface of the single polysilicon conductor; a spacer, Formed on a sidewall of the single polycrystalline germanium conductor; and a metal halide formed on the upper surface of the single polycrystalline germanium conductor. The non-volatile memory structure of claim 7, wherein the contact etch stop layer further comprises a second ruthenium oxide layer formed between the polysilicon gate structure and the tantalum nitride layer. The non-volatile memory structure of claim 7, wherein the first ruthenium oxide layer has a compressive stress characteristic and a thickness ranging from about 300 angstroms to about 2,000 angstroms. The non-volatile memory structure of claim 7, wherein the material of the inner dielectric layer is cerium oxide.