JP2019009339A - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

To suppress reduction of a ferroelectric film in a semiconductor device including the ferroelectric film.SOLUTION: A semiconductor device includes: a memory cell including a ferroelectric capacitor with a ferroelectric film; a first insulation film covering the ferroelectric capacitor; a second insulation film covering the first insulation film and having a smaller film stress than the first insulation film; and an annular structure embedded in the first and second insulation films and surrounding an outer periphery of the memory cell.SELECTED DRAWING: Figure 3

Description

  The disclosed technology relates to a semiconductor device and a method for manufacturing the semiconductor device.

  As a technique for reducing stress on metal wiring of a semiconductor device, a metal wiring is formed on the surface of an interlayer insulating film, a TEOS oxide film having a high stress value, an SOG film, and a TEOS oxide film having a low stress value are stacked, and then contact holes are formed. Techniques for forming are known.

  In addition, a ferroelectric memory including an interlayer insulating film, an insulating hydrogen barrier film having hydrogen resistance, and a capacitor element including a lower electrode, a capacitor insulating film, and an upper electrode is known.

Japanese Patent Laid-Open No. 10-163317 JP 2010-93064 A

  Ferroelectric materials such as PZT (lead zirconate titanate) that make up a ferroelectric memory are oxides, so they are easily reduced when exposed to a reducing atmosphere, resulting in deterioration of ferroelectricity, and memory performance. To do. Degradation of memory performance due to the reduction of the ferroelectric becomes more serious as the ferroelectric film is thinner. Accordingly, in miniaturization of a ferroelectric memory accompanied by thinning of the ferroelectric film, it is important how to protect the ferroelectric film from a reducing atmosphere. In the manufacturing process of the ferroelectric memory, as an element for reducing the ferroelectric film, penetration of hydrogen and moisture into the ferroelectric capacitor can be mentioned. Hydrogen and moisture are generated during the formation of the interlayer insulating film covering the ferroelectric capacitor, and reduce the ferroelectric film during and after the formation of the interlayer insulating film. Depending on the specifications of the ferroelectric memory, a plurality of interlayer insulating films may be stacked, and hydrogen and moisture remaining inside each of the plurality of interlayer insulating films diffuse between the plurality of interlayer insulating films. Can do.

  In the ferroelectric memory, in order to protect the ferroelectric film from hydrogen and moisture, a structure in which the outer periphery of the memory cell formation region is surrounded by a protective wall called a moisture-proof ring may be adopted. The present inventor has discovered that cracks occur in the interlayer insulating film adjacent to the moisture-proof ring depending on the arrangement of the moisture-proof ring. When a moisture-proof ring is provided in the immediate vicinity of the ferroelectric memory formation area, if a crack occurs in the interlayer insulating film adjacent to the moisture-proof ring, hydrogen and moisture in the interlayer insulating film easily reach the ferroelectric capacitor. The ferroelectric film is easily reduced.

  When cracks are not generated in the interlayer insulating film, hydrogen and moisture diffuse between the lattices in the interlayer insulating film, so the diffusion rate of hydrogen and moisture is suppressed. The diffusion rate becomes higher. Therefore, as the crack generation range in the interlayer insulating film is expanded, the ferroelectric film is easily reduced, and the memory performance is significantly deteriorated.

  An object of the disclosed technology is to suppress reduction of a ferroelectric film in a semiconductor device including the ferroelectric film.

  A semiconductor device according to the disclosed technique includes a memory cell including a ferroelectric capacitor including a ferroelectric film, a first insulating film that covers the ferroelectric capacitor, the first insulating film, and the first insulating film. And a second insulating film having a film stress smaller than that of the first insulating film. The semiconductor device further includes an annular structure embedded in the first insulating film and the second insulating film and surrounding the outer periphery of the memory cell.

  The disclosed technique has an effect of suppressing reduction of the ferroelectric film in a semiconductor device including the ferroelectric film.

It is a top view of the conductor apparatus which concerns on embodiment of the technique of an indication. 3 is an equivalent circuit diagram of a memory cell according to an embodiment of the disclosed technology. FIG. It is sectional drawing which showed typically the cross-section of the semiconductor device which concerns on embodiment of the technique of an indication. It is a figure which shows the method of estimating the film | membrane stress of the interlayer insulation film which concerns on embodiment of the technique of an indication. It is a figure which shows the method of estimating the film | membrane stress of the interlayer insulation film which concerns on embodiment of the technique of an indication. It is a figure which shows the method of estimating the film | membrane stress of the interlayer insulation film which concerns on embodiment of the technique of an indication. It is a figure which shows the manufacturing method of the semiconductor device which concerns on embodiment of the technique of an indication. It is a figure which shows the manufacturing method of the semiconductor device which concerns on embodiment of the technique of an indication. It is a figure which shows the manufacturing method of the semiconductor device which concerns on embodiment of the technique of an indication. It is a figure which shows the manufacturing method of the semiconductor device which concerns on embodiment of the technique of an indication. It is a figure which shows the manufacturing method of the semiconductor device which concerns on embodiment of the technique of an indication. It is a figure which shows the manufacturing method of the semiconductor device which concerns on embodiment of the technique of an indication. It is a figure which shows the manufacturing method of the semiconductor device which concerns on embodiment of the technique of an indication. It is a figure which shows the manufacturing method of the semiconductor device which concerns on embodiment of the technique of an indication. It is a figure which shows the manufacturing method of the semiconductor device which concerns on embodiment of the technique of an indication. It is a partial top view of the semiconductor device which shows the generation | occurrence | production site | part of a crack. It is a fragmentary sectional view of the semiconductor device which shows the generation part of a crack. It is sectional drawing which shows the generation | occurrence | production mechanism of a crack. It is sectional drawing which shows the generation | occurrence | production mechanism of a crack. It is a graph which shows the relationship between the polarization amount in a ferroelectric capacitor, and its dispersion | variation. It is a graph which shows the relationship between the leakage current in a ferroelectric capacitor, and its dispersion | variation.

  Hereinafter, an example of an embodiment of the disclosed technology will be described with reference to the drawings. In the drawings, the same or equivalent components and parts are denoted by the same reference numerals.

  FIG. 1 is a plan view of a semiconductor device 100 including a ferroelectric memory according to an embodiment of the disclosed technique. The semiconductor device 100 includes a plurality of memory cell arrays 110 formed on the semiconductor substrate 11 and an annular moisture-proof ring 120 provided corresponding to each of the memory cell arrays 110 and surrounding the outer periphery of the corresponding memory cell array 110. . The memory cell array 110 is an aggregate of a plurality of memory cells each including a ferroelectric capacitor. The moisture-proof ring 120 functions as an annular protective wall that suppresses the reduction of the ferroelectric film made of an oxide such as PZT constituting each memory cell by suppressing the entry of hydrogen and moisture into the memory cell array 110. To do. As shown in FIG. 1, the moisture-proof ring 120 having a double ring structure can enhance the effect of suppressing entry of hydrogen and moisture into the memory cell array 110. The moisture-proof ring 120 may have a single ring structure.

  The semiconductor device 100 further includes an annular moisture-proof ring 130 provided so as to surround the plurality of memory cell arrays 110 and the plurality of moisture-proof rings 120. That is, the moisture-proof ring 130 surrounds the outer edge of the semiconductor chip region. The moisture-proof ring 130 functions together with the moisture-proof ring 120 as an annular protective wall that suppresses entry of hydrogen and moisture into the memory cell array 110.

  FIG. 2 is an equivalent circuit diagram illustrating two adjacent memory cells MC1 and MC2 among the plurality of memory cells constituting the memory cell array 110. In this embodiment, each of the plurality of memory cells constituting the memory cell array 110 has a 2T / 2C type configuration in which 1-bit data is complementarily stored by two transistors and two ferroelectric capacitors. That is, the memory cell MC1 includes transistors Ta1 and Tb1 and ferroelectric capacitors Ca1 and Cb1, and the memory cell MC2 includes transistors Ta2 and Tb2 and ferroelectric capacitors Ca2 and Cb2. The transistor Ta1 of the memory cell MC1 has a drain connected to the bit line BL1, a gate connected to the word line WL1, and a source connected to one end of the ferroelectric capacitor Ca1. The transistor Tb1 of the memory cell MC1 has a drain connected to the bit line BL2, a gate connected to the word line WL1, and a source connected to one end of the ferroelectric capacitor Cb1. The other ends of the ferroelectric capacitors Ca1 and Cb1 of the memory cell MC1 are connected to the plate line PL1. The transistor Ta2 of the memory cell MC2 has a drain connected to the bit line BL1, a gate connected to the word line WL2, and a source connected to one end of the ferroelectric capacitor Ca2. The transistor Tb2 of the memory cell MC2 has a drain connected to the bit line BL2, a gate connected to the word line WL2, and a source connected to one end of the ferroelectric capacitor Cb2. The other ends of the ferroelectric capacitors Ca2 and Cb2 of the memory cell MC2 are connected to the plate line PL2.

  FIG. 3 is a cross-sectional view schematically showing a cross-sectional structure of the semiconductor device 100. 3 includes the transistor Ta1 and the ferroelectric capacitor Ca1 constituting the memory cell MC1, the transistor Ta2 and the ferroelectric capacitor Ca2 constituting the memory cell MC2, and the memory cells shown in FIG. A part of the moisture-proof ring 120 surrounding the outer periphery of the memory cell array is shown. In FIG. 3, the moisture-proof ring 130 (see FIG. 1) is not shown, but the structure of the moisture-proof ring 130 may be the same as the moisture-proof ring 120. First, the structure of the formation region of the memory cell array including the memory cells MC1 and MC2 will be described.

The semiconductor device 100 includes a semiconductor substrate 11 such as a P-type silicon substrate, for example. In the surface layer portion of the semiconductor substrate 11, an element isolation region 12 made of an insulator such as SiO ₂ that defines the formation regions of the transistors Ta 1 and Ta ₂ is provided.

Further, in the surface layer portion of the semiconductor substrate 11, the sources S1 and S2 and the drain D of the transistors Ta1 and Ta2 are provided. The sources S1, S2 and the drain D are composed of an N-type semiconductor. The transistors Ta1 and Ta2 share the drain D. Note that a P well may be provided in the surface layer portion of the semiconductor substrate 11, and the sources S1, S2 and the drain D may be provided in the P well. On the semiconductor substrate 11, gates G1 and G2 are provided via gate insulating films OX1 and OX2. The gate insulating film OX1 and OX2, for example, consists of SiO _2, the gate G1 and G2, for example, is formed of polysilicon. The gates G1 and G2 function as word lines WL1 and WL2 (see FIG. 2), respectively. Sidewalls 14 made of an insulator such as SiO ₂ are provided on the side surfaces of the gates G1 and G2. Silicide layers 13 are provided on the surfaces of the sources S1, S2, the drain D, and the gates G1, G2, respectively, for reducing the contact resistance.

A cover film 21, an interlayer insulating film 22, an etch stopper film 23, an interlayer insulating film 24, an antioxidant film 25, and a buffer film 26 are stacked on the transistors Ta1 and Ta2. The cover film 21, the etch stopper film 23, and the antioxidant film 25 are made of an insulator such as SiN, and the interlayer insulating films 22 and 24 and the buffer film 26 are made of an insulator such as SiO ₂ .

  Plugs 31, 32, and 33 made of a conductor such as tungsten penetrate the interlayer insulating film 22 and the cover film 21, and are connected to the sources S1, S2, and the drain D, respectively. A wiring 34 functioning as a bit line BL (see FIG. 2) is provided in the interlayer insulating film 24. The wiring 34 is connected to the drains D of the transistors Ta1 and Ta2 through the plug 33. Further, plugs 35 and 36 made of a conductor such as tungsten penetrate the buffer film 26, the antioxidant film 25, the interlayer insulating film 24, and the etch stopper film 23, respectively, and are connected to the plugs 31 and 32. .

On the buffer film 26, ferroelectric capacitors Ca1 and Ca2 are provided. The ferroelectric capacitors Ca1 and Ca2 have a laminated structure in which a lower electrode 41, a ferroelectric film 42, and an upper electrode 43 are laminated. The lower electrode 41 includes a TiN film 44, a TiAlN film 45, and an Ir film 46. The upper electrode 43 includes an IrO ₂ film 47 and an Ir film 48. The ferroelectric film 42 includes a PZT film. The lower electrode 41 of the ferroelectric capacitor Ca1 is connected to the source S1 of the transistor Ta1 via plugs 35 and 31, and the lower electrode 41 of the ferroelectric capacitor Ca2 is connected to the source S2 of the transistor Ta2 via plugs 36 and 32. It is connected to the.

The surfaces of the ferroelectric capacitors Ca1 and Ca2 are covered with a hydrogen barrier film 49 made of an insulator such as Al ₂ O ₃ or TiO ₂ . The hydrogen barrier film 49 functions as a protective film that suppresses intrusion of hydrogen and moisture into the ferroelectric capacitors Ca1 and Ca2. On the hydrogen barrier film 49, interlayer insulating films 51 and 52 made of an insulator such as SiO ₂ are laminated. The thickness of the interlayer insulating film 51 is, for example, about 680 nm, and the thickness of the interlayer insulating film 52 is, for example, about 250 nm. Plugs 53 and 54 made of a conductor such as tungsten penetrate the interlayer insulating films 51 and 52, respectively, and are connected to the upper electrodes 43 of the ferroelectric capacitors C1 and C2.

  On the interlayer insulating film 52, wirings 61 and 62 functioning as plate lines PL1 and PL2 (see FIG. 2) are provided, respectively. The wirings 61 and 62 are configured by laminating a barrier film 63, an aluminum copper alloy film 64, and a barrier film 65, respectively. The barrier films 63 and 65 each include a Ti film and a TiN film. The wirings 61 and 62 are connected to the upper electrodes 43 of the ferroelectric capacitors Ca1 and Ca2 via plugs 53 and 54, respectively.

  Next, the structure of the formation region of the moisture-proof ring 120 will be described. The moisture-proof ring 120 includes conductor rings 71, 72, 74, and 75 and a capacitor structure ring 73 that form annular walls surrounding the memory cell array including the memory cells MC1 and MC2.

  The conductor ring 71 is provided in the same layer (same depth position) as the plugs 31, 32 and 33, and penetrates the interlayer insulating film 22 and reaches the semiconductor substrate 11. The conductor ring 71 is made of a metal containing tungsten, like the plugs 31, 32, and 33. The conductor ring 71 forms an annular wall surrounding the outer periphery of the memory cell array including the memory cells MC1 and MC2.

  The conductor ring 72 is provided in the same layer (same depth position) as the plugs 35 and 36, penetrates the buffer film 26, the antioxidant film 25, the interlayer insulating film 24, and the etch stopper film 23, and forms a conductor ring 71. It is connected. Similar to the plugs 35 and 36, the conductor ring 72 is made of a metal containing tungsten. The conductor ring 72 forms an annular wall surrounding the outer periphery of the memory cell array including the memory cells MC1 and MC2.

The capacitor structure ring 73 is provided in the same layer (same depth position) as the ferroelectric capacitors Ca1 and Ca2. The capacitor structure ring 73 has the same multilayer structure as the ferroelectric capacitors Ca1 and Ca2. That is, the capacitor structure ring 73 has a laminated structure in which a TiN film 44, a TiAlN film 45, an Ir film 46, a ferroelectric film 42 (PZT film), an IrO ₂ film 47, and an Ir film 48 are laminated. The capacitor structure ring 73 forms an annular wall surrounding the outer periphery of the memory cell array including the memory cells MC1 and MC2. The bottom surface of the capacitor structure ring 73 is connected to the conductor ring 72, and the top surface of the capacitor structure ring 73 is connected to the conductor ring 74. Although the capacitor structure ring 73 has a capacitor structure, it does not function as a capacitor, but functions exclusively as a protective wall that suppresses the entry of hydrogen and moisture into the memory cell array including the memory cells MC1 and MC2.

  The conductor ring 74 is provided in the same layer (same depth position) as the plugs 53 and 54, passes through the interlayer insulating films 51 and 52, and is connected to the capacitor structure ring 73. Similar to the plugs 53 and 54, the conductor ring 74 is made of a metal containing tungsten. The conductor ring 74 forms an annular wall surrounding the outer periphery of the memory cell array including the memory cells MC1 and MC2.

  The conductor ring 75 is provided in the same layer (same depth position) as the wirings 61 and 62. That is, the conductor ring 75 is provided on the interlayer insulating film 52 and is connected to the conductor ring 74. The conductor ring 75 has the same laminated structure as the wirings 61 and 62, and is configured by laminating a barrier film, an aluminum alloy film, and a barrier film. The conductor ring 75 forms an annular wall surrounding the outer periphery of the memory cell array including the memory cells MC1 and MC2.

The interlayer insulating films 51 and 52 are mainly composed of the same material (SiO ₂ ), but the film stress of the upper interlayer insulating film 52 is smaller than the film stress of the lower interlayer insulating film 51. Yes. That is, the magnitude of stress applied to other adjacent films is smaller in the upper interlayer insulating film 52 than in the lower interlayer insulating film 51. By making the film stress of the interlayer insulating film 52 smaller than the film stress of the interlayer insulating film 51, the generation of cracks in the vicinity of the interface of the interlayer insulating film 52 with the moisture-proof ring 120 (conductor ring 74) can be suppressed. . On the other hand, the lower interlayer insulating film 51 has a certain film density, that is, a certain film stress in order to suppress the intrusion of hydrogen and moisture into the ferroelectric capacitors Ca1 and Ca2. It is preferable.

  The film stress of the upper interlayer insulating film 52 is preferably 1/7 or more and 1/2 or less of the film stress of the lower interlayer insulating film 51. The film stress of the upper interlayer insulating film 52 is preferably −100 MPa or more and −50 MPa or less. On the other hand, the film stress of the lower interlayer insulating film 51 is preferably −350 Mpa or more and −250 Mpa or less.

  The film stress of the interlayer insulating films 51 and 52 can be controlled by the film forming conditions of these films. The interlayer insulating films 51 and 52 are formed by, for example, a known plasma CVD (chemical vapor deposition) method. When the interlayer insulating films 51 and 52 are formed by the plasma CVD method, the film stress can be reduced as the ion irradiation amount during the film formation is reduced. In order to reduce the ion irradiation amount, for example, the RF power may be reduced or the pressure in the chamber of the plasma CVD apparatus may be increased.

  The film stress of the interlayer insulating films 51 and 52 can be estimated as follows. 4A, 4B, and 4C are diagrams illustrating a method for estimating the film stress of the interlayer insulating films 51 and 52. FIG. First, a thin film 210 corresponding to the interlayer insulating film 51 or 52 is formed on a flat substrate 200 such as a semiconductor wafer. That is, the thin film 210 is formed on the substrate 200 under the same conditions and the same film thickness as when the interlayer insulating film 51 or 52 is formed (FIG. 4A).

  The film stress of the thin film 210 is a force applied per unit area of a cross section perpendicular to the substrate surface. A force acting in a direction pushing the cross section is called a compressive stress, and a force acting in the direction pulling the cross section is a tensile stress. Call it. When tensile stress is generated, the substrate 200 is warped on the thin film 210 side as shown in FIG. 4B, and when compressive stress is generated, the substrate 200 is as shown in FIG. 4C. In addition, the substrate 200 is warped.

The film stress σ of the thin film 210 can be calculated from the Stony equation shown in the following equation (1).
σ = (ED ² ) / 6 (1-ν) Rt (1)
In equation (1), E is the Young's modulus of the substrate 200, D is the thickness of the substrate 200, and ν is the Poisson's ratio of the substrate 200. t is the thickness of the thin film 210, and R is the radius of curvature of the warp of the substrate 200 that has warped as the thin film 210 is formed. E, D, and ν are determined by the material of the substrate 200, and t can be measured using a film thickness measuring device. R can be measured using a film stress measuring apparatus. When tensile stress is generated, the film stress σ takes a positive value, and when compressive stress is generated, the film stress σ takes a negative value.

  A method for manufacturing the semiconductor device 100 will be described below. 5A to 5I are cross-sectional views illustrating the manufacturing process of the semiconductor device 100.

First, for example, an element isolation region 12 is formed in a surface layer portion of a semiconductor substrate 11 formed of a P-type silicon substrate by using a known STI (shallow trench isolation) technique. Thereafter, ion implantation is performed to form a well, a channel stop diffusion layer (both not shown), and the like. Next, SiO ₂ films constituting the gate insulating films OX1 and OX2 are formed on the surface of the semiconductor substrate 11 using a known thermal oxidation method. Next, a polysilicon film constituting the gates G1 and G2 is formed on the SiO ₂ film constituting the gate insulating films OX1 and OX2 by using a known CVD method. Next, gate insulating films OX1 and OX2 and gates G1 and G2 are formed by patterning the SiO ₂ film and the polysilicon film using a known photolithography technique (FIG. 5A).

Next, ion implantation for forming an LDD (lightly doped drain) structure is performed to form an N-type diffusion layer (not shown). Subsequently, an insulating film such as SiO ₂ is formed on the semiconductor substrate 11 so as to cover the gates G1 and G2 by using a well-known CVD method, and then the insulating film is etched back to thereby form side surfaces of the gates G1 and G2. A sidewall 14 is formed to cover the surface. Next, using the gates G1 and G2 and the sidewalls 14 as a mask, ion implantation for forming the drain D and the sources S1 and S2 is performed, and then heat treatment is performed to form the drain S and the sources S1 and S2. The N type impurity diffusion region to be activated is activated. Next, a silicide layer 13 for reducing the contact resistance is formed on the surfaces of the drain D, the sources S1, S2 and the gates G1, G2 by using a known salicide process. Through the above steps, transistors Ta1 and Ta2 are formed on the semiconductor substrate 11 (FIG. 5B).

Next, an insulator such as Si ₃ N ₄ is deposited on the surfaces of the transistors Ta1 and Ta2 by using a known CVD method to form the cover film 21 having a thickness of about 70 nm. Next, an interlayer insulating film 22 made of an insulator such as SiO ₂ is formed on the cover film 21 using a known CVD method, and then the surface of the interlayer insulating film 22 is used using a known CMP (chemical mechanical polish) method. To flatten. Next, contact holes reaching the drain D and the sources S1 and S2 are formed in the interlayer insulating film 22 and the cover film 21, respectively, using a known photolithography technique. In the formation region of the moisture-proof ring 120, an annular groove that surrounds the outer periphery of the formation region of the memory cell array and reaches the semiconductor substrate 11 is formed in parallel with the formation of the contact hole. Next, a Ti film and a TiN film functioning as an adhesion layer are sequentially formed on the side and bottom surfaces of the contact hole and the annular groove, and then the contact hole and the annular groove are filled with tungsten. Next, the plugs 31, 32, and 33 and the conductor ring 71 are formed by removing the excess Ti film, TiN film, and tungsten deposited on the interlayer insulating film 22 using a known CMP method (FIG. 5C). ).

Next, an insulator such as Si ₃ N ₄ is deposited on the interlayer insulating film 22 using a known CVD method to form an etch stopper film 23 having a thickness of about 40 nm. Subsequently, an interlayer insulating film 24 made of an insulator such as SiO ₂ is formed on the etch stopper film 23 using a known CVD method. Next, a line-shaped groove is formed in the formation region of the wiring 34 in the interlayer insulating film 24 using a known photolithography technique. Subsequently, a Ti film and a TiN film functioning as an adhesion layer are formed on the side surface and the bottom surface of the line-shaped groove, and then the line-shaped groove is filled with tungsten. Next, the excess Ti film, TiN film, and tungsten deposited on the interlayer insulating film 24 are removed using a known CMP method, thereby forming a wiring 34 that functions as a bit line BL (see FIG. 2) (see FIG. 2). FIG. 5D).

Next, an insulator such as Si ₃ N ₄ is deposited on the interlayer insulating film 24 using a known CVD method to form an antioxidant film 25 having a thickness of about 100 nm. Subsequently, an insulator such as SiO ₂ is deposited on the antioxidant film 25 using a known CVD method to form the buffer film 26 having a thickness of about 230 nm. Subsequently, contact holes reaching the plugs 31 and 32 are formed through the buffer film 26, the antioxidant film 25, the interlayer insulating film 24, and the etch stopper film 23 using a known photolithography technique. In the formation region of the moisture-proof ring 120, in parallel with the formation of the contact hole, the outer periphery of the formation region of the memory cell array is surrounded and penetrated through the buffer film 26, the antioxidant film 25, the interlayer insulating film 24, and the etch stopper film 23. Thus, an annular groove reaching the conductor ring 71 is formed. Next, a Ti film and a TiN film functioning as an adhesion layer are formed on the side and bottom surfaces of the contact hole and the annular groove, and then the contact hole and the annular groove are filled with tungsten. Next, the plugs 35 and 36 and the conductor ring 72 are formed by removing excess Ti film, TiN film and tungsten deposited on the buffer film 26 by using a known CMP method. Plugs 35 and 36 are connected to plugs 31 and 32, respectively. The conductor ring 72 is connected to the conductor ring 71 (FIG. 5E).

Next, ferroelectric capacitors Ca 1 and Ca 2 and a capacitor structure ring 73 are formed on the buffer film 26. First, a TiN film 44 that functions as an adhesion layer is formed on the buffer film 26. Next, a TiAlN film 45 is formed on the TiN film 44. The TiAlN film 45 functions as an antioxidant electrode that prevents the plugs 35 and 36 from being oxidized by the crystallization process of the ferroelectric film 42 that is performed in a later step. Next, an Ir film 46 is formed on the TiAlN film 45. Thereby, the lower electrode 41 including the TiN film 44, the TiAlN film 45, and the Ir film 46 is formed. Next, a ferroelectric film 42 is formed by depositing PZT on the lower electrode 41. Thereafter, a rapid heating process is performed on the ferroelectric film 42. As a result, excess element is eliminated and oxidized in the ferroelectric film 42, and the crystallization of the ferroelectric film 42 is completed. Next, an IrO ₂ film 47 and an Ir film 48 are sequentially formed on the ferroelectric film 42 to form the upper electrode 43. Next, each of the above films stacked on the buffer film 26 is patterned by using a known photolithography technique. As a result, the ferroelectric capacitors Ca 1 and Ca 2 and the capacitor structure ring 73 are formed on the buffer film 26. The capacitor structure ring 73 is patterned into an annular shape surrounding the outer periphery of the memory cell array formation region (FIG. 5F).

Next, using a known CVD method, a hydrogen barrier film 49 having a thickness of about 50 nm made of an insulator such as Al ₂ O ₃ so as to cover the upper and side surfaces of the ferroelectric capacitors Ca 1 and Ca 2 and the capacitor structure ring 73. Form. Note that TiO ₂ may be used as the material of the hydrogen barrier film 49. Next, an interlayer insulating film 51 having a thickness of about 1400 nm mainly containing SiO ₂ is formed on the hydrogen barrier film 49 by using a known plasma CVD method using a mixed gas containing TEOS (Tetraethyl orthosilicate), oxygen and helium. To do. The formation of the interlayer insulating film 51 is preferably performed under conditions that can eliminate hydrogen and moisture in the interlayer insulating film 51 in order to prevent deterioration of the characteristics of the ferroelectric capacitors Ca1 and Ca2. Specifically, it can be realized by measures such as increasing the film formation temperature, increasing the gas pressure, and increasing the oxygen flow rate. After the formation of the interlayer insulating film 51, the surface of the interlayer insulating film 51 is planarized using a known CMP method. Thereafter, heat treatment is performed with respect to the N 2 _O gas or N ₂ interlayer insulation film 51 in a plasma atmosphere generated by using a gas or the like. By this heat treatment, moisture contained in the interlayer insulating film 51 is removed and the film quality of the interlayer insulating film 51 is changed, and entry of hydrogen and moisture into the interlayer insulating film 51 is suppressed (FIG. 5G). .

Next, an interlayer insulating film 52 having a thickness of about 250 nm mainly containing SiO ₂ is formed on the interlayer insulating film 51 by using a known plasma CVD method using a mixed gas containing silane, N ₂ O and N ₂ . The interlayer insulating film 52 is formed under the condition that the film stress is smaller than that of the interlayer insulating film 51. For example, the film stress of the interlayer insulating film 52 is made higher than the film stress of the interlayer insulating film 51 by making the ion irradiation amount when forming the interlayer insulating film 52 smaller than the ion irradiation amount when forming the interlayer insulating film 51. Can also be reduced. In order to reduce the ion irradiation amount, for example, the RF power may be reduced or the pressure in the chamber of the plasma CVD apparatus may be increased. The ion irradiation amount also varies depending on the configuration of the plasma CVD apparatus, and the film formation conditions for obtaining a film having a desired film stress vary depending on the apparatus configuration. Therefore, an optimum film forming condition may be set while changing various parameters for each apparatus. Even if a recess is formed in the region between the ferroelectric capacitors C1 and C2 on the surface of the interlayer insulating film 51 by the influence of CMP by further forming the interlayer insulating film 52 on the surface of the interlayer insulating film 51. The recess is filled with the interlayer insulating film 52 and planarized. After forming the interlayer insulating film 52, N heat treatment is preferably performed in the interlayer insulating film 52 by a plasma atmosphere generated by using 2 _O gas or N ₂ gas or the like. By this heat treatment, moisture contained in the interlayer insulating film 52 is removed and the film quality of the interlayer insulating film 52 is changed, and entry of hydrogen and moisture into the interlayer insulating film 52 is suppressed (FIG. 5H). .

  Next, a contact hole reaching the upper electrode 43 of the ferroelectric capacitors Ca1 and Ca2 through the interlayer insulating films 51 and 52 and the hydrogen barrier film 49 is formed using a known photolithography technique. In the formation region of the moisture-proof ring 120, in parallel with the formation of the contact hole, the outer periphery of the formation region of the memory cell array is surrounded and penetrated through the interlayer insulating films 51 and 52 and the hydrogen barrier film 49 to reach the capacitor structure ring 73. An annular groove is formed. Next, a Ti film and a TiN film functioning as an adhesion layer are formed on the side and bottom surfaces of the contact hole and the annular groove, and then the contact hole and the annular groove are filled with tungsten. Next, the plugs 53 and 54 and the conductor ring 74 are formed by removing excess Ti film, TiN film and tungsten deposited on the interlayer insulating film 52 by using a known CMP method. Plugs 53 and 54 are connected to the upper electrodes 43 of the ferroelectric capacitors Ca1 and Ca2, respectively. The conductor ring 74 is connected to the capacitor structure ring 73 (FIG. 5H).

  Next, a barrier film 63 including a Ti film and a TiN film, an aluminum copper alloy film 64, and a barrier film 65 including a Ti film and a TiN film are stacked on the surface of the interlayer insulating film 52. Subsequently, these films are patterned using a known photolithography technique to form wirings 61 and 62 that function as plate lines PL1 and PL2 (see FIG. 2), respectively, and a conductor ring 75. The wirings 61 and 62 are connected to the upper electrodes 43 of the ferroelectric capacitors Ca1 and Ca2 via plugs 53 and 54, respectively. The conductor ring 75 is connected to the conductor ring 74 (FIG. 5I). The semiconductor device 100 is completed through the above steps.

  The inventor makes the film formation condition of the interlayer insulation film 52 the same as the film formation condition of the interlayer insulation film 51, that is, the film stress of the interlayer insulation film 52 is equal to the film stress of the interlayer insulation film 51. In addition, it was discovered that cracks occur in the vicinity of the formation region of the moisture-proof ring 120 of the interlayer insulating film 52. 6A and 6B are a partial plan view and a cross-sectional view, respectively, showing the crack generation site. When the film stress of the interlayer insulating film 52 is equal to the film stress of the interlayer insulating film 51, a crack 300 is generated in the interlayer insulating film 52 along the extending direction of the conductor ring 74. The crack 300 is formed by filling the annular groove formed in the interlayer insulating films 51 and 52 with a conductor such as tungsten in the annular groove for forming the conductor ring 74, and then surplus conductor deposited on the interlayer insulating film 52 in CMP. Occurs when removing. On the other hand, no cracks are generated around the plugs 53 and 54.

  FIGS. 7A and 7B are cross-sectional views showing the generation mechanism of the crack 300 in the interlayer insulating film 52. In the process of forming the conductor ring 74, the conductors (Ti film, TiN film and tungsten) 310 are filled in the annular groove 320 formed in the interlayer insulating films 51 and 52 as shown in FIG. Deposit on film 52. The stress F1 is generated due to the difference in thermal expansion coefficient between the conductor 310 and the interlayer insulating films 51 and 52. However, the stress F1 is relieved by the conductor 310 being deposited also on the interlayer insulating film 52. However, in the subsequent CMP, as shown in FIG. 7B, when the conductor 310 deposited on the interlayer insulating film 52 is removed, the stress F1 becomes significant, and a crack 300 is generated in the interlayer insulating film 52. At the site where the crack 300 occurs, the diffusion rate of hydrogen and moisture increases. Therefore, as the generation range of the crack 300 is expanded, the ferroelectric films 42 of the ferroelectric capacitors Ca1 and Ca2 are easily reduced, and the memory performance is deteriorated. The magnitude of the stress F1 depends on the magnitude of the film stress of the interlayer insulating film 52, and is considered to increase as the film stress increases in the interlayer insulating film 52.

  According to the semiconductor device 100 according to the embodiment of the disclosed technique, since the film stress of the interlayer insulating film 52 is smaller than the film stress of the interlayer insulating film 51, the compressive stress acting on the interlayer insulating film 52 when the conductor ring 74 is formed. F1 can be relaxed. Therefore, generation of cracks in the interlayer insulating film 52 can be suppressed, and reduction of the ferroelectric film 42 that causes deterioration of memory performance can be suppressed.

  On the other hand, by making the film stress of the interlayer insulating film 52 smaller than the film stress of the interlayer insulating film 51, the interlayer insulating film 52 has a low density and suppresses the penetration of hydrogen and moisture into the ferroelectric capacitors Ca1 and Ca2. Function may be degraded. However, the function of suppressing the entry of hydrogen and moisture into the ferroelectric capacitors Ca1 and Ca2 is secured by the interlayer insulating film 51 having a relatively large film stress and high density.

  Further, according to the semiconductor device 100 according to the embodiment of the disclosed technology, the moisture-proof ring 120 can suppress the intrusion of hydrogen and moisture into the ferroelectric capacitors Ca1 and Ca2, and the reduction of the ferroelectric film 42. Can be suppressed. The moisture-proof ring 120 has a capacitor structure ring 73 having a stacked structure similar to that of the ferroelectric capacitors Ca1 and Ca2. Since the capacitor structure ring 73 has the same stacked structure as the ferroelectric capacitors Ca1 and Ca2, the ferroelectric capacitors Ca1 and Ca2 and the capacitor structure ring 73 can be formed simultaneously. Therefore, intrusion of hydrogen and moisture into the ferroelectric capacitors Ca1 and Ca2 during the formation of the ferroelectric capacitors Ca1 and Ca2 can be effectively suppressed by the capacitor structure ring 73.

  In the semiconductor device 100 according to the embodiment of the disclosed technique and the semiconductor device according to the comparative example in which the film stress of the interlayer insulating film 52 is equal to the film stress of the interlayer insulating film 51, the polarization characteristics and leakage of the ferroelectric capacitor The current characteristics were compared. The results are shown in FIGS. 8A and 8B.

  FIG. 8A is a graph showing the relationship between the amount of polarization in a ferroelectric capacitor and its variation (standard deviation) σ. As shown in FIG. 8A, according to the semiconductor device 100 according to the embodiment of the disclosed technique, the polarization amount of the ferroelectric capacitor is larger than that of the semiconductor device according to the comparative example, which is preferable as the ferroelectric capacitor. Characteristics were obtained.

  FIG. 8B is a graph showing the relationship between the leakage current in the ferroelectric capacitor and its variation (standard deviation) σ. As shown in FIG. 8B, according to the semiconductor device 100 according to the embodiment of the disclosed technique, the leakage current of the ferroelectric capacitor is smaller than that of the semiconductor device according to the comparative example, which is preferable as the ferroelectric capacitor. Characteristics were obtained.

  In addition, the manufacturing yield was compared between the semiconductor device 100 according to an embodiment of the disclosed technology and the semiconductor device according to the comparative example. The results are shown in Table 1 below. Table 1 shows the yield and the overall yield when the retention performance, the imprint performance, and the low-temperature operation performance of the ferroelectric memory are inspected on the basis of the semiconductor device according to the comparative example. In the retention performance test, predetermined data is written into the memory cell, the memory cell is left at a high temperature, and then it is determined whether or not the read data is an appropriate value. In the imprint performance test, after the retention performance test, data different from the data written first is written to determine whether or not the read data is an appropriate value.

  According to the semiconductor device 100 according to the embodiment of the disclosed technology, the yield and the overall yield in the retention performance, the imprint performance, and the low-temperature operation performance in the ferroelectric memory are higher than those in the semiconductor device according to the comparative example. This is considered to be due to the effect of suppressing the reduction of the ferroelectric film 42 by suppressing the generation of cracks in the interlayer insulating film 52.

  In the above description, the case where the disclosed technology is applied to a 2T / 2C type ferroelectric memory is illustrated, but a 1T / 1C type memory that stores 1-bit data with one transistor and one ferroelectric capacitor. The disclosed technology can also be applied to the ferroelectric memory.

  Note that the semiconductor device 100 is an example of a semiconductor device in the disclosed technology. The ferroelectric film 42 is an example of a ferroelectric film in the disclosed technology. The ferroelectric capacitors C1 and C2 are examples of ferroelectric capacitors in the disclosed technology. The interlayer insulating film 51 is an example of a first insulating film in the disclosed technology. The interlayer insulating film 52 is an example of a second insulating film in the disclosed technology. The moisture-proof ring 120 is an example of an annular structure in the disclosed technology.

  Regarding the above embodiment, the following additional notes are disclosed.

(Appendix 1)
A memory cell including a ferroelectric capacitor having a ferroelectric film;
A first insulating film covering the ferroelectric capacitor;
A second insulating film covering the first insulating film and having a film stress smaller than that of the first insulating film;
An annular structure embedded in the first insulating film and the second insulating film and surrounding an outer periphery of the memory cell;
A semiconductor device including:

(Appendix 2)
The semiconductor device according to claim 1, wherein the annular structure includes a metal surrounding an outer periphery of the memory cell.

(Appendix 3)
The ferroelectric capacitor has a laminated structure in which a plurality of films including the ferroelectric film are laminated,
The semiconductor device according to claim 1 or 2, wherein the annular structure has the same stacked structure as the stacked structure of the ferroelectric capacitors at the same depth position as the ferroelectric capacitor.

(Appendix 4)
The semiconductor device according to any one of appendix 1 to appendix 3, wherein the film thickness of the second insulating film is smaller than the film thickness of the first insulating film.

(Appendix 5)
Forming a memory cell including a ferroelectric capacitor having a ferroelectric film;
Forming a first insulating film covering the ferroelectric capacitor;
Forming a second insulating film that covers the first insulating film and has a smaller film stress than the first insulating film;
Forming an annular structure embedded in the first insulating film and the second insulating film and surrounding an outer periphery of the memory cell;
A method of manufacturing a semiconductor device including:

(Appendix 6)
The step of forming the annular structure includes
Forming an annular groove in the first insulating film and the second insulating film from the surface of the second insulating film to the inside of the first insulating film and surrounding the outer periphery of the memory cell; ,
Embedding a conductor in the annular groove;
Removing excess conductor deposited on the surface of the second insulating film;
The manufacturing method of Additional remark 5 containing.

(Appendix 7)
The ferroelectric capacitor has a laminated structure in which a plurality of films including the ferroelectric film are laminated,
The step of forming the annular structure includes
The method of appendix 5 or appendix 6, including the step of forming a capacitor structure ring that surrounds the outer periphery of the memory cell and has the same multilayer structure as the ferroelectric capacitor at the same depth as the ferroelectric capacitor. Manufacturing method.

(Appendix 8)
The manufacturing method according to any one of appendix 5 to appendix 7, wherein the film thickness of the second insulating film is smaller than the film thickness of the first insulating film.

11 Semiconductor substrate 51, 52 Interlayer insulating film 71, 72, 74, 75 Conductor ring 73 Capacitor structure ring 100 Semiconductor device 110 Memory cell array 120 Moisture-proof ring MC1, MC2 Memory cell Ta1, Ta2 Transistors Ca1, Ca2 Ferroelectric capacitor

Claims (7)

A memory cell including a ferroelectric capacitor having a ferroelectric film;
A first insulating film covering the ferroelectric capacitor;
A second insulating film covering the first insulating film and having a film stress smaller than that of the first insulating film;
An annular structure embedded in the first insulating film and the second insulating film and surrounding an outer periphery of the memory cell;
A semiconductor device including: The semiconductor device according to claim 1, wherein the annular structure includes a metal surrounding an outer periphery of the memory cell. The ferroelectric capacitor has a laminated structure in which a plurality of films including the ferroelectric film are laminated,
The semiconductor device according to claim 1, wherein the annular structure has the same stacked structure as the stacked structure of the ferroelectric capacitors at the same depth position as the ferroelectric capacitors. The semiconductor device according to claim 1, wherein a film thickness of the second insulating film is smaller than a film thickness of the first insulating film. Forming a memory cell including a ferroelectric capacitor having a ferroelectric film;
Forming a first insulating film covering the ferroelectric capacitor;
Forming a second insulating film that covers the first insulating film and has a smaller film stress than the first insulating film;
Forming an annular structure embedded in the first insulating film and the second insulating film and surrounding an outer periphery of the memory cell;
A method of manufacturing a semiconductor device including: The step of forming the annular structure includes
Forming an annular groove in the first insulating film and the second insulating film from the surface of the second insulating film to the inside of the first insulating film and surrounding the outer periphery of the memory cell; ,
Embedding a conductor in the annular groove;
Removing excess conductor deposited on the surface of the second insulating film;
The manufacturing method of Claim 5 containing this. The ferroelectric capacitor has a laminated structure in which a plurality of films including the ferroelectric film are laminated,
The step of forming the annular structure includes
7. The method of forming a capacitor structure ring surrounding the outer periphery of the memory cell and having the same stacked structure as the stacked structure of the ferroelectric capacitors at the same depth position as the ferroelectric capacitor. The manufacturing method as described in.