TWI540701B - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 95
- 238000000034 method Methods 0.000 title claims description 51
- 239000000463 material Substances 0.000 claims description 104
- 239000000758 substrate Substances 0.000 claims description 60
- 230000005669 field effect Effects 0.000 claims description 47
- 229910052751 metal Inorganic materials 0.000 claims description 46
- 239000002184 metal Substances 0.000 claims description 46
- 238000004519 manufacturing process Methods 0.000 claims description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 24
- 229920005591 polysilicon Polymers 0.000 claims description 24
- 238000000151 deposition Methods 0.000 claims description 12
- 238000002955 isolation Methods 0.000 claims description 8
- 229910044991 metal oxide Inorganic materials 0.000 claims description 7
- 150000004706 metal oxides Chemical class 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 description 14
- 238000005229 chemical vapour deposition Methods 0.000 description 13
- 238000000059 patterning Methods 0.000 description 11
- 238000000231 atomic layer deposition Methods 0.000 description 10
- 229910052732 germanium Inorganic materials 0.000 description 9
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 9
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 239000007789 gas Substances 0.000 description 6
- 238000001459 lithography Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000000395 magnesium oxide Substances 0.000 description 2
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 2
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 1
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- ODINCKMPIJJUCX-UHFFFAOYSA-N Calcium oxide Chemical compound [Ca]=O ODINCKMPIJJUCX-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910021193 La 2 O 3 Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- UDNUMJGZDOKTFU-UHFFFAOYSA-N germanium;methane Chemical compound C.[Ge] UDNUMJGZDOKTFU-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052740 iodine Inorganic materials 0.000 description 1
- 239000011630 iodine Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- -1 tungsten nitride Chemical class 0.000 description 1
Classifications
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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Description
本發明係關於半導體製作,且特別是關於一種半導體裝置及其製造方法。
半導體積體電路工業已經歷了快速成長。於積體電路材料以及設計等方面之技術演進已經製造出了數個世代的積體電路,其中每一世代之產品較前一世代之產品具有更小與更為複雜之電路。於積體電路之演進路程中,隨著幾何尺寸(geometry size,即採用製造技術所製備出之最小元件或導線之尺寸)的縮減,功能密度(functional density,即每一晶片區域內之內連裝置的數量)已經普遍地增加。如此之尺寸縮小製程通常藉由增加製作效率以及降低所需成本而增加了效益。如此之尺寸縮小亦增加了製程與積體電路製造的複雜性,由於可實現前述效益,因此於積體電路製程與製造中便需要相同之發展。
於傳統之積體電路(IC)設計中已見有場效電晶體(FET)的使用。基於技術節點的微縮,通常使用高介電常數(high-k)介電材料與金屬以形成場效電晶體之一閘堆疊物(gate stack)。於單一之積體電路晶片內形成不同之高介電常數/金屬
閘場效電晶體(high-k/metal gate FET)時存在有整合問題,例如為核心(core)p型場效電晶體、核心(core)n型場效電晶體、輸入輸出(input/output)n型場效電晶體、輸入輸出(input/output)p型場效電晶體與高電阻之高介電常數/金屬閘。因此,便需要一種製造不同有高介電常數/金屬閘結構之製程,以提供彈性與可行性。
依據一實施例,本發明提供了一種半導體裝置,包括:一半導體基板;複數個隔離元件,於該半導體基板上分隔出複數個區域;一p型場效電晶體核心區,具有位於該半導體基板上之一第一閘堆疊物,其中第一閘堆疊物包括一中間層、位於該中間層上之第一材料之一上蓋層、以及位於該第一材料之該上蓋層上之一高介電常數介電層;一p型場效電晶體輸入/輸出區,具有位於該半導體基板上之一第二閘堆疊物,其中該第二閘堆疊物包括一介電層、位於該介電層上之一中間層、位於該中間層上之該第一材料之一上蓋層、以及位於該第一材料之該上蓋層上之一高介電常數介電層;一n型場效電晶體核心區,具有位於該半導體基板上之一第三閘堆疊物,其中該第三閘堆疊物包括一中間層、位於該中間層上之一高介電常數介電層、以及位於該高介電常數介電層上之一第二材料之一上蓋層;一n型場效電晶體輸入/輸出區,具有位於該半導體基板上之一第四閘堆疊物,其中該第四閘堆疊物包括一介電層、位於該介電層上之一中間層、位於該中間層上之一高介電常數介電層、以及位於該高介電常數介電層上之該第二材料之一上
蓋層;以及一高電阻區,具有位於該半導體基板上之一第五閘堆疊物,該第五閘堆疊物包括一中間層、位於該中間層上之一高介電常數介電層、以及位於該高介電常數介電層上之該第二材料之一上蓋層。
另外,依據另一實施例,本發明提供了一種半導體裝置,包括:一半導體基板;複數個隔離元件,於該半導體基板上分隔出複數個區域;一p型場效電晶體核心區,具有位於該半導體基板上之一第一閘堆疊物,其中該第一閘堆疊物包括一中間層、位於該中間層上之一高介電常數介電層、以及位於該高介電常數介電層上之一第一材料之一上蓋層;一p型場效電晶體輸入/輸出區,具有位於該半導體基板上之一第二閘堆疊物,其中該第二閘堆疊物包括一介電層、位於該介電層上之一中間層、位於該中間層上之一高介電常數介電層、以及位於該高介電常數介電層上之一第一材料之一上蓋層;一n型場效電晶體核心區,具有位於該半導體基板上之一第三閘堆疊物,其中該第三閘堆疊物包括一中間層、位於該中間層上之一第二材料之一上蓋層、以及位於該第二材料之該上蓋層上之一高介電常數介電層;一n型場效電晶體輸入/輸出區,具有位於該半導體基板上之一第四閘堆疊物,其中該第四閘堆疊物包括一介電層、位於該介電層上之一中間層、位於該中間層上之該第二材料之一上蓋層、以及位於該第二材料之該上蓋層上之一高介電常數介電層;以及一高電阻區,具有位於該半導體基板上之一第五閘堆疊物,其中該第五閘堆疊物包括一中間層、位於該中間層上之該第二材料之一上蓋層、以及位於該第二材料
之該上蓋層上之一高介電常數介電層。
依據又一實施例,本發明提供了一種半導體裝置之製造方法,包括:提供一半導體基板,具有用於設置一n型場效電晶體核心區、一n型場效電晶體輸入輸出區、一p型場效電晶體核心區、一p型場效電晶體輸入輸出區以及一高電阻區之複數個區域;形成一氧化物層於該些輸入輸出區內之該半導體基板之上;形成一中間層於該半導體基板與該氧化物層之上;沉積一第一材料之一上蓋層於該中間層之上;沉積一高介電常數介電層於該第一材料之該上蓋層與該中間層之上;沉積一第二材料之一上蓋層於該高介電常數介電層之上;形成一功函數金屬層於該第二材料之該上蓋層之上;沉積一多晶矽層於該功函數金屬層之上;以及形成複數個閘堆疊物於該些區域內之該半導體基板之上。
為讓本發明之上述目的、特徵及優點能更明顯易懂,下文特舉一較佳實施例,並配合所附的圖式,作詳細說明如下。
100‧‧‧製造方法
102、104、106、108、110、112、114、116‧‧‧步驟
200‧‧‧半導體裝置
202‧‧‧半導體基板
203‧‧‧淺溝槽隔離物
204‧‧‧介電層
206‧‧‧中間層
208‧‧‧上蓋層
210‧‧‧高介電常數介電層
212‧‧‧上蓋層
214‧‧‧功函數金屬層
216‧‧‧多晶矽層
218‧‧‧硬罩幕層
230、280、330、380‧‧‧第一閘堆疊物
240、290、340、390‧‧‧第二閘堆疊物
250、300、350、400‧‧‧第三閘堆疊物
260、310、360、410‧‧‧第四閘堆疊物
270、320、370、420‧‧‧第五閘堆疊物
A‧‧‧n型場效電晶體核心區
B‧‧‧p型場效電晶體核心區
C‧‧‧n型場效電晶體輸入輸出區
D‧‧‧p型場效電晶體輸入輸出區
E‧‧‧高電阻區
第1圖為一流程圖,顯示了依據本發明之一實施例之一種具有多個閘堆疊物之半導體裝置之製造方法;第2-8圖為一系列剖面圖,分別顯示了依據本發明之一實施例之一種具有多個閘堆疊物之半導體裝置之製造方法之一中間階段;第9-11圖為一系列剖面圖,分別顯示了依據本發明之另一
實施例之一種具有多個閘堆疊物之半導體裝置之製造方法之一中間階段;第12-13圖為一系列剖面圖,分別顯示了依據本發明之又一實施例之一種具有多個閘堆疊物之半導體裝置之製造方法之一中間階段;以及第14-15圖為一系列剖面圖,分別顯示了依據本發明之一實施例之一種具有多個閘堆疊物之半導體裝置之製造方法之一中間階段。
可以理解的是,於下文中提供了用於施行本發明之不同特徵之多個不同實施例,或範例。基於簡化本發明之目的,以下描述了元件與設置情形之特定範例。然而,此些元件與設置情形僅作為範例之用而非用於限制本發明。此外,本發明於不同實施例中可能重複使用標號及/或文字。如此之重複情形係基於簡化與清楚之目的,而非用於限定不同實施例及/或討論形態內的相對關係。再者,於描述中關於於一第二元件之上或上之第一元件的形成可包括了第一元件與第二元件係為直接接觸之實施情形,且亦包括了於第一元件與第二元件之間包括了額外元件之實施情形,因而使得第一元件與第二元件之間並未直接接觸。
第1圖為一流程圖,顯示了依據本發明之一實施例之一種具有多個閘堆疊物之半導體裝置200之製造方法100。第2-8圖為一系列剖面圖,分別顯示了依據本發明之一實施例之具有多個閘堆疊物之半導體裝置200之不同製造階段。第9-11
圖為一系列剖面圖,分別顯示了依據本發明之另一實施例之一半導體裝置200。第12-13圖為一系列剖面圖,分別顯示了依據本發明之又一實施例之一半導體裝置200。第14-15圖為一系列剖面圖,分別顯示了依據本發明之一實施例之一半導體裝置200。半導體裝置200以及其製造方法100將藉由第1-15圖進行解說。
方法100起始於步驟102,提供一半導體基板202。半導體基板202包括矽。或者,半導體基板202包括鍺或矽鍺。或者,半導體基板202包括一磊晶層。舉例來說,半導體基板202可包括位於一塊狀半導體(bulk semiconductor)上之一磊晶層。再者,半導體基板202可經過應變以增強其表現。舉例來說,上述磊晶層可包括不同於形成塊狀半導體材料之一半導體材料,例如為位於塊狀矽上之一矽鍺層或者為位於塊狀矽鍺層上之一矽層。此應變基板可藉由選擇性磊晶成長(selective epitaxial growth,SEG)所形成。再者,半導體基板202可包括一絕緣層上覆半導體(SOI)結構。再者,半導體基板202可包括一埋設介電層,例如為一埋設氧化物層(BOX),其藉由如氧之佈植技術、晶圓接合、選擇性磊晶成長等方法或其他適當方法所形成。
半導體基板202亦包括多個摻雜區,例如為藉由如離子佈植之適當技術所形成之n井區與p井區。半導體基板202包括形成於基板內之如淺溝槽隔離物203之多個隔離元件以分隔形成多個元件區。淺溝槽隔離物203的形成可包括於半導體基板內蝕刻出一溝槽以及於溝槽內填入如氧化矽、氮化矽或氮
氧化矽之一或多個絕緣材料。經填滿之溝槽可具有如包括一熱氧化物襯層與填滿溝槽之氮化矽之一多膜層結構。於一實施例中,淺溝槽隔離物203係藉由使用下述之一製程順序所形成,例如:成長一墊氧化物、形成一低壓化學氣相沈積(LPCVD)之氮化物層、使用阻劑與光罩以圖案化出一淺溝槽隔離開口、於半導體基板內蝕刻出一溝槽、選擇性成長一熱氧化物溝槽襯層以改善溝槽介面、使用化學氣相沈積之氧化物填滿溝槽、使用化學機械平坦程序以進行研磨與平坦化。
半導體基板202包括多個元件區(device region)。此些元件區包括了多個n型場效電晶體(nFET)與p型場效電晶體(pFET)以及一或多個電阻(resistor)。於本實施例中,半導體基板202包括一n型場效電晶體核心(nFET core)區A、一n型場效電晶體輸入輸出(nFET I/O)區C、一p型場效電晶體核心(pFET core)區B、一p型場效電晶體輸入輸出(pFET I/O)區D與一高電阻(high-resistor)區E。
請參照第2圖,方法100接著進行步驟104,藉由如沉積、光阻圖案化與蝕刻製程等適當技術於此些輸入輸出區內半導體基板202之上形成一介電層204。介電層204包括了氧化物、或其他適合材料。於如第3圖所示及下一步驟106中,於半導體基板202以及介電層204(未顯示)之上形成中間層206。中間層206可包括由如原子層沉積(ALD)、熱氧化法、深紫外線-臭氧(UV-ozone)氧化法、或化學氣相沉積(CVD)之一適當技術所形成之氧化矽。
請參照第4圖,於步驟108中係於中間層206上沉積
一第一材料208之一上蓋層。上蓋層208可為具有p型功函數之一金屬或金屬氧化物,包括了氧化鋁(Al2O3)、氧化鎂(MgO)、氧化鈣(CaO)或其混合物。於本實施例中,上蓋層208包括了氧化鋁。上蓋層208係由如原子層沉積(ALD)、化學氣相沉積(CVD)、或物理氣相沉積(PVD)之一適當技術所形成。於一實施例中,上蓋層208具有少於50埃之一厚度。
請參照第5圖,採用微影與蝕刻製程以移除nFET核心區A、nFET輸入輸出區C與高電阻區E內之半導體基板202上之上蓋層208,進而圖案化了上蓋層208。上述微影製程例如包括阻劑圖案化、顯影與阻劑去除。於本製程中,係於上蓋層208上形成圖案化之一阻劑層。此圖案化之阻劑層包括了位於上蓋層208之露出部之用於後續蝕刻之多個開口。上述蝕刻製程包括一乾蝕刻、一濕蝕刻或一乾蝕刻與一濕蝕刻之組合。乾蝕刻製程可採用一含氟氣體(例如CF4、SF6、CH2F2、CHF3、及/或C2F6)、一含氯氣體(例如Cl2、CHCl3、CCl4、及/或BCl3)、一含溴氣體(例如HBr及/或CHBR3)、一含碘氣體、其他適當氣體、及/或電漿、及/或其組合。此蝕刻製程可包括一多重步驟蝕刻以得到蝕刻選擇性、彈性以及期望之蝕刻輪廓。
請參照步驟110與第6圖,形成一高介電常數介電層210於nFET核心區A、nFET輸入輸出區C以及高電阻區E內之中間層206上,以及於pFET核心區B與pFET輸入輸出區D內之第一材料之上蓋層208之上。高介電常數介電層210可包括HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化鋯、氧化鋁、二氧化鉿-氧化鋁合金、其他適當高介電常數介電材料或其組
合。高介電常數介電材料層210可藉由原子層沈積(ALD)、化學氣相沈積(CVD)或物理氣相沈積(PVD)之一適當製程所形成。形成高介電常數介電層210之其他方法包括了金屬有機化學氣相沈積(MOCVD)、深紫外線-臭氧氧化法(UV-ozone oxidation)、或分子束磊晶(MBE)等。於一實施例中,高介電常數介電層210具有少於50埃之一厚度。
請參照第7圖與步驟112,沉積一第二材料之一上蓋層212於高介電常數介電層210之上。上蓋層212可包括n型功函數之金屬與金屬氧化物,包括La2O3、Sc2O3、Y2O3、SrO、BaO、Ta2O5、TiO2、LaAlO3、ZrO2、Gd2O3、或其組合。於本實施例中,上蓋層212包括了氧化鑭。上蓋層212係由原子層沈積(ALD)、化學氣相沈積(CVD)或物理氣相沈積(PVD)之一適當製程所形成。於一實施例中,上蓋層212具有少於約50埃之一厚度。
請參照第7圖,接著繼續進行步驟114,沉積一功函數金屬層214於上蓋層212之上,以及沉積一多晶矽層216於功函數金屬層214之上。於本實施例中,功函數金屬層214包括由原子層沈積(ALD)、化學氣相沈積(CVD)或物理氣相沈積(PVD)之一適當技術所形成之氮化鈦。於其他實施例中,功函數金屬層214包括氮化鉭、氮化鎢、或其組合。於一實施例中,金屬層214具有少於200埃之一厚度。
多晶矽(或非晶矽)層216可藉由採用矽甲烷(SiH4)或其他矽基前驅物之化學氣相沉積所形成。非晶矽的沉積可於一較高溫度下施行。於一實施例中,此沉積溫度可大於400
℃。於一實施例中,此多晶矽(非晶矽)可使用包括含摻質氣體而臨場地摻雜。
方法100繼續步驟116,藉由圖案化與蝕刻製程形成不同之閘堆疊物。請參照第8圖,上述之多個閘膜層經過圖案化後形成了五個不同之閘堆疊物,包括了位於nFET核心區A上之第一閘堆疊物230、位於pFET核心區B上之一第二閘堆疊物240、位於nFET輸入輸出區C上之一第三閘堆疊物250、位於pFET輸入輸出區D上之一第四閘堆疊物260、以及位於高電阻區E上之一第五閘堆疊物270。於本實施例中,第一閘堆疊物230由下至上包括了中間層206、高介電常數介電層210、第二材料之上蓋層212、功函數金屬層214與多晶矽層216。第二閘堆疊物240由下至上包括了中間層206、第一材料之上蓋層208、高介電常數介電層210、第二材料之上蓋層212、功函數金屬層214與多晶矽層216。第三閘堆疊物250由下至上包括了介電層204(未顯示)、中間層206、高介電常數介電層210、第二材料之上蓋層212、功函數金屬層214以及多晶矽層216。第四閘堆疊物260由下至上包括了介電層204(未顯示)、中間層206、第一材料之上蓋層208、高介電常數介電層210、第二材料之上蓋層212、功函數金屬層214、以及多晶矽層216。第五閘堆疊物270由下至上包括了中間層206、高介電常數介電層210、第二材料之上蓋層212、功函數金屬層214以及多晶矽層216。
形成上述閘堆疊物之圖案化製程包括了一微影圖案化製程以及一蝕刻製程。舉例來說,上述微影圖案化製程包括阻劑圖案化、顯影與阻劑去除。於一實施例中,上述蝕刻製
程可更使用一硬罩幕層218做為一蝕刻罩幕。於此實施例中,係形成一硬罩幕層218於此些閘膜層之上,以及形成一圖案化阻劑層(未顯示)於此硬罩幕層218之上,接著針對硬罩幕層218施行一第一蝕刻製程,以及接著採用圖案化之硬罩幕層做為蝕刻罩幕而針對此些閘膜層進行一第二蝕刻製程。此硬罩幕層218可包括氮化矽及/或氧化矽。
如第8圖所示,位於pFET核心區B與pFET輸入輸出區D內之第二閘堆疊物240與第四閘堆疊物260分別包括第一材料之上蓋層208與第二材料之上蓋層212。第一材料之上蓋層208可具有較為接近半導體基板202之p型功函數。第二材料之上蓋層212可具有n型功函數,其位於上蓋層208之上且更為遠離半導體基板202。高介電常數介電層210係介於此些上蓋層208與212之間。
第9圖與第10圖顯示了依據另一實施例之一種半導體裝置200之製造方法。如第9圖所示,於本實施例中,可採用額外步驟。於步驟114內之沉積功函數金屬層214之前,可藉由微影與蝕刻製程以移除pFET核心區B與pFET輸入輸出區D內之第二材料之上蓋層212。於此額外步驟之後續步驟(即沉積功函數金屬層214與多晶矽層216)則大體相同於前述第7圖之相關描述以及如第10圖所示情形。
第11圖繪示了藉由圖案化與蝕刻製程以形成多個閘堆疊物之製作。相似於第8圖,此些閘膜層係經過圖案化以形成五個不同之閘堆疊物,包括了位於nFET核心區A上之第一閘堆疊物280、位於pFET核心區B上之一第二閘堆疊物290、位
於nFET輸入輸出區C上之一第三閘堆疊物300、位於pFET輸入輸出區D上之一第四閘堆疊物310、以及位於高電阻區E上之一第五閘堆疊物320。
於本實施例中,第一閘堆疊物280由下至上包括了中間層206、高介電常數介電層210、第二材料之上蓋層212、功函數金屬層214與多晶矽層216。第二閘堆疊物290由下至上包括了中間層206、第一材料之上蓋層208、高介電常數介電層210、功函數金屬層214與多晶矽層216。第三閘堆疊物300由下至上包括了介電層204(未顯示)、中間層206、高介電常數介電層210、第二材料之上蓋層212、功函數金屬層214以及多晶矽層216。第四閘堆疊物310由下至上包括了介電層204(未顯示)、中間層206、第一材料之上蓋層208、高介電常數介電層210、功函數金屬層214、以及多晶矽層216。第五閘堆疊物320由下至上包括了中間層206、高介電常數介電層210、第二材料之上蓋層212、功函數金屬層214以及多晶矽層216。
請參照第12圖,顯示了依據另一實施例之一製造方法100。此製造方法100主要如第1-3圖所示般進行了步驟102-106。於本實施例中,此製造方法100大體相似於如第4-7圖所示方法,除了於製程中之第一材料之上蓋層208與第二材料之上蓋層212的位置為顛倒的。舉例來說,第12圖相似於第4圖,但是係先設置上蓋層212以替代上蓋層208。此外,於本實施例中,自pFET核心區B以及pFET輸入輸出區D內移除上蓋層212以取代如第5圖所示之自nFET核心區A以及nFET輸入輸出區C內移除上蓋層208之實施情形。此製造方法100可繼續進行
所述步驟108-114。
如步驟116中與第13圖所示,藉由圖案化與蝕刻製程以形成多個閘堆疊物之製作。相似於第8圖,此些閘膜層係經過圖案化以形成五個不同之閘堆疊物,包括了位於nFET核心區A上之第一閘堆疊物330、位於pFET核心區B上之一第二閘堆疊物340、位於nFET輸入輸出區C上之一第三閘堆疊物350、位於pFET輸入輸出區D上之一第四閘堆疊物360、以及位於高電阻區E上之一第五閘堆疊物370。
於本實施例中,第一閘堆疊物330由下至上包括了中間層206、第二材料之上蓋層212、高介電常數介電層210、第一材料之上蓋層208、功函數金屬層214與多晶矽層216。第二閘堆疊物340由下至上包括了中間層206、高介電常數介電層210、第一材料之上蓋層208、功函數金屬層214、第二材料之上蓋層212與多晶矽層216。第三閘堆疊物350由下至上包括了介電層204(未顯示)、中間層206、第二材料之上蓋層212、高介電常數介電層210、第一材料之上蓋層208、功函數金屬層214以及多晶矽層216。第四閘堆疊物360由下至上包括了介電層204(未顯示)、中間層206、高介電常數介電層210、第一材料之上蓋層208、功函數金屬層214、以及多晶矽層216。第五閘堆疊物370由下至上包括了中間層206、第二材料之上蓋層212、高介電常數介電層210、第一材料之上蓋層208、功函數金屬層214以及多晶矽層216。
如第13圖所示,分別位於nFET核心區A與nFET輸入輸出區C內之第一閘堆疊物330與第二閘堆疊物350皆包括了
第一材料之上蓋層208與第二材料之上蓋層212,第二材料之上蓋層212可具有較為接近半導體基板202之n型功函數。而第一材料之上蓋層208可具有p型功函數,且其係位於第二材料之上蓋層212之上而較遠離於半導體基板202。高介電常數介電材料層係位於上蓋層208與上蓋層212之間。
請參照第14圖,顯示了依據又一實施例之一半導體裝置200之一種製造方法。於本實施例中,所使用之製造方法主要如第9-10圖所示般進行,除了於製程中之第一材料之上蓋層208與第二材料之上蓋層212的位置為顛倒的。於本實施例中,自nFET核心區A以及nFET輸入輸出區C內移除上蓋層208以取代如第9圖所示之自pFET核心區B以及pFET輸入輸出區D內移除上蓋層212之實施情形。
第15圖顯示了藉由圖案化與蝕刻製程以形成多個閘堆疊物之製作。相似於第13圖,此些閘膜層係經過圖案化以形成五個不同之閘堆疊物,包括了位於nFET核心區A上之第一閘堆疊物380、位於pFET核心區B上之一第二閘堆疊物390、位於nFET輸入輸出區C上之一第三閘堆疊物400、位於pFET輸入輸出區D上之一第四閘堆疊物410、以及位於高電阻區E上之一第五閘堆疊物420。
於本實施例中,第一閘堆疊物380由下至上包括了中間層206、第二材料之上蓋層212、高介電常數介電層210功函數金屬層214與多晶矽層216。第二閘堆疊物390由下至上包括了中間層206、高介電常數介電層210、第一材料之上蓋層208、功函數金屬層214與多晶矽層216。第三閘堆疊物400由下
至上包括了介電層204(未顯示)、中間層206、第二材料之上蓋層212、高介電常數介電層210、功函數金屬層214以及多晶矽層216。第四閘堆疊物410由下至上包括了介電層204(未顯示)、中間層206、高介電常數介電層210、第一材料之上蓋層208、功函數金屬層214、以及多晶矽層216。第五閘堆疊物420由下至上包括了中間層206、第二材料之上蓋層212、高介電常數介電層210、功函數金屬層214以及多晶矽層216。
本發明一或多個實施例之製造方法100與半導體裝置200之具有多項優點。本發明提供了可用於製造不同類型之半導體裝置之四種製程。此些方法為彈性的,其允許由改變n/p上蓋膜層沉積與圖案化的順序而形成不同之元件。由於可同時沉積多個閘堆疊物,故此些方法為有效的。本發明之方法與裝置提供了可用於整合具有核心/輸出輸入/電阻之一CMOS裝置之一彈性整合製程,並可同時維持其內NMOS裝置與PMOS裝置的合理臨界電壓。
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何熟習此項技藝者,在不脫離本發明之精神和範圍內,當可作更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧製造方法
102、104、106、108、110、112、114、116‧‧‧步驟
Claims (10)
- 一種半導體裝置,包括:一半導體基板;複數個隔離元件,於該半導體基板上分隔出複數個區域;一p型場效電晶體核心區,具有位於該半導體基板上之一第一閘堆疊物,其中第一閘堆疊物包括一中間層、位於該中間層上之第一材料之一上蓋層、以及位於該第一材料之該上蓋層上之一高介電常數介電層,其中該第一閘堆疊物之該中間層具有一第一厚度;一p型場效電晶體輸入/輸出區,具有位於該半導體基板上之一第二閘堆疊物,其中該第二閘堆疊物包括一介電層、位於該介電層上之一中間層、位於該中間層上之該第一材料之一上蓋層、以及位於該第一材料之該上蓋層上之一高介電常數介電層,其中該第二閘堆疊物之該中間層具有大於該第一厚度之一第二厚度;一n型場效電晶體核心區,具有位於該半導體基板上之一第三閘堆疊物,其中該第三閘堆疊物包括一中間層、位於該中間層上之一高介電常數介電層、以及位於該高介電常數介電層上之一第二材料之一上蓋層;一n型場效電晶體輸入/輸出區,具有位於該半導體基板上之一第四閘堆疊物,其中該第四閘堆疊物包括一介電層、位於該介電層上之一中間層、位於該中間層上之一高介電常數介電層、以及位於該高介電常數介電層上之該第二材料之一上蓋層;以及 一高電阻區,具有位於該半導體基板上之一第五閘堆疊物,該第五閘堆疊物包括一中間層、位於該中間層上之一高介電常數介電層、以及位於該高介電常數介電層上之該第二材料之一上蓋層。
- 如申請專利範圍第1項所述之半導體裝置,其中該第一閘堆疊物與該第二閘堆疊物更包括該第二材料之該上蓋層,位於該第一材料之該上蓋層之上,且其中該高介電常數介電層係介於該第一材料之該上蓋層與該第二材料之該上蓋層之間。
- 如申請專利範圍第1項所述之半導體裝置,其中該第一材料包括一p型功函數之金屬或金屬氧化物,而該第二材料包括一n型功函數之金屬或金屬氧化物。
- 一種半導體裝置,包括:一半導體基板;複數個隔離元件,於該半導體基板上分隔出複數個區域;一p型場效電晶體核心區,具有位於該半導體基板上之一第一閘堆疊物,其中該第一閘堆疊物包括一中間層、位於該中間層上之一高介電常數介電層、以及位於該高介電常數介電層上之一第一材料之一上蓋層,其中該第一閘堆疊物之該中間層具有一第一厚度;一p型場效電晶體輸入/輸出區,具有位於該半導體基板上之一第二閘堆疊物,其中該第二閘堆疊物包括一介電層、位於該介電層上之一中間層、位於該中間層上之一高介電常數介電層、以及位於該高介電常數介電層上之一第一材料 之一上蓋層,其中該第二閘堆疊物之該中間層具有大於該第一厚度之一第二厚度;一n型場效電晶體核心區,具有位於該半導體基板上之一第三閘堆疊物,其中該第三閘堆疊物包括一中間層、位於該中間層上之一第二材料之一上蓋層、以及位於該第二材料之該上蓋層上之一高介電常數介電層;一n型場效電晶體輸入/輸出區,具有位於該半導體基板上之一第四閘堆疊物,其中該第四閘堆疊物包括一介電層、位於該介電層上之一中間層、位於該中間層上之該第二材料之一上蓋層、以及位於該第二材料之該上蓋層上之一高介電常數介電層;以及一高電阻區,具有位於該半導體基板上之一第五閘堆疊物,其中該第五閘堆疊物包括一中間層、位於該中間層上之該第二材料之一上蓋層、以及位於該第二材料之該上蓋層上之一高介電常數介電層。
- 如申請專利範圍第4項所述之半導體裝置,其中該第三閘堆疊物、該第四閘堆疊物、與該第五閘堆疊物更包括該第一材料之一上蓋層,位於該第二材料之該上蓋層之上,且其中該高介電常數介電層係介於該第一材料之該上蓋層與該第二材料之該上蓋層之間。
- 如申請專利範圍第4項所述之半導體裝置,其中該第一材料包括一p型功函數之金屬或金屬氧化物,而該第二材料包括一n型功函數之金屬或金屬氧化物。
- 一種半導體裝置之製造方法,包括: 提供一半導體基板,具有用於設置一n型場效電晶體核心區、一n型場效電晶體輸入輸出區、一p型場效電晶體核心區、一p型場效電晶體輸入輸出區以及一高電阻區之複數個區域;形成一氧化物層於該些輸入輸出區內之該半導體基板之上;形成一中間層於該半導體基板與該氧化物層之上;沉積一第一材料之一上蓋層於該中間層之上;沉積一高介電常數介電層於該第一材料之該上蓋層與該中間層之上;沉積一第二材料之一上蓋層於該高介電常數介電層之上;形成一功函數金屬層於該第二材料之該上蓋層之上;沉積一多晶矽層於該功函數金屬層之上;以及形成複數個閘堆疊物於該些區域內之該半導體基板之上。
- 如申請專利範圍第7項所述之半導體裝置之製造方法,於沉積該高介電常數介電材料層之前,更包括移除該n型場效電晶體核心區、該n型場效電晶體輸入輸出區、與該高電阻區內之該第一材料之該上蓋層,以及於沉積該高介電常數介電材料層之前,更包括移除該p型場效電晶體核心區、該p型場效電晶體輸入輸出區內之該第一材料之該上蓋層。
- 如申請專利範圍第7項所述之半導體裝置之製造方法,於沉積該功函數金屬層之前,更包括移除該p型場效電晶體核心區、該p型場效電晶體輸入輸出區、該n型場效電晶體核心區、該n型場效電晶體輸入輸出區、與該高電阻區內之該第 二材料之該上蓋層。
- 如申請專利範圍第7項所述之半導體裝置之製造方法,其中該第一材料與該第二材料包括p型或n型功函數之一金屬或金屬氧化物,而該高介電常數介電層係介於該第一材料之該上蓋層與該第二材料之該上蓋層之間。
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US8698252B2 (en) | 2012-04-26 | 2014-04-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device for high-K and metal gate stacks |
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US8698252B2 (en) | 2014-04-15 |
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US20130285150A1 (en) | 2013-10-31 |
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