TWI528469B - Semiconductor package and manufacturing method thereof - Google Patents
Semiconductor package and manufacturing method thereof Download PDFInfo
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- TWI528469B TWI528469B TW103101388A TW103101388A TWI528469B TW I528469 B TWI528469 B TW I528469B TW 103101388 A TW103101388 A TW 103101388A TW 103101388 A TW103101388 A TW 103101388A TW I528469 B TWI528469 B TW I528469B
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- substrate
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- semiconductor package
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- 239000004065 semiconductor Substances 0.000 title claims description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims description 100
- 239000008393 encapsulating agent Substances 0.000 claims description 24
- 229910000679 solder Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 5
- 235000012431 wafers Nutrition 0.000 claims 15
- 239000000084 colloidal system Substances 0.000 description 3
- 239000003292 glue Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
本發明係有關於一種半導體封裝件及其製法，尤指一種具有封裝膠體的半導體封裝件及其製法。 The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a semiconductor package having an encapsulant and a method of fabricating the same.
近年來，由於各種電子產品在尺寸上是日益要求輕、薄及小，因此可節省基板平面面積並可同時兼顧處理性能之堆疊式半導體封裝件愈來愈受到重視。 In recent years, as various electronic products are increasingly required to be light, thin, and small in size, stacked semiconductor packages that can save the planar area of the substrate and simultaneously satisfy the processing performance have received increasing attention.
第1A至1D圖所示者，係為習知之半導體封裝件之製法的剖視圖。 1A to 1D are cross-sectional views showing a method of fabricating a conventional semiconductor package.
如第1A圖所示，提供具有相對之第一表面10a與第二表面10b的第一基板10，該第一表面10a具有複數第一電性連接墊101，該第一表面10a上接置有晶片11，且該第一電性連接墊101與第二表面10b上分別接置有第一銲球12a與第二銲球12b。 As shown in FIG. 1A, a first substrate 10 having a first surface 10a and a second surface 10b is provided. The first surface 10a has a plurality of first electrical connection pads 101. The first surface 10a is connected to the first surface 10a. The first solder ball 12a and the second solder ball 12b are respectively disposed on the wafer 11 and the first electrical connection pad 101 and the second surface 10b.
如第1B圖所示，於該晶片11與第一表面10a之間填充底膠13，且該底膠13亦覆蓋該第一銲球12a，接著，以雷射清除部分該底膠13，以外露該第一銲球12a。 As shown in FIG. 1B, a primer 13 is filled between the wafer 11 and the first surface 10a, and the primer 13 also covers the first solder ball 12a, and then the portion of the primer 13 is removed by laser. The first solder ball 12a is exposed.
再如第1C與1D圖所示，將具有相對之第三表面20a與第四表面20b的第二基板20接置於該第一基板10的第一表面10a上， 該第三表面20a具有複數第二電性連接墊201，各該第二電性連接墊201上設有金屬柱202，該第四表面20b上設有電子元件21，該第二電性連接墊201藉由該金屬柱202電性連接該第一銲球12a，且令該晶片11位於該第一基板10與第二基板20之間。 Further, as shown in FIGS. 1C and 1D, the second substrate 20 having the third surface 20a and the fourth surface 20b opposite to each other is placed on the first surface 10a of the first substrate 10, The second surface 20a has a plurality of second electrical connection pads 201. Each of the second electrical connection pads 201 is provided with a metal post 202. The fourth surface 20b is provided with an electronic component 21, and the second electrical connection pad. The first solder ball 12a is electrically connected to the first pillar 12a by the metal pillar 202, and the wafer 11 is located between the first substrate 10 and the second substrate 20.
由於前述半導體封裝件之製法是先對該第一基板上的晶片進行該底膠之填充，再接置該第二基板，因此，並沒有對於該金屬柱進行保護，而容易降低抗落摔能力與抗高低溫循環能力的信賴性。 Since the semiconductor package is prepared by first filling the substrate on the first substrate and then attaching the second substrate, the metal column is not protected, and the falling resistance is easily reduced. Reliability with high and low temperature cycle resistance.
請再參照第2A與2B圖，其係習知之半導體封裝件之製法的另一實施例之剖視圖，如圖所示，此製法係先將該第二基板20接置於該第一基板10的第一表面10a上，再從一側將封裝膠體30灌入至該第一基板10與第二基板20之間，以包覆該晶片11、第一銲球12a與金屬柱202。惟，此種製法因為該金屬柱之數量多且密集排列，因此在將該封裝膠體灌入時，該封裝膠體從一側邊流動至另一側邊所需的時間過久，使得在未完全填滿於該第一基板與第二基板之間之前，該封裝膠體便已凝固，導致該封裝膠體的填充失敗。 Referring again to FIGS. 2A and 2B, which are cross-sectional views of another embodiment of a conventional method of fabricating a semiconductor package, as shown, the method of first attaching the second substrate 20 to the first substrate 10 On the first surface 10a, the encapsulant 30 is further poured into the first substrate 10 and the second substrate 20 from one side to cover the wafer 11, the first solder ball 12a and the metal post 202. However, this method is because the number of the metal pillars is large and densely arranged, so when the encapsulant is poured, the time required for the encapsulant to flow from one side to the other side is too long, so that it is not completely Before encapsulating between the first substrate and the second substrate, the encapsulant has solidified, resulting in failure of filling of the encapsulant.
由於前述之半導體封裝件係設置有金屬柱，所以能縮小該第一銲球的體積，進而能符合現今細線寬線距的趨勢。但前述兩種製法都各自有其製作上之缺失，無論是抗落摔能力與抗高低溫循環能力的信賴性不佳、或者是封裝膠體易於填充失敗。 Since the foregoing semiconductor package is provided with a metal pillar, the volume of the first solder ball can be reduced, thereby conforming to the trend of the current fine line width. However, each of the above two methods has its own lack of production, whether it is the reliability of the anti-drop ability and the anti-high and low temperature cycle ability, or the encapsulation colloid is easy to fill failure.
因此，如何避免上述習知技術中之種種問題，實為目前業界所急需解決的課題。 Therefore, how to avoid various problems in the above-mentioned prior art is an urgent problem to be solved in the industry.
有鑒於上述習知技術之缺失，本發明提供一種半導體封裝件之製法，係包括：提供具有相對之第一表面與第二表面的第一基板，該第一表面具有複數第一電性連接墊，且該第一表面上接置有晶片；藉由複數導電元件將具有相對之第三表面與第四表面及貫穿該第三表面與第四表面之穿孔的第二基板接置於該第一基板的第一表面上，該第三表面具有複數第二電性連接墊，該第二電性連接墊藉由該導電元件電性連接該第一電性連接墊，且令該晶片位於該第一基板與第二基板之間；以及經由該穿孔將封裝膠體注入至該第一基板與第二基板之間，以包覆該晶片與導電元件。 In view of the above-mentioned shortcomings of the prior art, the present invention provides a method of fabricating a semiconductor package, comprising: providing a first substrate having opposing first and second surfaces, the first surface having a plurality of first electrical connection pads And the first surface is connected with the wafer; the second substrate having the opposite third surface and the fourth surface and the through holes of the third surface and the fourth surface are attached to the first substrate by the plurality of conductive elements On the first surface of the substrate, the third surface has a plurality of second electrical connection pads, and the second electrical connection pad is electrically connected to the first electrical connection pad by the conductive component, and the wafer is located at the first surface Between a substrate and the second substrate; and injecting the encapsulant between the first substrate and the second substrate via the through hole to encapsulate the wafer and the conductive member.
於前述之製法中，該穿孔係位於該晶片的上方，該穿孔係位於該第二基板之中央，且於接置該第二基板之前，復包括於該晶片與該第一基板之第一表面之間形成底膠。 In the above method, the through hole is located above the wafer, and the through hole is located at the center of the second substrate, and is included in the first surface of the wafer and the first substrate before the second substrate is attached A primer is formed between them.
於本發明之半導體封裝件之製法中，注入該封裝膠體之方式係以噴嘴為之，於注入該封裝膠體時，該噴嘴係置於該穿孔中。 In the method of fabricating a semiconductor package of the present invention, the encapsulant is injected by a nozzle, and the nozzle is placed in the perforation when the encapsulant is injected.
依前所述之半導體封裝件之製法，該穿孔之尺寸係大於該噴嘴之尺寸，且於接置該第二基板之前，該導電元件係為接置於該第二電性連接墊上的金屬柱，於接置該第二基板之前，復包括於該第一電性連接墊上接置銲球，該第二電性連接墊藉由該導電元件電性連接該銲球。 According to the method of manufacturing the semiconductor package described above, the size of the through hole is larger than the size of the nozzle, and before the second substrate is attached, the conductive element is a metal post attached to the second electrical connection pad. Before the second substrate is connected, the solder ball is connected to the first electrical connection pad, and the second electrical connection pad is electrically connected to the solder ball by the conductive component.
本發明復提供一種半導體封裝件，係包括：第一基板，係具有相對之第一表面與第二表面，該第一表面並具有複數第一電性連接墊；晶片，係接置於該第一表面上；第二基板，係藉由複數導電元件接置於該第一基板的第一表面上，該第二基板具有相對之第三表面與第四表面及貫穿該第三表面與第四表面之穿孔，該 第三表面具有複數第二電性連接墊，該第二電性連接墊藉由該導電元件電性連接該第一電性連接墊，且令該晶片位於該第一基板與第二基板之間；以及封裝膠體，係形成於該第一基板與第二基板之間，以包覆該晶片與導電元件。 The present invention further provides a semiconductor package comprising: a first substrate having opposite first and second surfaces, the first surface having a plurality of first electrical connection pads; and a wafer attached to the first substrate a second substrate disposed on the first surface of the first substrate by a plurality of conductive elements, the second substrate having opposite third and fourth surfaces and the third surface and the fourth surface Perforation of the surface, the The third surface has a plurality of second electrical connection pads. The second electrical connection pad is electrically connected to the first electrical connection pad by the conductive component, and the wafer is located between the first substrate and the second substrate. And an encapsulant formed between the first substrate and the second substrate to encapsulate the wafer and the conductive element.
於前述之半導體封裝件中，該封裝膠體復形成於該穿孔中，該穿孔係位於該晶片的上方，該穿孔係位於該第二基板之中央。 In the foregoing semiconductor package, the encapsulant is formed in the through hole, and the through hole is located above the wafer, and the through hole is located in the center of the second substrate.
依上所述之半導體封裝件，復包括底膠，係形成於該晶片與該第一基板之第一表面之間，該導電元件係為接置於該第二電性連接墊上的金屬柱，復包括銲球，係形成於該第一電性連接墊上，該第二電性連接墊藉由該導電元件電性連接該銲球。 According to the above semiconductor package, a primer is formed between the wafer and the first surface of the first substrate, and the conductive component is a metal pillar attached to the second electrical connection pad. The solder ball is formed on the first electrical connection pad, and the second electrical connection pad is electrically connected to the solder ball by the conductive component.
由上可知，本發明係能有效縮短封裝膠體的流動距離與時間，進而能縮短工時、提高產品良率與提升產品信賴度。 As can be seen from the above, the present invention can effectively shorten the flow distance and time of the encapsulant, thereby shortening the working hours, improving the product yield and improving the reliability of the product.
10、40‧‧‧第一基板 10, 40‧‧‧ first substrate
10a、40a‧‧‧第一表面 10a, 40a‧‧‧ first surface
10b、40b‧‧‧第二表面 10b, 40b‧‧‧ second surface
101、401‧‧‧第一電性連接墊 101, 401‧‧‧ first electrical connection pads
11、41‧‧‧晶片 11, 41‧‧‧ wafer
12a、42a‧‧‧第一銲球 12a, 42a‧‧‧ first solder ball
12b、42b‧‧‧第二銲球 12b, 42b‧‧‧second solder balls
20、50‧‧‧第二基板 20, 50‧‧‧ second substrate
20a、50a‧‧‧第三表面 20a, 50a‧‧‧ third surface
20b、50b‧‧‧第四表面 20b, 50b‧‧‧ fourth surface
201、501‧‧‧第二電性連接墊 201, 501‧‧‧second electrical connection pad
202‧‧‧金屬柱 202‧‧‧Metal column
21‧‧‧電子元件 21‧‧‧Electronic components
30、70‧‧‧封裝膠體 30, 70‧‧‧Package colloid
13、43‧‧‧底膠 13, 43‧‧ ‧ primer
51‧‧‧導電元件 51‧‧‧Conducting components
500‧‧‧穿孔 500‧‧‧Perforation
60‧‧‧噴嘴 60‧‧‧ nozzle
第1A至1D圖所示者係為習知之半導體封裝件之製法的剖視圖；第2A與2B圖所示者係為習知之半導體封裝件之製法的另一實施例之剖視圖；以及第3A至3D圖所示者係本發明之半導體封裝件之製法的剖視圖。 1A to 1D are cross-sectional views showing a method of fabricating a conventional semiconductor package; FIGS. 2A and 2B are cross-sectional views showing another embodiment of a conventional semiconductor package; and 3A to 3D. The figure is a cross-sectional view showing the method of fabricating the semiconductor package of the present invention.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均 僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It should be noted that the structure, proportion, size, etc. shown in the drawings of this specification are It is intended to be used in conjunction with the disclosure of the specification for the understanding and reading of those skilled in the art, and is not intended to limit the scope of the invention, and is not technically meaningful, any structural modification or proportional relationship. Changes in size or size are intended to be within the scope of the teachings disclosed herein without departing from the scope of the invention. In the meantime, the terms used in this specification are for convenience of description only, and are not intended to limit the scope of the invention, and the relative relationship changes or adjustments are also considered as The scope of the invention can be implemented.
第3A至3D圖所示者，係本發明之半導體封裝件之製法的剖視圖。 3A to 3D are cross-sectional views showing a method of fabricating the semiconductor package of the present invention.
首先，如第3A圖所示，提供具有相對之第一表面40a與第二表面40b的第一基板40，該第一表面40a具有複數第一電性連接墊401，且該第一電性連接墊401與第二表面40b上分別接置有第一銲球42a與第二銲球42b，並於該第一表面40a上接置晶片41，於該晶片41與該第一基板40之第一表面40a之間形成底膠43；該底膠43與第一銲球42a係視需要而設置。 First, as shown in FIG. 3A, a first substrate 40 having a first surface 40a and a second surface 40b opposite to each other is provided. The first surface 40a has a plurality of first electrical connection pads 401, and the first electrical connection A first solder ball 42a and a second solder ball 42b are respectively disposed on the pad 401 and the second surface 40b, and the wafer 41 is attached to the first surface 40a, and the wafer 41 and the first substrate 40 are first. A primer 43 is formed between the surfaces 40a; the primer 43 and the first solder balls 42a are disposed as needed.
如第3B圖所示，藉由複數導電元件51將具有相對之第三表面50a與第四表面50b及貫穿該第三表面50a與第四表面50b之穿孔500的第二基板50接置於該第一基板40的第一表面40a上，該穿孔500係位於該晶片41的上方，該穿孔500係位於該第二基板50之中央，該第三表面50a具有複數第二電性連接墊501，該第二電性連接墊501藉由該導電元件51電性連接該第一電性連接墊401，且令該晶片41位於該第一基板40與第二基板50之間。 As shown in FIG. 3B, the second substrate 50 having the third surface 50a and the fourth surface 50b opposite to each other and the through holes 500 penetrating the third surface 50a and the fourth surface 50b is interposed by the plurality of conductive members 51. The first surface 40a of the first substrate 40 is disposed above the wafer 41. The through hole 500 is located at the center of the second substrate 50. The third surface 50a has a plurality of second electrical connection pads 501. The second electrical connection pad 501 is electrically connected to the first electrical connection pad 401 by the conductive component 51 , and the wafer 41 is located between the first substrate 40 and the second substrate 50 .
於本實施例中，該導電元件51係為接置於該第二電性連接墊 501上的金屬柱，該第二電性連接墊501藉由該金屬柱電性連接該第一銲球42a。 In this embodiment, the conductive element 51 is connected to the second electrical connection pad. The second electrical connection pad 501 is electrically connected to the first solder ball 42a by the metal post.
如第3C至3D圖所示，將噴嘴60置於該穿孔500中，該穿孔500之尺寸係大於該噴嘴60之尺寸，並藉由噴嘴60經由該穿孔500將封裝膠體70注入至該第一基板40與第二基板50之間，以包覆該晶片41與導電元件51。 As shown in FIGS. 3C to 3D, the nozzle 60 is placed in the perforation 500, the perforation 500 is sized larger than the size of the nozzle 60, and the encapsulant 70 is injected into the first via the perforation 500 by the nozzle 60. The substrate 40 and the second substrate 50 are wrapped to cover the wafer 41 and the conductive member 51.
本發明復提供一種半導體封裝件，係包括：第一基板40，係具有相對之第一表面40a與第二表面40b，該第一表面40a並具有複數第一電性連接墊401；晶片41，係接置於該第一表面40a上；第二基板50，係藉由複數導電元件51接置於該第一基板40的第一表面40a上，該第二基板50具有相對之第三表面50a與第四表面50b及貫穿該第三表面50a與第四表面50b之穿孔500，該第三表面50a具有複數第二電性連接墊501，該第二電性連接墊501藉由該導電元件51電性連接該第一電性連接墊401，且令該晶片41位於該第一基板40與第二基板50之間；以及封裝膠體70，係形成於該第一基板40與第二基板50之間，以包覆該晶片41與導電元件51。 The present invention further provides a semiconductor package, comprising: a first substrate 40 having a first surface 40a and a second surface 40b opposite to each other, the first surface 40a having a plurality of first electrical connection pads 401; The second substrate 50 is attached to the first surface 40a of the first substrate 40 by a plurality of conductive elements 51 having a third surface 50a opposite to the first surface 40a. And the fourth surface 50b and the through hole 500 penetrating the third surface 50a and the fourth surface 50b, the third surface 50a has a plurality of second electrical connection pads 501, and the second electrical connection pads 501 are provided by the conductive elements 51. The first electrical connection pad 401 is electrically connected to the first substrate 40 and the second substrate 50; and the encapsulant 70 is formed on the first substrate 40 and the second substrate 50. To cover the wafer 41 and the conductive member 51.
前述之半導體封裝件中，該封裝膠體70復形成於該穿孔500中，該穿孔500係位於該晶片41的上方，且該穿孔500係位於該第二基板50之中央。 In the foregoing semiconductor package, the encapsulant 70 is formed in the through hole 500. The through hole 500 is located above the wafer 41, and the through hole 500 is located in the center of the second substrate 50.
依前所述之半導體封裝件，復包括底膠43，係形成於該晶片41與該第一基板40之第一表面40a之間，該導電元件51係為接置於該第二電性連接墊501上的金屬柱。 The semiconductor package according to the foregoing includes a primer 43 formed between the wafer 41 and the first surface 40a of the first substrate 40. The conductive component 51 is connected to the second electrical connection. A metal post on the mat 501.
綜上所述，相較於習知技術，本發明之灌膠起始點係位於第 二基板中間的穿孔處，因此能縮短封裝膠體至多一半的流動距離與時間，使得封裝膠體可在凝固前完整包覆導電元件，進而達到縮短工時、提高產品良率與提升產品信賴度之目的。 In summary, the starting point of the glue filling of the present invention is located in comparison with the prior art. The perforation in the middle of the two substrates can shorten the flow distance and time of the encapsulant at most half, so that the encapsulant can completely cover the conductive components before solidification, thereby achieving the purpose of shortening working hours, improving product yield and improving product reliability. .
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
40‧‧‧第一基板 40‧‧‧First substrate
40a‧‧‧第一表面 40a‧‧‧ first surface
40b‧‧‧第二表面 40b‧‧‧ second surface
401‧‧‧第一電性連接墊 401‧‧‧First electrical connection pad
41‧‧‧晶片 41‧‧‧ wafer
42a‧‧‧第一銲球 42a‧‧‧First solder ball
42b‧‧‧第二銲球 42b‧‧‧second solder ball
50‧‧‧第二基板 50‧‧‧second substrate
50a‧‧‧第三表面 50a‧‧‧ third surface
50b‧‧‧第四表面 50b‧‧‧ fourth surface
501‧‧‧第二電性連接墊 501‧‧‧Second electrical connection pad
70‧‧‧封裝膠體 70‧‧‧Package colloid
43‧‧‧底膠 43‧‧‧Bottom glue
51‧‧‧導電元件 51‧‧‧Conducting components
500‧‧‧穿孔 500‧‧‧Perforation
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| TW103101388A TWI528469B (en) | 2014-01-15 | 2014-01-15 | Semiconductor package and manufacturing method thereof |
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| TWI595603B (en) * | 2016-11-10 | 2017-08-11 | 矽品精密工業股份有限公司 | Package stack structure |
| CN110060961B (en) * | 2018-01-19 | 2021-07-09 | 华为技术有限公司 | Wafer packaging device |
| CN112420526B (en) * | 2019-08-20 | 2024-07-02 | 江苏长电科技股份有限公司 | Double-substrate laminated structure and packaging method thereof |
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