CN101266933A - Method for making semiconductor device and bearing part using this method - Google Patents
Method for making semiconductor device and bearing part using this method Download PDFInfo
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- CN101266933A CN101266933A CNA2007101359897A CN200710135989A CN101266933A CN 101266933 A CN101266933 A CN 101266933A CN A2007101359897 A CNA2007101359897 A CN A2007101359897A CN 200710135989 A CN200710135989 A CN 200710135989A CN 101266933 A CN101266933 A CN 101266933A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention discloses a manufacturing method of a semiconductor device and a bearing assembly used therein, comprising: placing a substrate embedded with a chip into an opening of a bearing assembly, the bearing part is formed with at least a store hole and a inspection hole, wherein the store hole can be used for injecting compound to fill the internals between the substrate and the bearing part via the capillary phenomenon, in order to judge whether the intervals between the substrate and the bearing part are completely filled with the compound via observing whether the inspection hole is filled with the compound; after completely filled with the compound, carrying out mould-pressing process to form a package colloid for coating the chip; then carrying out ball mounting process and cutting process in order to form expected semiconductor device. Via the inspection hole, the user can inspect whether the intervals between the substrate and the bearing part are completely filled with the compound with naked eyes; meanwhile, the costs for inspection process can be reduced, and the yield rate of product can be increased without increasing the package costs.
Description
Technical field
The present invention relates to a kind of manufacture of semiconductor, particularly relate to a kind of method for making of semiconductor device and be used for the bearing part of this method for making.
Background technology
Tradition is covered geode grid array formula (Flip-Chip Ball Grid Array, FCBGA) semiconductor package part, mainly include a substrate, be electrically connected to the chip of this upper surface of base plate and plant in this base lower surface to cover crystal type, to be electrically connected to extraneous a plurality of soldered balls, simultaneously, this packaging part comprises that again one is formed at this upper surface of base plate and coats the packing colloid of this chip by the mold pressing processing procedure.Relevant as United States Patent (USP) the 6th, 038,136,6,444,498,6,699,731 and 6,830, prior aries such as No. 957 have all disclosed approximate encapsulating structure.
Processing procedure such as United States Patent (USP) the 6th about this crystal covering type ball grid array (FCBGA) semiconductor package part, 830, No. 957 disclose, mainly be respectively to extend a clamped areas Clamp Area) in the length and width outer rim of substrate, make the cavity dimension of the size of substrate greater than dies with epoxy compound, cause this substrate can be mould institute clamping, make this colloid can overflow to the back side of this substrate, undermine solder ball pad (Ball Pad) weldability in order to plant soldered ball on the substrate; Yet this design has caused the increase of substrate size and has made the overall package cost greatly promote (the substrate cost that covers brilliant usefulness generally all accounts for more than 60% of packaging part cost).Moreover, because after the mold pressing processing procedure finishes, for peel of mould can be finished the demoulding (Releasing) step smoothly, must mat die cavity shape and make the packing colloid edge on this substrate form a draft angle, with the convenient demoulding, generally speaking, this draft angle can not be greater than 60., there is preferable stripping result the side, similarly for the packing colloid that forms this draft angle must increase extra substrate size, not only forms the waste of substrate utilance (Utilization), more will make whole cost rise about 15 ~ 20%.
Therefore, for ball grid array (BGA) semiconductor package, this problem shows and to have formed facing a difficult choice on the processing procedure, the mold pressing processing procedure that forms packing colloid is the steps necessary in the packaging part preparation in fact, but this step will make substrate size and material cost increase, and be unfavorable for volume production on the industry, obviously become the developmental bottleneck of ball grid array (BGA) semiconductor package.
See also Figure 1A to Fig. 1 D, in view of this, TaiWan, China patent I244145 and disclose a kind of method for producing semiconductor packaging part (applicant of described patent and the present patent application physiognomy with) for I244707 number, it comprises a plurality of substrates 10 of preparation and a bearing part 16, the rough predetermined length and width size that equals semiconductor package part of the length and width size of this substrate 10, and be provided with at least one chip 11 on each substrate 10, have a plurality of openings 160 on this bearing part 16, and the length and width size of this opening 160 is greater than the length and width size of this substrate 10, so that these a plurality of substrates 10 are positioned respectively in the opening 160 of this bearing part, the gap 17 that while this substrate 10 of capping and this bearing part are 16, and make this this bearing part 16 (shown in Figure 1A) of gap 17 unlikely perforations; Carry out the mold pressing processing procedure, to form the packing colloid 13 in order to coat this chip 11 respectively on each opening 160, wherein, the length and width size of 13 area coverages of this packing colloid is greater than the length and width size (shown in Figure 1B) of this opening 160; And then after the demoulding, plant soldered ball 12 (shown in Fig. 1 C) in these substrate 10 back sides, and the rough marginal position along this substrate 10 cuts (shown in Fig. 1 D) according to the predetermined length and width size of this semiconductor package part, to make a plurality of semiconductor package parts.Thereby the gap 17 by 16 of capping substrate 10 and this bearing parts is to prevent the excessive glue of packing colloid 13, simultaneously, order in order to the projection length and width size of the die cavity that forms this packing colloid 13 greater than the length and width size of this opening 160 with the convenient demoulding; So, can avoid prior art for solving the shortcoming that the problems such as the glue and the demoulding of overflowing increase these substrate 10 sizes, and then can significantly dwindle the preparation size of this substrate 10, and make the rough preliminary dimension that equals packaging part of its preparation length and width size, reduce the unnecessary baseplate material waste in cutting back.
But, in aforementioned processing procedure, for effectively locating this substrate 10 and this gap 17 of capping, it discloses in a glue mode sizing material 18 that macromolecular materials such as solder flux (Solder Mask) or epoxy resin are for example refused in the gap 27 of 16 of this substrate 10 and bearing parts filling one, and be a glue operation that can accelerate, usually 1mm at least need be reserved in this gap 17, write (pen-write) mode fast in these gap 17 filling sizing materials 18 for a glue operation, but gap 17 is bigger, required sizing material 18 consumptions promptly the more cause cost to rise; Simultaneously, if the glutinous in advance substrate 10 generation skews (shift) that place on the film are also caused in gap 17 too greatly easily, even cause the successive process puzzlement, for example because of substrate 10 skews, cause gap, relative both sides difference, and then cause one side sizing material to fill out discontented, and excessive glue problem (shown in Fig. 2 A) takes place in another side relatively, even corresponding to one side that excessive glue takes place, when follow-up formation covers the packing colloid 13 of chip 11, to cause 10 of packing colloid 13 and substrates sizing material 18 (shown in Fig. 2 B) to be arranged, and the edge delamination problems will take place easily because of residual.Relatively, too little as this gap 17, offset problem takes place though can reduce substrate 10, but must use thinner some plastic pin and slower some glue speed, the side is fully filled in this gap 17 sizing material 18, so will cause a glue speed slow excessively, causes the rising of cost simultaneously.
Other sees also Fig. 3, for solving foregoing problems, applicant of the present invention proposes a kind of method for making of semiconductor package part at TaiWan, China number of patent application the 95133420th, it is provided with the substrate 20 of chip 21, be accommodated in the opening 260 of a bearing part 26, because this opening 260 is slightly larger than substrate 20 sizes, 26 of this substrate 20 and bearing parts are formed with a gap S, can be the filling fully of sizing material institute for making this gap S enough little with the consumption of sizing material and before molding operation carries out to save filling, and form at least one storage hole 261 in the periphery of the opening 260 of this bearing part 26, thereby when carrying out a some glue operation, allow sizing material C inject this storage hole 261 earlier, make the sizing material stored in the hole 261 can mat capillarity and be filled among the gap S of 26 of substrate 20 and bearing parts.
And be to make the sizing material that injects in this storage hole mat capillarity be fills up to the gap, the width in this gap promptly should be preferably 0.1mm between 0.05 to 0.2mm.These width decapacitation provide the generation of capillarity and save outside the consumption of sizing material, can also avoid excesssive gap and have substrate to fail accurately to be positioned problem in the opening.But very little because of the gap, desire judges whether the gap is that sizing material fills up fully, often can't detect with naked eyes, and must use the microscope of 30x to detect.The step that this detects with microscope not only increases the complexity of processing procedure, also increases the overall package cost simultaneously; And if do not adopt microscope to detect clearance filled integrality, can cause when the gap is not filled with sizing material fully, in mold pressing processing procedure (Molding Process) carries out, have packing colloid (Molding Compound) and be not filled with sizing material place spill and leakage pollutes solder ball pad (ball pad) to substrate back problem from the gap, even influence the yield of manufactured goods.
Therefore, how a kind of method for making of semiconductor device is provided and is used for the bearing part of this method for making, and needn't use microscope promptly can carry out the inspection method whether gap is filled with sizing material fully rapidly by naked eyes, thereby when avoiding existing between semiconductor device and bearing part the gap not to be filled with sizing material fully, packing colloid is not filled with the problem of sizing material place spill and leakage to substrate back from the gap in the mold pressing processing procedure, pollute solder ball pad (ball pad) and influence the yield of manufactured goods, reality is a present related industry institute problem demanding prompt solution.
Summary of the invention
In view of this, a purpose of the present invention provides a kind of method for making of semiconductor device and is used for the bearing part of this method for making, needn't microscopical use and whether the gap that can detect rapidly between semiconductor device and bearing part with naked eyes is filled with sizing material fully.
Another object of the present invention provides a kind of method for making of semiconductor device and is used for the bearing part of this method for making, detects cost and process complexity thereby can reduce.
A further object of the present invention provides a kind of method for making of semiconductor device and is used for the bearing part of this method for making, thereby can detect under the condition of cost not increasing, and guarantees that the gap between semiconductor device and bearing part is able to complete filling.
For reaching above-mentioned and other purpose, the invention provides a kind of method for making of semiconductor device, it comprises the following steps: and will connect in the opening that the substrate that is equipped with chip is arranged at a bearing part, make between this substrate and bearing part the gap that forms a width that tool is desired, and the opening periphery of this bearing part and be formed with at least one storage hole and at least one hole that detects; Sizing material inject is stored the hole, so that this sizing material can mat capillarity and be filled into this gap and detect in the hole; Inspect this and detect whether be filled with sizing material in the hole,, then enter next step if having; Carry out molding operation on this substrate and bearing part, to form one in order to coat this chip and to cover the packing colloid that covers this opening; And, cut single job (Singulation Process) to form the semiconductor device of being desired.This chip mainly is to connect and put and be electrically connected to this substrate to cover crystal type.
What this detected the hole is provided with position and quantity, and those skilled in the art all know and there is no specific limited.Certainly, quantity is many more, can judge more accurately more whether formed gap is filled with sizing material fully between substrate and bearing part.Simultaneously, this size and shape that detects the hole does not also have specific limited, its shape can be semicircle, rectangle, triangle or Else Rule or irregular person, its size then is preferably 3 to 10 times of gap width, that is, its radius or length and width size must be positioned between 0.5 to 2mm scope, and are advisable with 1mm, with the waste of avoiding sizing material but can not judge whether sizing material is inserted for naked eyes again simultaneously with hindering.
The present invention also provides the bearing part of using on a kind of method for making of above-mentioned semiconductor device, and this bearing part is a slice body structure, has at least one opening that runs through, and is formed at least one storage hole of opening periphery, and at least one hole that detects that is formed at this opening periphery.
Description of drawings
Figure 1A to Fig. 1 D is TaiWan, China patent I244145 and the method for producing semiconductor packaging part that disclosed for I244707 number;
Fig. 2 A and Fig. 2 B are prior art is met with substrate orientation in bearing part filler problem cutaway view;
The method for making schematic diagram of the semiconductor package part that Fig. 3 is proposed in TaiWan, China number of patent application the 95133420th for the present patent application people;
Fig. 4 A to Fig. 4 H is the method for making schematic diagram of semiconductor device of the present invention; And
Fig. 5 to Fig. 9 is the different embodiment schematic diagrames of bearing part that are used for the method for making of semiconductor device of the present invention.
The component symbol explanation
10 substrates, 11 chips
12 soldered balls, 13 packing colloids
16 bearing parts, 160 openings
17 gaps, 18 sizing materials
20 substrates, 21 chips
26 bearing parts, 260 bearing part openings
261 store hole C sizing material
40 chips, 41 welding blocks
42 substrates, 420 substrate backs
421 solder ball pads, 43 bearing parts
The 430 bearing part back sides, 431 bearing part openings
432 store hole 433 detects the hole
44 packing colloids, 45 soldered balls
46 films, 53 bearing parts
533 detect hole 63 bearing parts
631 bearing part openings 632 are stored the hole
633 detect hole 73 bearing parts
731 bearing parts are opened 732 and are stored the hole
733 detect hole 83 bearing parts
831 bearing parts are opened 832 and are stored the hole
833 detect hole 93 bearing parts
931 bearing parts are opened 933 and are detected the hole
Embodiment
Below, understand advantage of the present invention and effect easily by the content that this specification disclosed for those skilled in the art by specific instantiation explanation embodiments of the present invention.
Notice, the present invention is for solving the defective of above-mentioned TaiWan, China number of patent application 95133420 applications for a patent for invention, so being described in detail of identical parts, material or step will slightly remove so that this specification is more succinct.
This specification described " one " is not the quantity in order to " thing " that limits its binding, and is meant that " one " reaches the quantity of " more than one "; So, if " thing " quantity of indication is non-when having only one, then can clearly limit so that " many " are individual in full, again if only can have only one the time, also can be clearly with " one " or the qualification of reciprocity speech.
See also Fig. 4 A to Fig. 4 H, be method for making flow process (step) schematic diagram of semiconductor device of the present invention.
Shown in Fig. 4 A, welding block (Solder Bumps) 41 welderings that a chip 40 is located on this chip 40 by a plurality of welderings are located on the substrate 42, this chip 40 can be electrically connected via welding block 41 and substrate 42.This kind chip is a prior art with the technology of covering the electric connection of crystalline substance (Flip Chip) mode and substrate, and non-characteristics of the present invention place, so do not repeat them here.This chip also can be selected to be electrically connected to this substrate in the bonding wire mode in addition.
Shown in Fig. 4 B and Fig. 4 C, this Fig. 4 C vertical view that is corresponding diagram 4B wherein, provide one by FR4, FR5, BT or the similar made bearing part 43 of macromolecular material, on the back side 430 of this bearing part 43, paste a film (Tape) 46 and run through opening 431 1 ports that are formed at this bearing part 43 with involution one, thereby when being positioned over this substrate 42 that is equipped with chip 40 in this opening 431, this substrate 42 can place opening 431 by this film 46.
The opening 431 of this bearing part 43 is square, in four corners of this opening 431 and be formed with and store hole 432, multiple periphery in this opening 431 be formed with the semicircular in shape of storing hole 432 spaced apart one suitable distances detect hole 433.This opening 431 is slightly larger than substrate 42, thereby, after this substrate 42 is inserted opening 431, it is formed with a gap S 43 of this substrate 42 and bearing parts, and making this gap S have the width of being desired, the capillarity streamer that can provide because of gap S in order to the sizing material of this gap of filling S (being specified in the back) with order is therebetween; The width of this gap S is preferably about 0.1mm, and this gap S is with this storage hole 432 and detect hole 433 and be connected.
This storage hole 432 is injected sizing material for general point glue equipment, and the suitable size of storing hole 432 can make sizing material more promptly fill in, and needn't use the point glue equipment of expensive and fine Glue dripping head, so can reduce cost and make the processing procedure acceleration.Relatively, whether fully this detect hole 433 and only be provided with bore hole and inspect the gap S usefulness of filling sizing material, so its size is can not be too big and make capillarity interrupt and/or increase the consumption of sizing material, also can not be too little and cause inspecting this and detect hole 433 and whether be filled with sizing material with bore hole; Be with, this detects the neglecting shape greatly of hole 433 and decides, its radius or long limit are preferably about 1mm, make this detect hole 433 usually less than storage hole 432.
Shown in Fig. 4 D, for example to put the glue mode sizing material C is injected this storage hole 432, inject (direction flows shown in the figure arrow) between the S of gap thereby this sizing material C can be flowed by the capillarity that gap S is provided, and when detecting hole 433, also can inject and detect hole 433 in stimulating the menstrual flow.Thereby, being filled among the S of gap by this sizing material C, this substrate 42 can firmly be positioned in the bearing part 43.Simultaneously, this sizing material C is generally macromolecular materials such as refusing solder flux (Solder Mask) or epoxy resin.
Shown in Fig. 4 E, then promptly can bore hole etc. mode inspect easily and detect hole 433 and whether be filled with sizing material C, avoid using microscope to detect complexity and increase overall package cost that institute causes increasing processing procedure.If no sizing material C filling is in detecting hole 433, represent that promptly gap S does not tamp fully for sizing material C, then must not carry out follow-up encapsulation procedure, with the waste of avoiding material and the increase of fraction defective; If inspecting the result has been filled with sizing material C for detecting hole 433, expression gap S is filled with sizing material C fully, and can enter next processing procedure.
Shown in Fig. 4 F, carry out molding operation, to form a packing colloid 44 on the bearing part 43 that is combined with substrate 42 in this.The floor space of this packing colloid 44 is greater than this opening 431, so that this packing colloid 44 completely covers substrate 42, meets the chip 40 and the gap S that place on this substrate 42.Because this gap S has been the filling fully of sizing material C institute, as previously mentioned, so in molding operation carries out, packing colloid 44 unlikely leakage glue are to the back side 420 of substrate 42 and cause the pollution of solder ball pad set on the back side 420 of substrate 42 (Ball Pads) 421, therefore, can guarantee the welding quality of soldered ball (will be shown in Fig. 4 G) and solder ball pad 421.Then, this film 46 is removed.
Shown in Fig. 4 G, plant ball operation (Solder Ball ImplantationProcess), a plurality of soldered balls 45 being planted on the back side 420 that is connected to substrate 42 corresponding solder ball pad 421, thereby make this soldered ball 45 of chip 40 mats form electrical connection with external device.
At last, shown in Fig. 4 H, cut single job (Singulation Process),, desired the semiconductor device 4 of size to form in order to cut this packing colloid 44 and substrate 42 along the line of cut on the substrate 42 (not shown).Notice is aforesaidly planted the ball operation and also must be given enforcement again after cutting single job and finishing, and there is no specific limited and plants the ball operation and must carry out before cutting single job, and aforesaid enforcement order only is an illustrative, but but not in order to limit practical range of the present invention.
See also Fig. 5 to Fig. 9 again, different embodiment for the bearing part of the method for making that is used for semiconductor device of the present invention, the different embodiment of mat present, be provided with position, relative position relation and the quantity that formed storage hole on the bearing part that the present invention is suitable for are described and detect the hole there is no specific limited, whether but this detects the hole and is preferably the centre position of being located at adjacent storage hole, fill and be distributed in the gap effectively to inspect colloid.
As shown in Figure 5, this bearing part is different from the difference place of employee in the previous embodiment, is that the hole 533 that detects of this bearing part 53 is square, and has isometric side, respectively is 1mm in this embodiment.
As shown in Figure 6, this bearing part 63 is different from the difference place of employee in the previous embodiment, is that two store holes 632 and are formed on the two relative angle corners of bearing part opening 631, and two detect hole 633 then is formed on the two relative corners in addition of opening 631.
As shown in Figure 7, the bearing part 73 of present embodiment is different from the difference place of employee in the previous embodiment, is to store hole 732 through taking up an official post between two adjacent angular corners in the periphery of opening 731, and is relative, detects the four corner places that hole 733 then is formed at opening 731 respectively.
As shown in Figure 8, the bearing part 83 of present embodiment is different from the difference place of employee in the previous embodiment, be to detect the middle place that hole 833 is formed at two corresponding edges of opening 831, storage hole 832 then is formed at the roughly middle place of two opposed edges in addition of opening 831, and this storage hole 832 exists in paired mode.
As shown in Figure 9, the bearing part 93 of present embodiment is different from the difference place of employee in the previous embodiment, be that the formed hole 933 that detects exists in paired mode on arbitrary side of this bearing part opening 931, this increase that detects hole 933 quantity can make and detect effect promoting.
Thereby, by the explanation of previous embodiment as can be known, the method for making of semiconductor device of the present invention and be applied to bearing part in this method for making, because of the formation that detects the hole is arranged, make the gap that detects between substrate and bearing part whether be the operation of sizing material institute complete filling, detect with bore hole and to get final product, and needn't be by as aids such as microscopes, so complexity and the deadline that can reduce packaging cost and processing procedure, even when avoiding existing between semiconductor device and bearing part the gap not to be filled with sizing material fully, packing colloid is not filled with the problem of sizing material place spill and leakage to substrate back from the gap in the mold pressing processing procedure, pollutes solder ball pad (ball pad) and influences problem such as manufactured goods yield.
The foregoing description is illustrative principle of the present invention and effect thereof only, but not is used to limit the present invention.Any those skilled in the art all can be under spirit of the present invention and category, and the foregoing description is modified and changed.Therefore, the scope of the present invention should be foundation with the scope of claims of the present invention.
Claims (15)
1. the method for making of a semiconductor device comprises the following steps:
To connect in the opening that the substrate that is equipped with chip is arranged at a bearing part, this opening is slightly larger than this substrate, forming a gap between this substrate and bearing part, and is formed with at least one storage hole and at least one and this storage span is opened detects the hole at the periphery of opening;
Sizing material is injected this storage hole, with by the capillarity that this gap was provided, make the sizing material filling in the gap and detect in the hole, and inspect this and detect whether be filled with sizing material in the hole;
Form a packing colloid to cover whole parts that reach bearing part in chip, substrate and gap; And
Cut this packing colloid and substrate to form the semiconductor device of a size that tool is desired.
2. method for making according to claim 1, wherein, this storage hole dimension detects hole dimension greater than this.
3. method for making according to claim 1, wherein, this detects the radius in hole or width that long limit is about the gap 3 to 10 times.
4. method for making according to claim 1, wherein, this detects corner or side that the hole is formed at this opening.
5. method for making according to claim 1, wherein, this radius or long limit that detects the hole is about 0.15 to 2.0mm, and is advisable with 1.0mm.
6. method for making according to claim 1 wherein, detects the centre position that adjacent storage hole is located in the hole.
7. method for making according to claim 1, wherein, this chip is electrically connected to this substrate to cover crystal type.
8. method for making according to claim 1, wherein, this sizing material is selected from refuses wherein one of solder flux and epoxy resin.
9. method for making according to claim 1, wherein, this sizing material in order to substrate orientation in the opening of bearing part, and make the gap between this substrate and bearing part be the filling fully of this sizing material institute.
10. method for making according to claim 1 comprises again and plants the ball operation, carries out before or after this cutting operation, so that many soldered ball welderings are established to the back side of this substrate.
11. a bearing part that is used to make semiconductor device, this bearing part is a slice body structure, comprising:
At least one opening;
Storage hole at least one periphery that is formed at this opening; And
Detect the hole at least one periphery that is formed at this opening, wherein, this storage hole detects the hole greater than this, and this detects the hole and this storage span is opened.
12. bearing part according to claim 11, wherein, this radius or long limit that detects the hole is about 0.15 to 2.0mm, and is advisable with 1.0mm.
13. bearing part according to claim 11, wherein, this detects the centre position that adjacent storage hole is located in the hole.
14. bearing part according to claim 11, wherein, this detects the hole and is formed on the corner or side of this opening.
15. bearing part according to claim 11, wherein, this opening is in order to ccontaining semiconductor device, and be formed with the gap between this semiconductor device and this bearing part opening, inject this storage hole for sizing material, and, make the sizing material filling in the gap and detect in the hole by the capillarity that this gap provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101359897A CN101266933A (en) | 2007-03-14 | 2007-03-14 | Method for making semiconductor device and bearing part using this method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101359897A CN101266933A (en) | 2007-03-14 | 2007-03-14 | Method for making semiconductor device and bearing part using this method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101266933A true CN101266933A (en) | 2008-09-17 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007101359897A Pending CN101266933A (en) | 2007-03-14 | 2007-03-14 | Method for making semiconductor device and bearing part using this method |
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| Country | Link |
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| CN (1) | CN101266933A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101964311A (en) * | 2009-07-08 | 2011-02-02 | 台湾积体电路制造股份有限公司 | Method of forming integrated circuit and integrated circuit structure |
| CN104779175A (en) * | 2014-01-15 | 2015-07-15 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
-
2007
- 2007-03-14 CN CNA2007101359897A patent/CN101266933A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101964311A (en) * | 2009-07-08 | 2011-02-02 | 台湾积体电路制造股份有限公司 | Method of forming integrated circuit and integrated circuit structure |
| CN101964311B (en) * | 2009-07-08 | 2014-03-12 | 台湾积体电路制造股份有限公司 | Method of forming integrated circuit and integrated circuit structure |
| CN104779175A (en) * | 2014-01-15 | 2015-07-15 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
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