TWI527030B - 用於自我刷新模式之記憶體裝置控制 - Google Patents

用於自我刷新模式之記憶體裝置控制 Download PDF

Info

Publication number
TWI527030B
TWI527030B TW099108749A TW99108749A TWI527030B TW I527030 B TWI527030 B TW I527030B TW 099108749 A TW099108749 A TW 099108749A TW 99108749 A TW99108749 A TW 99108749A TW I527030 B TWI527030 B TW I527030B
Authority
TW
Taiwan
Prior art keywords
cke
power
power module
memory controller
memory
Prior art date
Application number
TW099108749A
Other languages
English (en)
Chinese (zh)
Other versions
TW201044391A (en
Inventor
達美舒庫瑪Ｎ 巴哈塔
約翰Ｃ 克里茲
艾瑞克Ｄ 波森
Original Assignee
安華高科技通用Ｉｐ（新加坡）公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 安華高科技通用Ｉｐ（新加坡）公司 filed Critical 安華高科技通用Ｉｐ（新加坡）公司
Publication of TW201044391A publication Critical patent/TW201044391A/zh
Application granted granted Critical
Publication of TWI527030B publication Critical patent/TWI527030B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G06F1/3225—Monitoring of peripheral devices of memory devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G11C5/144—Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4067—Refresh in standby or low power modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Power Sources (AREA)
TW099108749A 2009-04-29 2010-03-24 用於自我刷新模式之記憶體裝置控制 TWI527030B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/431,876 US7869300B2 (en) 2009-04-29 2009-04-29 Memory device control for self-refresh mode

Publications (2)

Publication Number Publication Date
TW201044391A TW201044391A (en) 2010-12-16
TWI527030B true TWI527030B (zh) 2016-03-21

Family

ID=42226108

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099108749A TWI527030B (zh) 2009-04-29 2010-03-24 用於自我刷新模式之記憶體裝置控制

Country Status (6)

Country Link
US (1) US7869300B2 (https=)
EP (1) EP2246769A1 (https=)
JP (1) JP5590605B2 (https=)
KR (1) KR20100118950A (https=)
CN (1) CN101882464B (https=)
TW (1) TWI527030B (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8942056B2 (en) * 2011-02-23 2015-01-27 Rambus Inc. Protocol for memory power-mode control
US9159397B2 (en) 2012-12-04 2015-10-13 Micron Technology, Inc. Methods and apparatuses for refreshing memory
JP2014146115A (ja) * 2013-01-28 2014-08-14 Canon Inc データ処理装置およびその制御方法
US10055370B2 (en) * 2014-07-09 2018-08-21 Advanced Micro Devices, Inc. Method and apparatis for processor standby
US9142280B1 (en) 2014-08-06 2015-09-22 Freescale Semiconducotr, Inc. Circuit for configuring external memory
CA3034395A1 (en) * 2015-08-24 2017-03-02 Src Labs, Llc System and method for retaining dram data when reprogramming reconfigurable devices with dram memory controllers incorporating a data maintenance block colocated with a memory module or subsystem
JP6516630B2 (ja) * 2015-08-26 2019-05-22 キヤノン株式会社 メモリ制御回路及びその制御方法
KR102535182B1 (ko) 2016-07-27 2023-05-23 에스케이하이닉스 주식회사 반도체 장치
US11176986B2 (en) * 2019-12-30 2021-11-16 Advanced Micro Devices, Inc. Memory context restore, reduction of boot time of a system on a chip by reducing double data rate memory training
TWI897241B (zh) * 2024-02-19 2025-09-11 華邦電子股份有限公司 記憶體儲存裝置及其操作方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5831467A (en) * 1991-11-05 1998-11-03 Monolithic System Technology, Inc. Termination circuit with power-down mode for use in circuit module architecture
US6564329B1 (en) * 1999-03-16 2003-05-13 Linkup Systems Corporation System and method for dynamic clock generation
US6829677B1 (en) * 2000-05-18 2004-12-07 International Business Machines Corporation Method and apparatus for preserving the contents of synchronous DRAM through system reset
TW588235B (en) * 2001-04-02 2004-05-21 Via Tech Inc Motherboard with less power consumption
JP3799251B2 (ja) * 2001-08-24 2006-07-19 エルピーダメモリ株式会社 メモリデバイス及びメモリシステム
KR100502664B1 (ko) * 2003-04-29 2005-07-20 주식회사 하이닉스반도체 온 다이 터미네이션 모드 전환 회로 및 그방법
KR100529033B1 (ko) * 2003-05-23 2005-11-17 주식회사 하이닉스반도체 동기식 반도체 메모리 소자
KR100528164B1 (ko) * 2004-02-13 2005-11-15 주식회사 하이닉스반도체 반도체 기억 소자에서의 온 다이 터미네이션 모드 전환회로 및 그 방법
JP4298610B2 (ja) * 2004-08-31 2009-07-22 キヤノン株式会社 データ記憶装置
US7164611B2 (en) * 2004-10-26 2007-01-16 Micron Technology, Inc. Data retention kill function
JP4775141B2 (ja) * 2005-09-29 2011-09-21 株式会社ハイニックスセミコンダクター 遅延固定ループ回路
DE102006036822A1 (de) * 2006-08-07 2008-02-14 Qimonda Ag Verfahren zum Betrieb eines Speichermoduls und Speichermodul
KR100866601B1 (ko) * 2006-12-04 2008-11-03 삼성전자주식회사 반도체 장치의 종단 저항을 제어할 수 있는 장치 및 방법
JP2008217890A (ja) * 2007-03-02 2008-09-18 Ricoh Co Ltd 電子装置、画像処理装置及び電源供給制御方法
US7729191B2 (en) * 2007-09-06 2010-06-01 Micron Technology, Inc. Memory device command decoding system and memory device and processor-based system using same
JP5200692B2 (ja) * 2007-09-14 2013-06-05 株式会社リコー データ処理装置、データ処理装置の電圧制御方法及び画像形成装置
US7715264B2 (en) * 2008-06-24 2010-05-11 Qimonda North America Corp. Method and apparatus for selectively disabling termination circuitry

Also Published As

Publication number Publication date
JP5590605B2 (ja) 2014-09-17
US7869300B2 (en) 2011-01-11
JP2010262645A (ja) 2010-11-18
CN101882464A (zh) 2010-11-10
US20100278000A1 (en) 2010-11-04
CN101882464B (zh) 2013-10-30
TW201044391A (en) 2010-12-16
EP2246769A1 (en) 2010-11-03
KR20100118950A (ko) 2010-11-08

Similar Documents

Publication Publication Date Title
TWI527030B (zh) 用於自我刷新模式之記憶體裝置控制
US8879348B2 (en) Power management in semiconductor memory system
US11221774B2 (en) Power down mode for universal flash storage (UFS)
CN104681071B (zh) 半导体存储器件及其i/o控制电路
US7886103B2 (en) Input-output module, processing platform and method for extending a memory interface for input-output operations
CN107667326B (zh) 双存储器平台中的功率管理
US9305613B2 (en) Reconfigurable load-reduced memory buffer
CN104571442A (zh) 一种基于power平台的内存板上电时序的控制方法
JP2012507933A (ja) 差動式オンライン終端
TW200823922A (en) Deep power down mode control circuit
CN108962333B (zh) 包括电源门控电路的半导体装置及其修复方法
US8139433B2 (en) Memory device control for self-refresh mode
US7484027B1 (en) Apparatus and method for configurable device pins
CN104516684A (zh) 数据处理装置、微型控制器、以及半导体装置
CN103092783A (zh) 内存控制器以及内存系统
CN109427372B (zh) 动态存储器离线和电压定标
US7733709B2 (en) Semiconductor memory device with internal voltage generating circuit and method for operating the same
TW201405298A (zh) 記憶體裝置及其控制方法
CN102930897B (zh) 电压产生器
US9063714B1 (en) Detecting startup fault of SDRAM voltage regulator
TW200933354A (en) Multi-regulator power delivery system for ASIC cores
CN106205723A (zh) 半导体装置和驱动其的方法
CN221746872U (zh) 一种ddr5 ckd udimm内存模组
CN103885866B (zh) 时间延迟参数可调转接卡
CN110633227B (zh) 内存重置电路及应用所述内存重置电路的主板

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees