TWI524480B - Cof package having improved heat dissipation - Google Patents

Description

Thin film flip chip package with improved heat dissipation

The present invention claims to apply for the South Korean Patent No. 10-2012-0014340 filed on February 13, 2012, and the South Korean Patent No. 10-2012-0014341, filed on February 13, 2012. The South Korean Patent No. 10-2012-0014342, the Korean Patent No. 10-2012-0014343 filed on February 13, 2012, and the South Korean Patent No. 10-2012-0029837 filed on February 23, 2012 are preferred. This is incorporated herein by reference.

The present invention relates to thin film flip chip (COF) packages, and more particularly to thin film flip chip packages having improved heat dissipation.

The use of tape-type wiring substrates has increased in the field of semiconductor wafer mounting technology, as semiconductor devices have recently been characterized by relatively small and small size, high density integration, high speed, and multiple pins. The tape-type wiring substrate has a wiring pattern and a structure in which a lead wire connecting the wiring pattern is formed on the film, and the film is composed of an insulating material such as polyimide resin and the like. A tape automated bonding (TAB) technique for bonding a bump pre-formed on a semiconductor wafer to a wire with a wiring substrate in a lump can be applied to a tape wiring substrate. Due to this characteristic, the tape-type wiring substrate is referred to as a TAB tape. Further, there is a tape carrier package (TCP) as an example of a tape-type wiring substrate and a semiconductor package to which the tape carrier package is applied.

However, due to lower cost, fine pitch, flexibility, and the ability to carry passive components, driver ICs using glass flip-chip (COG) packages and thin film flip-chip (COF) packages are available in large TFT-LCD panels. The ratio has increased.

Therefore, the market demand for driver ICs with COG and COF packages has been increase.

1 is a structural view showing a COF package according to a conventional technique.

As illustrated in FIG. 1 , the structure of the COF package includes: a polyimide film 110; an adhesive layer 120 on one surface of the polyimide film 110; a metal layer 130 on the adhesive layer 120; and a solder resist layer 140 And disposed on the metal layer 130. The metal layer 130 is changed to the circuit pattern layer 130 via an etching process. The IC wafer 160 is bonded to the circuit pattern layer 130 via a metal bump 150 as a bonding pad. Further, the molding unit 170 for fixing and protecting the IC wafer 160 may be formed using a resin and the like.

In this structure of the COF package, the circuit pattern layer 130 is surrounded by the polyimide film 110 and the solder resist layer 140, and the IC wafer 160 is also molded by the molding unit 170. Therefore, the heat dissipation capability of the COF package structure is very low.

Incidentally, the ratio of driver ICs using glass flip-chip (COG) packages and film flip-chip (COF) packages in large TFT-LCD panels has increased. Since the frame frequency, the driving voltage, and the higher display channel are required for the TFT-LCD panel, the heat dissipation capability of the driver IC has become more and more important.

Therefore, as the market demand for driver ICs with COG and COF packages has increased, there has been a need to improve the heat dissipation capability in COF package structures.

The present invention has been made in view of the problems occurring in the above-described prior art. . The invention provides a thin film flip chip package with excellent heat dissipation capability.

According to an aspect of the invention, a thin film flip chip package includes: an insulating layer on which a via for thermal radiation is formed, and the insulating layer includes a wafer mounting region; and a circuit unit is located in the insulating layer On one surface of the layer; an IC chip electrically connected to the circuit unit and mounted in the wafer mounting region; and a dummy pattern unit located on a same layer as the circuit unit to correspond to the wafer mounting region, wherein The through hole is formed to correspond to the dummy pattern unit.

In the display device, since the demand for a driver IC in which a COF package is employed has increased, there is a need to improve the heat dissipation capability in the structure of the COF package.

According to the present invention, because of the electricity used to radiate the circuit unit mounted on the insulating layer The thermal dummy pattern unit of the sub-circuit wafer is included in the same layer as the circuit unit, and a via hole for exposing the dummy pattern unit to the outside is formed on the insulating layer, so that heat generated from the COF package is efficiently radiated to Externally, it is possible to prevent the semiconductor wafer from being improperly operated or damaged due to overheating. That is, the present invention effectively reduces the failure rate due to the heat of the IC wafer by lowering the temperature of the wafer.

110‧‧‧ Polyimine film

120‧‧‧Adhesive layer

130‧‧‧metal layer/circuit pattern layer

140‧‧‧solder layer

150‧‧‧Metal bumps

160‧‧‧ IC chip

200‧‧‧ Tape Carrier Package

204‧‧‧ wafer mounting area

210‧‧‧Insulation

212‧‧‧through hole

215‧‧ ‧ seed layer

230‧‧‧ circuit unit

233‧‧‧Power Endpoints

235‧‧‧Electroplating

240‧‧‧virtual pattern unit

242‧‧‧Extension

244‧‧‧ Connection unit

250‧‧‧ solder mask

260‧‧‧ IC chip

262‧‧‧Bumps

265‧‧‧Molding unit

270‧‧‧Seal unit / thermal radiation plating unit

274‧‧‧Thermal/thermal radiation layer

280‧‧‧Wire/adhesive layer

285‧‧‧Heat cushion unit

312‧‧‧through hole

314‧‧‧through hole

340‧‧‧Virtual pattern unit

342‧‧‧Extension

350‧‧‧Virtual pattern unit

360‧‧‧metal patch unit

402‧‧‧Tetragonal

410‧‧‧Insulation

412‧‧‧through hole

430‧‧‧ circuit unit

440‧‧‧Virtual pattern unit

1 is a block diagram showing a COF package according to the prior art.

2 is a front elevational view of a tape carrier package in accordance with an exemplary embodiment of the present invention.

3 is a cross-sectional view of the COF package of FIG. 2.

4 is a front elevational view of a COF package in accordance with an exemplary embodiment of the present invention.

FIG. 5 is a front elevational view of a COF package in accordance with another exemplary embodiment of the present invention. FIG.

6 is a front elevational view of a COF package in accordance with another exemplary embodiment of the present invention.

7 is a front elevation and cross-sectional view showing a COF package in accordance with another exemplary embodiment of the present invention.

Figure 8 is a cross-sectional view showing a COF package in accordance with another exemplary embodiment of the present invention.

Figure 9 is a configuration diagram showing the mounting of the wafer in the COF package of Figure 8.

Figure 10 is a front elevational view of a COF package in accordance with another exemplary embodiment of the present invention.

Figure 11 is an enlarged front elevational view of a COF package in accordance with yet another exemplary embodiment of the present invention.

12 through 15 are each cross-sectional view showing a COF package in accordance with the embodied shape of the present invention.

Exemplary embodiments in accordance with the present invention will now be described more fully hereinafter with reference to the accompanying drawings. However, the exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, the exemplary embodiments are provided so that this invention will be in the Further, when it is determined that a specific description about a related function or configuration known to the public may not necessarily be related to the gist of the present invention, the corresponding description is omitted. In addition, each element in the diagram can be enlarged for convenience of description. The size, which does not reflect the actual size of the corresponding component.

2 is a front elevational view of a tape carrier package in accordance with an exemplary embodiment of the present invention.

Referring to FIG. 2, a tape carrier 200, which is a semiconductor device, includes an insulating layer 210 made of a film. The insulating layer 210 is formed using a film having a thickness of 10 μm to 25 μm so as to have flexibility bending ability. However, the thickness of the insulating layer 210 is not limited thereto. It can be determined that the thickness is within a range that is generally apparent to those skilled in the art. For example, the insulating layer 210 may be formed of a polyimide-based resin. The insulating layer 210 may be cut such that a plurality of IC wafers (i.e., a plurality of light emitting devices) mounted on the insulating layer are separated from each other. In other words, the insulating layer 210 is formed in a strip type, and the COF packages are disposed at regular intervals along the length direction.

Specifically, after the metal layer is formed on the insulating layer 210, the circuit unit 230 is formed by patterning the metal layer. An IC chip (light emitting device) is mounted in the wafer mounting region 204. In this case, the wiring of the circuit unit 230 is electrically connected to the end point corresponding to the IC chip. According to the present invention, the dummy pattern unit 240 is formed, and heat generated from the IC wafer when the circuit unit 230 is formed is transferred to the dummy pattern unit 240. The dummy pattern unit 240 is formed while performing a process of patterning the metal layer. Thereafter, the insulating layer 210 is cut to separate the COF packages from each other. Referring to Figure 3, the configuration of a COF package will be explained.

3 is a cross-sectional view of the COF package of FIG. 2.

Referring to FIG. 3, the COF package includes: an insulating layer 210 on which a via hole 212 for radiant heat is formed; a circuit unit 230 formed on one surface of the insulating layer 210; and a dummy pattern unit 240 formed in and The circuit unit 230 is on the same layer. Also, the COF package may include a solder resist layer and an IC wafer. The IC chip is electrically connected to the circuit unit 230. The IC chip can be a light emitting device such as an LED.

A through hole 212 for radiant heat is formed on the insulating layer 210. The dummy pattern unit 240 is positioned to correspond to the IC wafer and to receive and radiate heat generated from the IC wafer. According to an example embodiment, the dummy pattern unit 240 may be formed by patterning a metal layer on which the circuit unit 230 is patterned.

The via 212 can be formed by etching a portion of the insulating layer 210 with a laser. through The hole 212 is formed on the insulating layer such that the dummy pattern unit 240 is exposed to the outside. Specifically, in the COF package, the dummy pattern unit 240 for radiating heat of the IC wafer is formed on the same layer as the circuit unit 230. Also, the dummy pattern unit 240 is located between the IC wafer and the via 212 for radiant heat. Therefore, heat generated from the IC wafer is transferred to the dummy pattern unit 240 and is distributed via the via 212.

According to an exemplary embodiment, since the dummy pattern unit 240 is positioned to correspond to the IC wafer, the via 212 may be formed to correspond to a region in which the IC wafer is mounted in the insulating layer. According to another exemplary embodiment, the via 212 may be formed outside the region of the insulating layer 210 where the IC chip is mounted. In this case, the dummy pattern unit 240 is formed to correspond to a region in which the IC wafer is mounted and extends to the outside of the region. Therefore, the via 212 is formed to correspond to the dummy pattern unit 240 that extends to the outside of the wafer mounting region.

The dummy pattern unit 240 may be formed on the insulating layer 210 simultaneously with the circuit unit 230. Specifically, the circuit unit 230 is formed by forming a metal layer on the insulating layer 210 and then performing an etching process on the metal layer. At this time, the metal layer is etched by including a pattern of the dummy pattern unit 240 for heat radiation and the circuit unit 230. Since the dummy pattern unit 240 is made of a metal layer on which circuit units are formed, it has a high thermal conductivity.

According to an example embodiment, the dummy pattern unit 240 is selectively and physically connectable to the circuit unit 230. In this case, the heat generated from the circuit unit 230 is transferred to the dummy pattern unit 240. According to another example embodiment, the dummy pattern unit 240 may include a connection unit (not drawn) that extends from the dummy pattern unit and is connected to the circuit unit 230.

Therefore, heat generated from the IC chip or circuit unit 230 is transferred to the dummy pattern unit 240. This heat is radiated via the dummy pattern unit 240. Also, the heat is radiated to the outside via the via 212, and the via 212 is formed to be connected to the dummy pattern unit 240.

4 is a front elevational view of a COF package in accordance with another exemplary embodiment of the present invention.

Referring to Figure 4, one portion of the insulating layer is enlarged and exemplified. An IC wafer (not drawn) is mounted into the wafer mounting area 204. The circuit unit 230 is formed on the insulating layer 210. Further, the dummy pattern unit 240 is formed on the same layer as the circuit unit 230. As depicted, the dummy pattern unit 240 is formed to correspond to the wafer mounting region 204. Also, according to an exemplary embodiment, a virtual map The file unit 240 extends to the outside of the wafer mounting area 204. The via 212 can be formed to correspond to the extended portion 242 of the dummy pattern 240 that extends outside of the wafer mounting region 204. In Figure 4, the vias 212 are shown in dashed lines.

The extended portion 242 of the dummy pattern unit 240 that extends to the exterior of the wafer mounting region 204 can be formed in any portion of the dummy pattern unit 240 that is positioned to correspond to the wafer mounting region 204. In other words, the extended portion 242 of the dummy pattern unit 240 extending to the outside of the wafer mounting region 204 may be formed in any portion of the insulating layer 210 on which the circuit unit 230 is not formed.

Also, in the present exemplary embodiment, one virtual pattern unit 240 is included, but the present invention is not limited thereto. For example, the circuit unit 230 and the plurality of dummy pattern units 240 may be included on the insulating layer 210.

In the present exemplary embodiment, a through hole 212 for dissipating heat is formed on the insulating layer 210. However, a plurality of through holes can be formed. For example, some of the plurality of vias may be formed in the wafer mounting region 204, and other vias may be formed in the exterior of the wafer mounting region 204. Even under any condition, one or more through holes should be formed to be connected to the dummy pattern unit 240. The number of vias 212 can be determined based on various conditions, such as the design of the circuit pattern and the like.

FIG. 5 is a front elevational view of a COF package in accordance with another exemplary embodiment of the present invention. FIG.

Referring to Figure 5, one portion of the insulating layer is enlarged and exemplified. Regarding FIG. 5, an explanation about the same configuration as the COF package illustrated in FIG. 4 will be omitted.

Referring to FIG. 5, the dummy pattern unit 340 is formed to correspond to the wafer mounting region 204. Also, according to the present exemplary embodiment, the dummy pattern unit 340 extends to the outside of the wafer mounting region 204. Specifically, the dummy pattern unit 340 extends between the plurality of leads of the circuit unit 230. That is, the dummy pattern unit 340 has the extended portion 342 in a portion in which the circuit unit 230 is not formed. One or more through holes 312 are formed in the extended portion 342.

As shown, the through hole 312 is indicated by a broken line. The via may be formed to correspond to the extended portion 342 of the dummy pattern unit 340 that extends to the outside of the wafer mounting region 204. The number of through holes 312 may be according to the size and shape of the through holes or the size of the extended portion 342 of the dummy pattern unit. And the shape changes.

In this case, heat generated from the IC wafer mounted in the wafer mounting region 204 is transferred to a portion of the dummy pattern unit 340 corresponding to the wafer mounting region 204, and then transferred to the extended portion 342 of the dummy pattern unit 340. This heat is radiated to the outside via the through hole 312 corresponding to the extended portion 342 of the dummy pattern unit 340. According to another example embodiment, the vias 312 may be formed to correspond to portions of the dummy pattern cells 240 that are positioned on the wafer mounting region 204.

6 is a front elevational view of a COF package in accordance with another exemplary embodiment of the present invention.

Referring to Figure 6, a portion of the insulating layer is enlarged and exemplified. An IC chip (not shown) is mounted in the wafer mounting area (204). The circuit unit 230 is formed on the insulating layer 210. Also, the dummy pattern unit 350 is formed on the same layer as the circuit unit 230. In the present exemplary embodiment, the COF package is illustrated as including two dummy pattern units 350. However, the invention is not limited thereto.

As depicted, the dummy pattern unit 350 is formed to correspond to the wafer mounting region 204. Also, the dummy pattern unit 350 is formed to be connected to the power supply terminals of the circuit unit 230, respectively. The power supply terminal of circuit unit 230 is the endpoint that receives power. When power is supplied, the power terminals may overheat. Therefore, in a state where the dummy pattern unit 350 is respectively connected to the power source terminal of the circuit unit 230, the dummy pattern unit 350 can receive heat from the power source terminal of the circuit unit 230 when the power source terminal is overheated with the supply of power.

Further, the vias 314 are formed to correspond to the dummy pattern unit 350, respectively. In the present exemplary embodiment, one through hole 314 is formed for one dummy pattern unit 350, but the present invention is not limited thereto. The number of vias 314 for one dummy pattern unit 350 may vary depending on the size and shape of the vias or the size and shape of the dummy pattern unit 350.

Also, in the present exemplary embodiment, the dummy pattern unit 350 is formed to correspond to the power source terminal 233 of the circuit unit 230, respectively. However, the invention is not limited thereto. A dummy pattern unit can be connected to all or selective power terminals 233 of circuit unit 230.

7 is a front elevational view of a COF package in accordance with another exemplary embodiment of the present invention.

Referring to Figure 7, a portion of the insulating layer is enlarged and exemplified. IC chip (not shown) Mounted in the wafer mounting area 204. The circuit unit 230 is formed on the insulating layer 210. Further, a plurality of dummy pattern units 240 are formed on the same layer as the circuit unit 230. In the present exemplary embodiment, the COF package is illustrated to include four dummy pattern units 240. However, the invention is not limited thereto. For example, one virtual pattern unit 240 can be formed. In this case, the dummy pattern unit may have a larger size than the dummy pattern unit 240 illustrated in FIG. Also, as illustrated, the dummy pattern unit 240 is formed to correspond to the wafer mounting region 204.

Further, the vias 212 are formed to correspond to the dummy pattern unit 240, respectively. In the present exemplary embodiment, one through hole 212 is formed for one dummy pattern unit 240, but the present invention is not limited thereto. The number of vias 212 for one dummy pattern unit 240 may vary depending on the size and shape of the vias or the size and shape of the dummy pattern unit 240.

Therefore, heat generated from the IC wafer mounted in the wafer mounting region 204 is transferred to the dummy pattern unit 240 corresponding to the wafer mounting region 204. Then, the heat is radiated to the outside via the via 212, and the via 212 is formed to correspond to the dummy pattern unit 240.

In (b) of Fig. 7, a cross section of the COF package cut along the line A-A' of Fig. 7(a) will be described. As illustrated, to improve the effect of heat being dissipated to the outside via the vias 212, a thermal strip 274 is formed on the other or back surface of the insulating layer 210 to correspond to the vias 212 using a metal strip or paste.

The thermal layer 274 may be formed on the insulating layer 210 by adhering a metal strip to the back surface of the insulating layer 210 or applying a metal paste to the back surface of the insulating layer 210 so as to correspond to the via 212. Unlike this, the thermal layer 274 can be formed by plating the back surface of the insulating layer 210 with a metal.

When the IC wafer placed in the wafer mounting region 204 generates heat, the thermal layer 274 quickly receives heat through the via 212 and dissipates the heat to the outside. Therefore, the COF package is prevented from overheating.

Figure 8 is a cross-sectional view showing a COF package in accordance with another exemplary embodiment of the present invention.

According to the present exemplary embodiment, the COF package includes: an insulating layer 210 on which a via hole 212 for heat radiation is formed; a circuit unit 230 formed on one surface of the insulating layer 210; and a dummy pattern unit 240 formed On the same layer as circuit unit 230; and metal patch unit 360, which is formed to correspond to via 212 for thermal radiation. That is, COF package The piece includes a metal patch unit 360 that is positioned to contact the dummy pattern unit 240 that is exposed to the outside via the via 212. The metal patch unit 360 receives heat transferred from the IC wafer or circuit unit to the dummy pattern unit 240 and radiates heat to the outside. This dummy pattern unit 240 may be formed of a metal, preferably Cu.

Moreover, the metal patch unit 360 is formed to abut against the dummy pattern unit 240 to be in contact with a portion of the dummy pattern unit 240, wherein the dummy pattern unit 240 is exposed to the outside through the through hole 212, and is also formed. On the wall of the through hole 212. In this case, according to an exemplary embodiment, the metal patch unit 360 may be formed to extend from the portion formed on the wall of the through hole to the other surface of the insulating layer 210. According to another example embodiment, the metal patch unit 360 may be formed on the wall of the via 212, but may not extend to the insulating layer 210. The metal patch unit 360 may be formed to be in contact only with a portion of the wall of the through hole 212.

Metal patch unit 360 may be formed from a fin material. According to an exemplary embodiment, the metal patch unit 360 may be formed by plating a wall of the via 212 with a metal and a portion of the dummy pattern unit 240 exposed to the outside via a through hole 212 having a metal. According to another exemplary embodiment, the metal patch unit 360 may be formed of a tape or paste for heat radiation. In this case, the tape or paste is pressed toward the through hole 212 on the other surface of the insulating layer 210, and thus its shape may be changed according to the shape of the through hole 212.

Therefore, in the COF package, heat generated from the IC chip or the circuit unit 230 is mainly absorbed to the dummy pattern unit, and heat from the dummy pattern unit 240 is quickly transferred to the metal patch unit 360 and efficiently radiated to the outside. Therefore, the semiconductor wafer can be prevented from being improperly operated or damaged due to overheating.

Figure 9 is a configuration diagram showing the mounting of the wafer in the COF package of Figure 8.

Referring to FIG. 9, the COF package includes: an insulating layer 210 on which a via hole 212 for heat radiation is formed; a circuit unit 230 formed on one surface of the insulating layer 210; and a dummy pattern unit 240 formed in and The circuit unit 230 is on the same layer; a metal chip unit 360 is formed to correspond to the via 212; the IC wafer 260; and a sealing unit 270 for molding the IC wafer 260.

The IC chip 260 is connected to the circuit unit 230 via a wire 280. Also, the IC wafer 260 is connected to the dummy pattern unit 240 via the bumps 262. According to another exemplary embodiment, an IC The wafer 360 may be mounted into the circuit unit 330 to be in direct contact with the dummy pattern unit 340.

The heat generated from the IC wafer 260 may be transferred to the dummy pattern unit 240 via the bumps 262 or by the air in the space between the IC wafer 260 and the dummy pattern unit 240.

As described above, the metal patch unit 360 is formed on a portion of the dummy pattern unit 240 to be in contact with a portion of the dummy pattern unit 240 that is exposed to the outside via the through hole 212. Therefore, the metal patch unit 360 receives the heat transmitted from the IC wafer 260 or the circuit unit 230 to the dummy pattern unit 240 and radiates heat to the outside. The dummy pattern unit 240 may be formed of a metal, preferably copper.

Specifically, since the via 212 is formed to correspond to the dummy pattern unit 240, one side of the via 212 is blocked by the dummy pattern unit 240. The metal chip unit 360 is formed on the wall of the through hole 212 and abuts against the dummy pattern unit 240 and is also formed on a portion of the dummy pattern unit 240. The portion of the dummy pattern unit 240 is exposed through the through hole 212. Externally. In this case, according to an exemplary embodiment, the metal patch unit 360 may extend from the portion formed on the wall of the through hole 212 to the other surface of the insulating layer 210. According to another exemplary embodiment, the metal patch unit 360 may be formed on the wall of the via 212, but may not extend to the other surface of the insulating layer 210. As such, since the metal patch unit 360 is formed along the wall of the through hole 212, the metal patch unit 360 has a shape similar to the through hole 212. Of course, the metal patch unit 360 may be formed to be in contact only with a portion of the wall surface of the through hole 212.

Figure 10 is a front elevational view of a COF package in accordance with another exemplary embodiment of the present invention.

Referring to FIG. 10, the circuit unit 230 and the plurality of dummy pattern units 240 are formed on the insulating layer 210. A plurality of dummy pattern units 240 are positioned within an area 204 in which the IC wafer is mounted. Further, a plurality of through holes 212 are formed in positions corresponding to the plurality of dummy pattern units 240. In the drawings, this is indicated by a broken line. Preferably, the size of the through hole 212 is smaller than the size of the dummy pattern unit 240. The shape of the through hole 212 may be similar to the shape of the dummy pattern unit 240. However, the invention is not limited thereto. The size of the through hole 212 may be larger than the size of the corresponding dummy pattern unit 240.

Referring to (a) of FIG. 10, the dummy pattern unit 240 may include a connection unit 244 that extends from the dummy pattern unit and is physically connected to the circuit unit 230. In this case In this case, the end point of the circuit unit 230 connected to the dummy pattern unit 240 may be a power source terminal that receives power. As described above, since the power supply terminal receives power, the power supply terminal quickly overheats when power is supplied. According to another exemplary embodiment of the present invention, when the power supply terminal of the circuit unit 230 is connected to the dummy pattern unit 240, the heat of the power source terminal can be prevented from being overheated by the dummy pattern unit 240.

Unlike this, as illustrated in (b) of FIG. 10, the dummy pattern unit 440 may be physically spaced from the circuit unit 430. When the dummy pattern unit 240 is connected to the circuit unit 230 via the connection unit 244, the heat generated from the circuit unit 230 can be more efficiently transmitted to the dummy pattern unit 240.

Accordingly, heat generated from an IC chip (not shown) mounted in the wafer mounting region 204 is transferred to the dummy pattern unit 240 positioned directly below the IC wafer. Then, the heat may be radiated to the outside again via the through holes 212 for heat radiation, and the through holes 212 are formed to be connected to the dummy pattern unit 240. Specifically, the dummy pattern unit 240 is heated by the heat generated from the IC wafer. The heat of the dummy pattern unit 240 is radiated to the outside via the through hole 212 for exposing the dummy pattern unit 240. Therefore, the heat radiation of the COF package can be easily performed.

11 is a front elevational view of a COF package in accordance with another exemplary embodiment of the present invention.

Referring to FIG. 11, a circuit unit 430 and a dummy pattern unit 440 are formed on the insulating layer 410. The through hole 412 is formed directly under the dummy pattern unit 440 and is indicated by a broken line in the drawing. Again, quadrilateral 402 includes virtual pattern unit 440 while also including a portion of circuit unit 430 and is shown in dashed lines, which represents the area in which IC wafer 460 will be mounted.

As illustrated, a plurality of vias 412 may be formed in the mounting area of the dummy pattern unit 440, as shown in (a) of FIG. 11, according to an example. According to another example, a through hole 412 can be formed as shown in (b) of FIG. The number of vias 412 can be determined based on various conditions, such as the design of the circuit pattern. 12 through 15 are each cross-sectional view showing a COF package in accordance with the embodiment of the present invention.

The COF package illustrated in FIG. 12 includes: an insulating layer 210 on which a via hole 212 for heat radiation is formed; and a circuit unit formed on one surface of the insulating layer 210; A dummy pattern unit 240, which is formed on the same layer as the circuit unit 230; a solder resist layer 250; an IC wafer 260; and a molding unit 265 for molding the IC wafer.

The circuit unit 230 and the dummy pattern unit 240 are positioned on one surface of the insulating layer 210. The circuit unit 230 and the dummy pattern unit 240 may be simultaneously formed. The circuit unit 230 and the dummy pattern unit 240 are formed by patterning a metal layer on one surface of the insulating layer 210 and thereafter patterning the metal layer according to the pattern of the circuit unit 230 and the dummy pattern unit 240. For example, after the metal layer is formed on one surface of the insulating layer 210, an etching process may be formed on the metal layer to form the circuit unit 230 and the dummy pattern unit 240. The metal layer can be formed by applying copper to the insulating layer 210. Hereinafter, the circuit unit 230 and the dummy pattern unit 240 may be mentioned together as one metal layer.

The solder resist layer 250 is formed by being applied to the circuit unit 230. The solder resist layer 250 covers the circuit unit 230 so that an unexpected connection is not caused due to soldering performed when the component is mounted. In addition, the COF package includes a seed layer 215 between the insulating layer 210 and the metal layers 230, 240. The seed layer 215 is formed of an alloy of Ni and Cr. In this case, the Cr content in the alloy should be at least greater than 1%. Preferably, the Cr content in the alloy of Ni and Cr may be greater than 5% and may also be as high as 20%. The seed layer 215 is formed by applying an alloy of Ni and Cr to one surface of the circuit unit 230 on which the insulating layer is to be formed. In this case, the via hole 212 for heat radiation is formed after the seed layer 215 is applied to the insulating layer 210. The through hole 212 can be formed by a laser or a punching tool. In this case, a hole corresponding to the via hole 212 of the insulating layer 210 is also formed on the seed layer 215. That is, the via hole 212 is formed on the insulating layer 210 using a single process, and the hole corresponding to the via hole 212 is formed on the seed layer 215. The seed layer 215 bonds the circuit unit 230 and the dummy pattern unit 240 to the insulating layer 210.

In addition, the COF package includes a plating layer 235 that is plated with metal on the metal layers 230, 240. Preferably, the metal is Sn. The plating layer 235 is produced by surface treatment on the metal layers 230, 240, so that the connection with the IC wafer 260 is easily performed. The plating layer 235 may be formed of any one of nickel (Ni), palladium (Pd), gold (Au), and silver (Ag), and tin (Sn).

The IC chip 260 can be mounted on the circuit unit 230. In this case, the IC wafer 260 can be connected to the circuit unit 230 via the bumps 262.

Referring to Figure 13, a COF package in accordance with another example embodiment is illustrated. The COF package illustrated in FIG. 13 has a configuration similar to that of the COF package illustrated in FIG. 12 except for the thermal radiation plating unit 270 formed on the through hole.

As described above, in the case where the COF package includes the seed layer 215, since the via hole 212 for heat radiation is formed after the seed layer 215 is applied to the insulating layer 210, it corresponds to the pass of the insulating layer 210. Holes of the holes 212 are also formed on the seed layer 215. The heat radiation plating unit 270 can be formed by plating a hole formed in the seed layer 215 with a metal. The heat radiation plating unit 270 is bound by the dummy pattern unit 240 formed on the seed layer 215 to correspond to the through hole 212 of the insulating layer 210. Accordingly, the thermal radiation plating unit 270 can receive heat from the circuit unit 230 or the IC wafer via the dummy pattern unit 240. Since the heat radiation plating unit 270 is formed of a metal having high thermal conductivity, such as tin (Sn), the heat radiation plating unit 270 can well receive heat from the dummy pattern unit 240. The heat transmitted from the dummy pattern unit 240 to the heat radiation plating unit 270 is radiated to the outside via the through holes 212 formed on the insulating layer 210. Due to this configuration, heat generated from the COF package can be effectively radiated to the outside.

Referring to Figure 14, a COF package in accordance with another exemplary embodiment of the present invention is illustrated. The COF package illustrated in FIG. 14 has a configuration similar to that of the COF package illustrated in FIG. 13 except for the thermal pad unit 285 formed on the via 212.

The thermal pad unit 285 is formed on the other surface opposite to one surface of the circuit unit in which the insulating layer 210 is formed. Specifically, the thermal pad unit 285 is bonded to the other surface of the insulating layer 210 via the adhesive layer 280 to correspond to the through hole 212 of the insulating layer 210.

The thermal pad unit 285 may be formed of a metal having high thermal conductivity similar to that of the thermal radiation plating unit 270. Thermal radiation is transmitted via vias 212 to a thermal pad unit 285 that is positioned to correspond to vias 212. The thermal pad unit 285 absorbs heat transferred through the vias 212, thereby preventing overheating of the COF package.

Referring to Figure 15, a COF package in accordance with yet another exemplary embodiment of the present invention is illustrated. The COF package illustrated in FIG. 15 has a configuration similar to that of the COF package illustrated in FIG. 12, except for the heat radiation layer 274 formed on the back surface of the insulating layer.

As described above, the thermal layer 274 is positioned on the other surface of the insulating layer 210, wherein the circuit unit 230 is formed on one surface of the insulating layer 210. Thermal layer 274 can be used by A radiant heat metal strip is bonded to the other surface of the insulating layer 210 or a metal paste is applied to the other surface. In contrast, the thermal layer 274 can be formed by plating the other surface of the insulating layer 210 with a metal. When the heat is transferred from the IC wafer mounted in the wafer mounting region via the via hole 212, the thermal layer 274 absorbs heat from the via hole 212 and radiates heat to the outside. Therefore, the IC chip is prevented from being overheated.

As such, according to the present invention, since the COF package is configured such that the hot dummy pattern unit for radiating the circuit wafer mounted on the insulating circuit unit is included in the same layer as the dummy pattern unit, and is used for The via hole exposed to the outside of the pattern unit is formed on the insulating layer, so heat generated from the COF package can be efficiently radiated to the outside, thereby preventing the semiconductor wafer from being improperly operated or damaged due to overheating.

The detailed description of the present invention has been described by the embodiments of the present invention, and the invention may be modified and changed without departing from the spirit and scope of the invention. Therefore, the present invention is to be understood as being limited to the specific embodiments disclosed, and the modifications of the disclosed embodiments and other embodiments are intended to be included in the scope of the appended claims and their equivalents. Within the scope.

204‧‧‧ wafer mounting area

210‧‧‧Insulation

212‧‧‧through hole

230‧‧‧ circuit unit

240‧‧‧virtual pattern unit

242‧‧‧Extended part

Claims (19)

A film flip chip (COF) package comprising: an insulating layer on which a via for heat radiation is formed, and the insulating layer includes a wafer mounting region; and a circuit unit located in the insulating layer An IC chip electrically connected to the circuit unit and mounted in the wafer mounting region; and at least one dummy pattern unit located on a same layer as the circuit unit to correspond to the wafer mounting region and having A portion extends to the exterior of the wafer mounting region, wherein the via is formed to correspond to the dummy pattern unit. The film flip chip package of claim 1, wherein the extension portion extends between the plurality of leads of the circuit unit. The thin film flip chip package of claim 1, wherein the circuit unit has at least one power supply terminal, the power supply terminal receives power, and the virtual pattern unit is connected to the power supply end point. The film flip chip package of claim 1, further comprising a metal patch unit located on a portion of the dummy pattern unit exposed through the through hole. The film flip chip package of claim 4, wherein the metal patch unit is formed of copper. The film flip chip package of claim 4, wherein the metal patch unit is formed on one of the walls of the through hole. The film flip chip package of claim 6, wherein the metal patch unit extends from a portion of the wall formed on the through hole to the other surface of the insulating layer. The film flip chip package of claim 1, wherein the insulating layer is embodied by a polyimide film. The film flip chip package of claim 1, wherein the dummy pattern unit is formed simultaneously with the circuit unit. The film flip chip package according to claim 1, further comprising a seed layer, A seed layer is located between the insulating layer and the circuit unit, and the circuit unit is bonded to the insulating layer. The film flip chip package of claim 1, wherein the seed layer comprises a hole corresponding to the through hole formed on the insulating layer. The film flip chip package of claim 11, further comprising a heat radiation plating unit formed by electroplating the hole of the seed layer with a metal. The film flip chip package of claim 1, further comprising a solder resist layer on the circuit unit for preventing soldering of the circuit unit. The film flip chip package of claim 13, further comprising a plating layer between the circuit unit and the solder resist layer, and plating the circuit unit. The film flip chip package of claim 1, further comprising a thermal pad unit bonded to the other surface of the insulating layer to correspond to the through hole. The film flip chip package of claim 1, wherein the dummy pattern unit is connected to the circuit unit. The film flip chip package of claim 1, wherein the dummy pattern unit comprises a connection unit extending from the dummy pattern unit and connected to the circuit unit. The film flip chip package of claim 1, wherein the through hole has a smaller size than the dummy pattern unit. The film flip chip package of claim 1, further comprising a thermal layer formed on the other surface of the insulating layer and receiving heat.