TWI523113B - Method of manufacturing semiconductor device having metal gate - Google Patents

Description

Semiconductor component having metal gates

The present invention relates to a method of fabricating a semiconductor device having a metal gate.

In the conventional semiconductor industry, polycrystalline lanthanide is widely used in semiconductor components such as metal-oxide-semiconductor (MOS) transistors as a standard gate material. However, as the size of the MOS transistor continues to shrink, the conventional polysilicon gate causes a decrease in component efficiency due to boron penetration effects, and an unavoidable depletion effect, etc., resulting in an equivalent gate. The thickness of the dielectric layer increases, and the value of the gate capacitance decreases, which leads to the dilemma of the deterioration of the component driving capability. Therefore, the semiconductor industry has adopted a new gate material, such as the use of work function metal to replace the traditional polysilicon gate for control of high dielectric constant (High-K) gate dielectric layer. electrode.

In a complementary metal-oxide semiconductor (CMOS) device, the dual-function metal gate needs to be matched with the NMOS device on the one hand, and the PMOS device on the other hand, so that the integration technology of the related components is made. And the process control is more complicated, and the thickness and composition control requirements of each material are more stringent. The manufacturing method of the double work function metal gate can be roughly divided into two categories: a gate first process and a gate last process. Among them, the front gate process will start the metal/gate bungee ultra-shallow junction activation and tempering and form a high-heat budget process such as metal telluride, which makes the selection and adjustment of materials face more challenges. In order to avoid the above-mentioned high thermal budget environment and obtain a wide choice of materials, the industry has proposed a method of replacing the front gate process by the gate process.

In the conventional gate process, a sacrificial gate or a replacement gate is formed first, and after the fabrication of the general MOS transistor is completed, the sacrificial/replacement gate is removed. A gate trench is filled with different metals in the gate recess according to electrical requirements. However, since the post-gate process is quite complicated and requires multiple processes to complete, the manufacturers are currently striving to simplify the process of forming metal gates.

The present invention thus provides a method of fabricating a semiconductor device having a metal gate, which results in better process reliability.

According to a preferred embodiment, the present invention provides a method of fabricating a semiconductor component having a metal gate. This method first provides a substrate. The substrate comprises a first conductivity type transistor and a second conductivity type transistor, wherein the first conductivity type transistor comprises a first sacrificial gate, and the second conductivity type transistor comprises a second sacrificial gate. Then, the first sacrificial gate of the first conductivity type transistor is removed to form a first trench, and a first metal layer is formed in the first trench. The second sacrificial gate of the second conductivity type transistor is removed to form a second trench, and a second metal layer is formed in the first trench and in the second trench. Finally, a third metal layer is formed on the second metal layer, so that the third metal layer is filled into the first trench and the second trench.

The method provided by the invention firstly forms a P-type work function metal layer and an N-type work function metal layer in the first trench or the second trench, and finally fills the first trench and the first trench with a low-resistance metal layer. The second ditches can avoid the problem of poor filling ability of the conventional metal layer (usually aluminum), and the invention only requires one metal planarization step, so that the process yield can be effectively improved.

The present invention will be further understood by those skilled in the art to which the present invention pertains. The effect.

Referring to FIGS. 1 through 12, there is shown a schematic diagram of a method of fabricating a semiconductor device having a metal gate in a first embodiment of the present invention. First, a substrate 300 is provided, such as a germanium substrate, a germanium-containing substrate, or a silicon-on-insulator (SOI) substrate. The substrate 300 has a plurality of shallow trench isolation (STI) 302, and the shallow trench isolation 302 can have appropriate stress. By the area surrounded by the shallow trench isolation 302, a first active region 400 and a second active region 500 electrically insulated from each other can be defined. A first conductive type transistor 402 and a second conductive type transistor 502 are formed on the substrate 300 of the first active region 400 and the second active region 500, respectively. In the present embodiment, the first conductive type transistor 402 is a P-type transistor, and the second conductive type transistor 502 is an N-type transistor.

As shown in FIG. 1, the first conductive type transistor 402 includes a first gate dielectric layer 404, a first sacrificial gate 406, a first cap layer 408, a first sidewall sub-410, and a first A light doped drain (LDD) 412 and a first source/drain 414. In the preferred embodiment of the present invention, the first gate dielectric layer 404 can be a germanium dioxide layer or a high-k gate dielectric layer. The material of the high dielectric constant gate dielectric layer is, for example, a group consisting of tantalum nitride (SiN), bismuth oxynitride (SiON) or metal oxide, wherein the metal oxide may be a rare earth metal oxide layer, for example It is composed of hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon oxynitride (HfSiON), aluminum oxide (aluminum oxide, Al ₂ O _{3 ).} ), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta ₂ O ₅ ), zirconium oxide (ZrO ₂ ), zirconium silicate Zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO), strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate , PbZr _x Ti _1-x O ₃ , PZT) or barium strontium titanate (BaxSr _1-x TiO ₃ , BST). The first gate dielectric layer 404 can also be a composite layer comprising any combination of the above, preferably comprising a hafnium oxide layer and a high dielectric constant gate dielectric layer from bottom to top. The first sacrificial gate 406 is, for example, a polysilicon gate, but may also be a composite gate composed of a polysilicon layer, an amorphous Si or a germanium layer, or, in other embodiments, a first sacrificial gate. The pole 406 will have a sloping side wall with a "upper and lower" shape. Optionally, a matching layer or an etch stop layer for subsequent processing may be added between the first sacrificial gate 406 and the first gate dielectric layer 404, for example, including a tantalum nitride layer or a metal nitride layer such as titanium nitride. Or tantalum nitride. The first cap layer 408 is a selective film layer, such as a tantalum nitride layer or an oxide layer or a composite layer of the two. The first sidewall sub-410 may be a composite film layer structure, which may comprise a high temperature oxide layer (HTO), tantalum nitride, hafnium oxide or hexachlorodisilane (Si ₂ Cl ₆ ). Niobium nitride (HCD-SiN). In one embodiment, the first sidewall sub-410 may also be partially or completely removed, such that the contact etch stop layer (CESL) 306 is for the first conductive transistor 402 and the second conductive transistor. Crystal 502 can have better stress. The first lightly doped drain 412 and the first source/drain 414 are formed with a suitable concentration of dopant.

The second conductive type transistor 502 includes a second gate dielectric layer 504, a second sacrificial gate 506, a second cap layer 508, a second sidewall spacer 510, and a second lightly doped drain 512. A second source/drain 514. The embodiment of each element in the second conductivity type transistor 502 is substantially the same as that of the first conductivity type transistor 402, and will not be described herein. In addition, although not clearly depicted in FIG. 1, the first conductive type transistor 402 and the second conductive type transistor 502 may still include other semiconductor structures, such as a metal salicide layer, for selective epitaxial growth. Selective epitaxial growth (SEG) forms a source/drain or other protective layer having a hexagonal (also known as sigma Σ) or octangon cross-sectional shape. After the first conductive type transistor 402 and the second conductive type transistor 502 are formed, a contact etch stop layer (CESL) 306 and an inner dielectric layer are sequentially formed on the substrate 300 ( An inter-layer dielectric (ILD) 308 is overlaid on the first conductive type transistor 402 and the second conductive type transistor 502. In one embodiment, the contact hole etch stop layer 306 has a stress as a selective strain scheme (SSS); the contact hole etch stop layer 306 may be a single layer or a composite layer. A compressive stress is applied to a conductive type transistor 402 to apply a tensile stress on the second conductive type transistor 502.

As shown in FIG. 2, a planarization process, such as a chemical mechanical polish (CMP) process or an etch process or a combination of the two, is performed to sequentially remove portions of the inner layer. The electrical layer 308, a portion of the contact hole etch stop layer 306, a portion of the first sidewall sub-410, a portion of the second sidewall sub-510, and completely remove the first cap layer 408 and the second cap layer 508 until exposed The top surfaces of the first sacrificial gate 406 and the second sacrificial gate 506 are exited.

As shown in FIG. 3, a mask layer 312 and a selective auxiliary layer 314 are then formed over the substrate 300. In a preferred embodiment of the invention, mask layer 312 is preferably a titanium nitride (TiN) layer, and auxiliary layer 314 is preferably a hafnium oxide (SiO ₂ ) layer. The auxiliary layer 314 can provide better adhesion of the subsequently patterned photoresist layer 316. In one embodiment, the thickness of the mask layer 312 is substantially 50 to 150 angstroms, preferably 100 angstroms, and the thickness of the auxiliary layer 314 is substantially 0 to 50 angstroms, preferably 20 angstroms. , but not limited to the above. Next, a first patterned photoresist layer 316 is formed on the substrate 300 to cover at least the second active region 500.

Next, the first patterned photoresist layer 316 is used as a mask to remove the mask layer 312, the auxiliary layer 314, and the first sacrificial gate 406 that are not covered by the first patterned photoresist layer 316. The above steps first transfer the pattern of the first patterned photoresist layer 316 to the mask layer 312, and then remove the first sacrificial gate 406 with the mask layer 312 as a mask. However, the material of the first sacrificial gate 406 is, for example, polysilicon, and when the mask layer 312 is used as a mask to remove the underlying polysilicon material, the wet etching has a better etching selectivity ratio and can be perfectly stopped at the first gate. On the dielectric layer 404, but with severe undercut problems, such problems have interconnected P-type transistors and N-types in forming other semiconductor structures, such as static random access memory (SRAM) A semiconductor device having a gate interface of a transistor is more likely to occur. Conversely, dry etching has no lateral etching, but cannot be stopped on the first gate dielectric layer 404, and there is an over-etching problem. Therefore, in one embodiment, most of the first sacrificial gates are removed by dry etching. After 406, the last first sacrificial gate 406 is removed by wet etching and stopped on the first gate dielectric layer 404. Another embodiment of the present invention provides the following steps when removing the first sacrificial gate 406 of the polysilicon. Please refer to Figures 4a to 7b, wherein Figures 4b and 7b represent semiconductor structures having P-type transistors and N-type transistor gate junctions, which may correspond to Figures 4a and 7a, respectively. The cross-sectional view of the figure, and the profile corresponds to the position of the second sacrificial gate 506. The dotted line I of Fig. 4b and Fig. 7b represents the junction position composed of polycrystalline germanium, the right side of the broken line I represents a P-type semiconductor, and the left side represents an N-type semiconductor.

As shown in FIGS. 4a and 4b, a dry etching process is first performed to remove the mask layer 312 and the auxiliary layer 314 that are not covered by the first patterned photoresist layer 316, and a portion of the first sacrificial gate 406. . Next, as shown in FIG. 5, the first patterned photoresist 316 is trimmed, for example, using oxygen (O ₂ ), ozone (O ₃ ), carbon tetrafluoride (CF ₄ ) or hydrogen bromide. The plasma gas of (HBr) or the like is trimmed to the sidewall of the first patterned photoresist layer 316 to slightly reduce the width of the first patterned photoresist layer 316 such that the first patterned photoresist layer 316 is substantially uniformly Zooming inwardly, a second patterned photoresist layer 317 is formed. As shown in FIG. 4b, the first patterned photoresist layer 316 is originally closer to one side of the first sacrificial gate 406, and after the photoresist trimming step, the first photoresist layer 316 is adjacent to the second sacrificial gate 506. A second patterned photoresist layer 317 is formed on one side. It can be understood that the coverage area of the second patterned photoresist layer 317 may be smaller than the coverage area of the first patterned photoresist layer 316 from the perspective of the above view. Next, as shown in FIG. 6, the second patterned photoresist layer 317 is used as a mask to remove the mask layer 312 and the auxiliary layer 314 which are not covered by the second patterned photoresist layer 317. Finally, as shown in FIGS. 7a and 7b, after the second patterned photoresist layer 317 and the auxiliary layer 314 are removed, a wet etching step is performed to completely remove the first sacrificial gate 406. As shown in FIG. 7a, after removing the first sacrificial gate 406, a first trench 416 is formed in the first conductive type transistor 402, and a second sacrificial gate of the second conductive type transistor 502 is formed. 506 is not removed because it is covered by the mask layer 312; and as shown in FIG. 7b, the etched polysilicon sidewalls can be located more accurately at the dashed line I without the problem of lateral etching.

In an embodiment of the invention, after the first sacrificial gate 406 is removed, an annealing step may also be performed. Since a portion of the contact hole etch stop layer 306 is removed during the formation of the planarization process as in FIG. 2, the stress originally etched by the contact hole etch stop layer 306 is destroyed. Therefore, after the first sacrificial gate 406 is removed, the present invention also performs an annealing step to restore the stress state of the contact hole etch stop layer 306. In a preferred embodiment of the invention, the annealing step is performed, for example, by 500 to 700 degrees of heating using a rapid temperature annealing apparatus or a laser annealing apparatus, or by irradiating ultraviolet light (UV) in an environment of 300 to 450 degrees. In addition, after the first sacrificial gate 406 is removed, a dry etching step or a wet etching step may be performed to protect the upper portion of the first trench 416 with a photoresist (not shown) protecting the lower portion of the first trench 416. The first spacer 410, for example, removes the first spacer 410 located in the area A to increase the size of the upper opening of the first trench 416.

Next, as shown in FIG. 8, a P-type work function metal layer 318 is formed on the substrate 300. The P-type work function metal layer 318 is conformally formed along the surface of the first trench 416, but does not completely fill the first trench 416. In the present embodiment, the P-type work function metal layer 318 is a metal that satisfies the required work function of the P-type transistor, such as nickel (Ni), palladium (Pd), platinum (Pt), bismuth (Be), I (Ir), 碲 (Te), 铼 (Re), 钌 (Ru), 铑 (Rh), tungsten (W), molybdenum (Mo); tungsten, tantalum, molybdenum, tantalum (Ta), titanium (Ti) Nitride; tungsten, tantalum, titanium carbide; or TiAlN, TaAlN, but not limited to the above; P-type work function metal and mask layer 312 can use the same material or different materials, but preferably P-type work The functional metal and mask layer 312 can have a similar etch rate for the same etchant, and the preferred P-type work function metal is the same material as the mask layer 312.

Next, as shown in FIG. 9, a third patterned photoresist layer 320 is formed on the substrate 300, which covers at least the first active region 400. Next, as shown in FIG. 10, the third patterned photoresist layer 320 is used as a mask to remove the P-type work function metal layer 318 and the mask layer 312 that are not covered by the third patterned photoresist layer 320, and A second sacrificial gate 506 is exposed. Finally, the third patterned photoresist layer 320 is removed. Of course, when the etching step is performed by the third patterned photoresist layer 320, the trimming step described above may also be included.

Next, as shown in FIG. 11, a dry etching process and/or a wet etching process is performed to remove the second sacrificial gate 506, and a second trench 516 is formed in the second conductivity type transistor 502. Similarly, after the second sacrificial gate 506 is removed, an annealing process can be performed to restore the stress of the contact hole etch stop layer 306. Similarly, after the second sacrificial gate 506 is removed, the photoresist (not shown) protecting the lower portion of the second trench 516 may be selectively used to perform a dry etching step or a wet etching step to remove A second spacer 510 located at an upper portion of the second trench 516 enlarges the opening size of the upper portion of the second trench 516. Next, an N-type work function metal layer 322 is formed conformally on the substrate 300. The N-type work function metal layer 322 is conformally formed along the surface of the second trench 516 and the surface of the P-type work function metal layer 318 in the first trench 416, but does not completely fill the second trench 516 and the first trench 416. . In a preferred embodiment of the present invention, the N-type work function metal layer 322 is a metal that satisfies the required work function of the N-type transistor, such as titanium aluminides (TiAl), aluminium zirconium (aluminum zirconium, ZrAl), aluminum tungsten (WAl), aluminum tantalum (TaAl) or aluminum hafnium (HfAl), but not limited to the above. Next, in order to prevent the N-type work function metal layer 322 from being spiked by the subsequently filled metal layer 326 to affect its function, the embodiment may also selectively be between the N-type work function metal layer 322 and the metal layer 326. A barrier layer 324 is formed. In a preferred embodiment of the invention, the barrier layer 324 is a metal layer, such as a titanium nitride (TiN) layer. Finally, a low resistance metal layer 326 is formed on the substrate 300. The metal layer 326 is formed on the N-type work function metal layer 322 (if the barrier layer 324 is formed on the barrier layer 324), and fills the second trench 516 and the first trench 416. In a preferred embodiment of the invention, the metal layer 326 comprises aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), and nitride. Titanium (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium tungsten (Ti/W) or composite metal layers such as titanium and titanium nitride (Ti/TiN), but not limited thereto.

Finally, as shown in FIG. 12, a planarization process is performed to simultaneously remove the first trench 416 and the P-type work function metal layer 318, the N-type work function metal layer 322, and the metal layer 326 other than the second trench 516. As a result, the P-type work function metal 318, the N-type work function metal 322, the (barrier layer 324), and the metal layer 326 located in the first trench 416 form the first conductive type transistor 402 (P-type transistor). a first metal gate 418 having a work function substantially between 4.8 eV and 5.2 eV; and an N-type work function metal layer 322, a barrier layer 324, and a metal layer in the second trench 518 326 forms a second metal gate 518 in the second conductivity type transistor 502 (N-type transistor) and has a work function substantially between 3.9 eV and 4.3 eV. In another embodiment of the present invention, the thickness of the P-type work function metal layer 318 and the N-type work function metal layer 322 can be adjusted to perform a better work function.

After the first metal gate 418 and the second metal gate 518 are completed, a contact plug can also be fabricated, for example, to form a contact plug having stress. Alternatively, before the contact plug is formed, the inner dielectric layer 306 and the contact hole etch stop layer 308 may be completely removed, and then at least another contact hole etch stop layer (not shown) is formed on the substrate 300 again. And by applying ultraviolet rays or thermal energy, a new contact hole etch stop layer generates a stress to improve the performance of the first conductive type transistor 402 and the second conductive type transistor 502, respectively. Next, another inner dielectric layer (not shown) is formed again, and a contact plug is formed therein, and the contact plug can also have an appropriate stress.

It should be noted that the foregoing embodiment is preceded by the formation of a high dielectric constant gate dielectric layer (i.e., a high-K first process), and those skilled in the art will appreciate that the present invention can also be used prior to forming a metal gate. Forming a high dielectric constant gate dielectric layer (ie, a high-K last process), for example, forming a high surface on the first trench 416 prior to forming the P-type work function metal layer 318 in the first trench 416 The gate dielectric layer of the dielectric constant is then sequentially formed into a P-type work function metal layer 318 and a metal layer 326. The high dielectric constant gate dielectric layer in the first trench 416 has a U-shaped cross-section similar to the P-type work function metal layer 318; likewise, an N-type work function metal layer 322 is formed in the second trench 516. Previously, a high dielectric constant gate dielectric layer may be formed on the surface of the second trench 516, and then an N-type work function metal layer 322 and a metal layer 326 may be sequentially formed, which is located at the second trench 516. The gate dielectric layer of dielectric constant will have a U-shaped profile as the N-type work function metal layer 322. In addition, if the high-Klast process is employed, the dielectric layer formed before the sacrifice of the gate is not limited to a high dielectric constant material, but may be a material such as SiO ₂ .

Please refer to FIG. 13 to FIG. 19, which are schematic diagrams showing a method of fabricating a semiconductor device having a metal gate in a second embodiment of the present invention. The first half of the second embodiment is the same as the first embodiment to the second embodiment of the first embodiment, and the above description is omitted, and details are not described herein. In order to be able to clearly describe the embodiments of the present invention, the same elements will be denoted by the same elements. As shown in FIG. 13 , after performing the planarization process, a mask layer 312 , an auxiliary layer 314 and a first patterned photoresist layer 319 are formed on the substrate 300 , wherein the first patterned photoresist layer is formed. 319 will cover at least the first active area 400.

Next, as shown in FIG. 14, the first patterned photoresist layer 319 is used as a mask to remove the mask layer 312, the auxiliary layer 314, and a portion of the second sacrifice that are not covered by the first patterned photoresist layer 319. Gate 506. Then, after the first patterned photoresist layer 319 and the auxiliary layer 314 are removed, the second sacrificial gate 506 is completely removed to form the second trench 516. An annealing step is then performed to reinforce the stress in the contact hole etch stop layer 308. Of course, when the etching step is performed by using the first patterned photoresist layer 319, the trimming step described in the first embodiment may also be included. Alternatively, a dry etching step or a wet etching step may be performed to enlarge the opening size of the upper portion of the second trench 516.

Next, as shown in FIG. 15, an N-type work function metal layer 322 is entirely formed on the substrate 300. The N-type work function metal layer 322 is formed along the surface of the second trench 516, but does not completely fill the second trench 516. Next, as shown in FIG. 16, a third patterned photoresist layer 321 is formed on the substrate 300 to cover at least the second active region 500. As shown in FIG. 17, the third patterned photoresist layer 321 is used as a mask, and the N-type work function metal layer 322 and the mask layer 312 not covered by the third patterned photoresist layer 321 are removed and exposed. The first sacrificial gate 406 is finally removed and the third patterned photoresist layer 321 is removed. When the etching step is performed by the third patterned photoresist layer 321 herein, the trimming step described in the first embodiment may also be included.

As shown in FIG. 18, a dry etching process and/or a wet etching process is performed to remove the first sacrificial gate 406, and a first trench 416 is formed in the first conductive type transistor 402. In another embodiment, a dry etching step or a wet etching step may be performed to enlarge the opening size of the upper portion of the first trench 416. Alternatively, an annealing step is performed to reinforce the stress of the contact hole etch stop layer 308. Next, a P-type work function metal layer 318 is formed on the substrate 300. The P-type work function metal layer 318 is formed along the surface of the first trench 416 and the surface of the N-type work function metal layer 322 in the second trench 516, but does not completely fill the first trench 416 and the second trench 516. Next, a low resistance metal layer 326 can be formed directly on the P-type work function metal layer 318. Metal layer 326 is formed over N-type work function metal layer 322 and fills second trench 516 and first trench 416.

Finally, as shown in FIG. 19, a planarization process is performed to simultaneously remove the P-type work function metal layer 318, the N-type work function metal layer 322, and the metal layer 326 located outside the first trench 416 and the second trench 516. . As such, the P-type work function metal layer 318 and the metal layer 326 located in the first trench 416 form the first metal gate 418 of the first conductive type transistor 402 (P-type transistor), and the work function thereof Roughly between 4.8 eV and 5.2 eV; and the N-type work function metal layer 322, the P-type work function metal layer 318, and the metal layer 326 located in the second trench 518 form a second conductivity type transistor 502 (N The second metal gate 518 in the type of transistor has a work function substantially between 3.9 eV and 4.3 eV.

The feature of the present embodiment is that the material of the P-type work function metal layer 318 can also be used as a good barrier layer (TiN). Therefore, in this embodiment, the barrier layer 324 is additionally disposed in comparison with the first embodiment. The N-type work function metal layer 322 and the metal layer 326 are between. The P-type work function metal layer 318 can simultaneously function as a P-type work function metal and a barrier layer. In this way, the number of stacked layers of the metal layer in the first transistor 402 and the second transistor 502 can be reduced to avoid excessive metal layer filling holes, resulting in a problem of poor hole filling ability.

Similarly, after the first metal gate 418 and the second metal gate 518 are completed in this embodiment, a contact hole etch stop layer having a stress contact plug or a stress may be formed according to the design of the selective stress system. In addition to the foregoing high-K first process, the high-K last process can also be applied to the embodiment.

In another embodiment of the present invention, after the N-type work function metal layer 322 is formed, a passivation process can be performed immediately, so that the surface of the N-type work function metal layer 322 forms a passivation structure. The passivation process, for example, uses aqueous water to passivate the surface of the N-type work function metal layer 322, or to perform a nitridation process or an oxidation process. After the passivation process is completed, a P-type work function metal layer 318, a metal layer 326 or a barrier layer 324 may be formed on the N-type work function metal layer 322 in the manner of the foregoing embodiment.

In summary, the present invention provides a method of fabricating a semiconductor device having a gate. The method first forms a P-type work function metal layer and an N-type work function metal layer in the first trench or the second trench, and finally fills the first trench and the second trench simultaneously with a low-resistance metal layer, so It is possible to avoid the problem of poor filling ability of the conventional metal layer (usually aluminum). The invention also requires only one metal planarization step, which can effectively improve the yield of the process. The present invention also considers the problem that the N-type work function metal layer is easily invaded by metal aluminum, and thus various embodiments are provided (forming a barrier layer, performing a passivation process, and directly using a P-type work function metal layer as a barrier layer) to avoid This is the case. In addition, the present invention uses the photoresist trimming process and the annealing process to form the first trench and the second trench, which can increase the reliability of the product and improve the product yield.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

300. . . Base

302. . . Shallow trench isolation

306. . . Contact hole etch stop layer

308. . . In-layer dielectric layer

312. . . Mask layer

314. . . Auxiliary layer

316. . . First patterned photoresist layer

317. . . Second patterned photoresist layer

318. . . P type work function metal layer

319. . . First patterned photoresist layer

320. . . Third patterned photoresist layer

321. . . Third patterned photoresist layer

322. . . N-type work function metal layer

324. . . Barrier layer

326. . . Metal layer

400. . . First active area

402. . . First conductivity type transistor

404. . . First gate dielectric layer

406. . . First sacrificial gate

408. . . First cover

410. . . First side wall

412. . . First lightly doped bungee

414. . . First source/dip

416. . . First ditches

418. . . First metal gate

500. . . Second active area

502. . . Second conductivity type transistor

504. . . Second gate dielectric layer

506. . . Second sacrificial gate

508. . . Second cover

510. . . Second side wall

512. . . Second lightly doped bungee

514. . . Second source/dip

516. . . Second ditches

518. . . Second metal gate

1 to 12 are schematic views showing a method of fabricating a semiconductor device having a metal gate in the first embodiment of the present invention.

13 to 19 are schematic views showing a method of fabricating a semiconductor device having a metal gate in a second embodiment of the present invention.

300. . . Base

302. . . Shallow trench isolation

306. . . Contact hole etch stop layer

308. . . In-layer dielectric layer

318. . . P type work function metal layer

322. . . N-type work function metal layer

324. . . Barrier layer

326. . . Metal layer

400. . . First active area

404. . . First gate dielectric layer

410. . . First side wall

412. . . First lightly doped bungee

414. . . First source/dip

500. . . Second active area

504. . . Second gate dielectric layer

510. . . Second side wall

512. . . Second lightly doped bungee

514. . . Second source/dip

516. . . Second ditches

Claims (19)

A method of fabricating a semiconductor device having a metal gate includes: providing a substrate, wherein the substrate comprises a first conductivity type transistor, a second conductivity type transistor, and the first conductivity type transistor comprises a first Sacrificating the gate, the second conductivity type transistor includes a second sacrificial gate; removing the first sacrificial gate of the first conductivity type transistor to form a first trench; forming in the first trench a first metal layer; the second sacrificial gate of the second conductivity type transistor is removed to form a second trench; a second metal layer is formed in the first trench and in the second trench; Forming a third metal layer on the second metal layer such that the third metal layer fills the first trench and the second trench; and performing a planarization process after forming the third metal layer while removing the The first trench and the first metal layer, the second metal layer and the third metal layer outside the second trench. A method of fabricating a semiconductor device having a metal gate as described in claim 1, wherein the first conductivity type transistor comprises a P type transistor, and the second conductivity type transistor comprises an N type transistor. A method of fabricating a semiconductor device having a metal gate as described in claim 2, wherein the first metal layer comprises nickel (Ni), palladium (Pd), platinum (Pt), bismuth (Be), I (Ir), 碲 (Te), 铼 (Re), 钌 (Ru), 铑 (Rh), tungsten (W), molybdenum (Mo); tungsten, tantalum, molybdenum, tantalum (Ta), titanium (Ti) Nitride; carbide of tungsten, tantalum, titanium; or TiAlN, TaAlN. A method of fabricating a semiconductor device having a metal gate as described in claim 2, wherein the second metal layer comprises titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), aluminum Taal or hafnium oxide (HfAl). The method for fabricating a semiconductor device having a metal gate as described in claim 2, before forming the third metal layer, further comprising forming a barrier layer on the second metal layer, such that the barrier layer Filling in the first trench and the second trench. A method of fabricating a semiconductor device having a metal gate as described in claim 5, wherein the barrier layer comprises titanium nitride. The method for fabricating a semiconductor device having a metal gate as described in claim 2, further comprising performing a passivation process on the second metal layer before forming the third metal layer. A method of fabricating a semiconductor device having a metal gate as described in claim 7, wherein the passivation process comprises an oxidation process, a nitridation process, or a process using ammonia water. A method of fabricating a semiconductor device having a metal gate as described in claim 1, wherein the first conductivity type transistor comprises an N-type transistor, and the second conductivity type transistor comprises a P-type transistor. A method of fabricating a semiconductor device having a metal gate according to claim 9, wherein the first metal layer comprises titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), aluminum Taal or hafnium oxide (HfAl). A method of fabricating a semiconductor device having a metal gate according to claim 9, wherein the second metal layer comprises nickel (Ni), palladium (Pd), platinum (Pt), bismuth (Be), bismuth ( Ir), yttrium (Te), yttrium (Re), yttrium (Ru), yttrium (Rh), tungsten (W), molybdenum (Mo); nitrogen of tungsten, tantalum, molybdenum, tantalum (Ta), titanium (Ti) a carbide of tungsten, tantalum or titanium; or TiAlN, TaAlN. The method for fabricating a semiconductor device having a metal gate as described in claim 9 further comprises: performing a passivation process on the second metal layer before forming the third metal layer. A method of fabricating a semiconductor device having a metal gate as described in claim 12, wherein the passivation process comprises an oxidation process, a nitridation process, or a process using ammonia water. Fabricating a semiconductor device having a metal gate as described in claim 1 The method, wherein the third metal layer comprises aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN ), titanium carbide (TiC), tantalum nitride (TaN), titanium tungsten (Ti/W) or titanium and titanium nitride (Ti/TiN). The method of fabricating a semiconductor device having a metal gate according to claim 1, wherein the step of removing the first sacrificial gate of the first conductivity type transistor comprises: forming a mask layer; Forming a first patterned photoresist layer on the mask layer to cover the second conductive type transistor; removing the mask layer and the portion of the first sacrifice not covered by the first patterned photoresist layer a gate; performing a photoresist trimming step on the first patterned photoresist layer to form a second patterned photoresist layer, wherein the second patterned photoresist layer has a smaller coverage area than the first patterned photoresist layer Covering area; removing the mask layer not covered by the second patterned photoresist layer; removing the second patterned photoresist layer; and performing a wet etching process to completely remove the first sacrificial gate . A method of fabricating a semiconductor device having a metal gate as described in claim 15 wherein the photoresist trimming step comprises using oxygen (O ₂ ), ozone (O ₃ ), carbon tetrafluoride (CF ₄ ) or Plasma gas of hydrogen bromide (HBr). The method of claim 15, further comprising forming an auxiliary layer on the mask layer, wherein the auxiliary layer comprises cerium oxide (SiO ₂ ). The method of fabricating a semiconductor device having a metal gate as described in claim 1, further comprising performing an annealing step after removing the first sacrificial gate. The method for fabricating a semiconductor device having a metal gate as described in claim 1, further comprising performing an annealing step after removing the second sacrificial gate.