TWI517219B - Method for making transistor having metal gate - Google Patents

Description

Method of fabricating a transistor having a metal gate

The present invention relates to a method of fabricating a metal gate, and more particularly to a method of etching an etch stop layer with an oxide layer as a dummy gate.

In the conventional semiconductor industry, poly-silicon is widely used in semiconductor components such as metal-oxide-semiconductor (MOS) transistors as a standard gate material. However, as the size of MOS transistors continues to shrink, conventional polysilicon gates have reduced device performance due to boron penetration effects, and depletion effects, resulting in equivalent gate dielectrics. The thickness of the equivalent oxide thickness (EOT) increases, and the value of the gate capacitance decreases, which in turn leads to a decline in the driving ability of the element. Therefore, the semiconductor industry has adopted a new gate material, such as the use of work function metal to replace the traditional polysilicon gate for control of high dielectric constant (high-K) gate dielectric layer. electrode.

The invention proposes a method for fabricating a transistor having a metal gate so that a metal gate can obtain a better work function adjustment function.

In accordance with a preferred embodiment of the present invention, the present invention provides a method of fabricating a transistor having a metal gate. A substrate is first provided and a transistor is formed on the substrate. The transistor includes a high dielectric constant gate dielectric layer, an oxygen-containing dielectric layer disposed on the high dielectric constant gate dielectric layer, and a dummy gate disposed on the oxygen-containing dielectric layer. The dummy gate and the oxygen-containing dielectric layer on the high dielectric constant gate dielectric layer are then removed. Finally, a metal gate is formed, wherein the metal gate is in direct contact with the high dielectric constant gate dielectric layer.

The present invention uses an oxygen-containing dielectric layer as an etch stop layer for removing dummy gates. The oxygen-containing dielectric layer can avoid oxygen depletion in the high dielectric constant gate dielectric layer during the annealing process, and can be removed in subsequent steps, so that the metal gate can directly contact the high dielectric constant gate dielectric. The layer is obtained to obtain a transistor of better performance.

The present invention will be further understood by those skilled in the art to which the present invention pertains. The effect.

Please refer to FIG. 1 to FIG. 3 , which are schematic diagrams showing the steps of forming a transistor having a metal gate in the first embodiment of the present invention. As shown in FIG. 1, a transistor 200 is first formed on the substrate 100. The transistor 200 includes an interface gate dielectric layer 102, a high dielectric constant layer 104, a metal layer 106, a dummy gate 108, a cap layer 110, a sidewall 112, and a source/drain 114. . The interface gate dielectric layer 102 mainly provides a high adhesion property of the high dielectric constant layer 104, and the material thereof is, for example, cerium oxide or a nitrogen-containing nitridation silicon dioxide. The high dielectric constant layer 104 may be one or more layers having a dielectric constant substantially greater than 20. The high dielectric constant layer 104 may be a metal oxide layer, such as a rare earth metal oxide layer, such as hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO), bismuth ruthenate. Hafnium silicon oxynitride (HfSiON), aluminum oxide (AlO), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta) ₂ O ₃ ), zirconium oxide (ZrO ₂ ), zirconium silicon oxide (ZrSiO), hafnium zirconium oxide (HfZrO), strontium bismuth tantalate (SrBi) ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) or barium strontium titanate (BaxSr _1-x TiO ₃ , BST). The metal layer 106 includes various metal materials such as titanium nitride (TiN), tantalum nitride (TaN), or titanium and titanium nitride (Ti/TiN), but is not limited thereto. The dummy gate 108 is, for example, a poly-silicon, but may be a composite gate composed of a polycrystalline germanium layer, an amorphous silicon or a germanium layer. The cap layer 110 is, for example, tantalum nitride (SiN). The sidewall sub-112 may be a single-layer or composite film layer structure, for example, it may include high temperature oxide (HTO), tantalum nitride, hafnium oxide, hafnium oxynitride or hexachlorodisilane (hexachlorodisilane). Niobium nitride (HCD-SiN) formed by Si ₂ Cl ₆ ). Source/drain 114 is formed with a suitable dopant. An inner dielectric layer 115 is then formed over the transistor 200. As shown in FIG. 2, the cap layer 110 and the dummy gate 108 are removed, and the metal layer 106 is used as an etch stop layer. Finally, as shown in FIG. 3, after the metal gate 116 is filled, a planarization process is performed to form the transistor 200 having the metal gate 116. The metal gate 116 may include a work function metal layer 117 having a U-shaped cross section and a metal layer 119. If the transistor 200 is an N-type transistor, the work function metal layer 117 may be titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl) or tantalum aluminide (HfAl). ), but not limited to the above. If the transistor 200 is a P-type transistor, the work function metal layer 117 may be titanium nitride (TiN) or tantalum carbide (TaC), etc., but is not limited thereto. The metal layer 119 may be aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide ( TiC), tantalum nitride (TaN), titanium tungsten (Ti/W) or a composite metal layer such as titanium and titanium nitride (Ti/TiN), but not limited thereto.

However, in the foregoing embodiment, the high dielectric constant layer 104 is formed before the dummy gate 108 is removed, and thus passes through a fabrication process of a general MOS transistor, such as some high temperature annealing processes, which will be The electrical constant layer 104 causes damage. As shown in FIG. 1, the upper portion of the high dielectric constant layer 104 is a metal layer 106. When a high temperature annealing (eg, activating source/drain 114) process is performed, the metal layer 106 is drawn in the high dielectric constant layer 104. An oxygen atom causes a phenomenon of oxygen vacancy. This affects the quality of the high dielectric constant layer 104 and also causes the flat band voltage (Vfb) to decrease. Moreover, the metal layer 106 is not removed when the dummy gate 108 is removed, so that the presence of the metal layer 106 affects the overall work function of the metal gate 116 when the metal gate 116 is subsequently filled. , which reduces the performance of the component.

Please refer to FIG. 4 to FIG. 10 , which are schematic diagrams showing the steps of fabricating a transistor having a metal gate in the second embodiment of the present invention. As shown in FIG. 4, a substrate 300 is first provided, such as a germanium substrate, a germanium-containing substrate, or a silicon-on-insulator (SOI) substrate. A plurality of shallow trench isolation (STI) 401 are then formed on the substrate 300.

Then, an interfacial layer 301, a high dielectric constant layer 303, an oxide layer 305, a dummy gate layer 307, and a cap layer 309 are sequentially deposited on the substrate 300. The deposition method can be carried out by various conventional deposition processes, such as chemical vapor deposition (PVD), physical vapor deposition (PVD), etc., but not limited to the above. The interface layer 301 mainly provides a high adhesion property of the high dielectric constant layer 303, and the material thereof is, for example, cerium oxide or a nitrogen-containing nitridation silicon dioxide. In another embodiment of the invention, the interface layer 301 can be formed on the substrate 300 in a thermally oxidized manner. The high dielectric constant layer 303 may be one or more layers having a dielectric constant substantially greater than 20. The high dielectric constant layer 303 may be a metal oxide layer, such as a rare earth metal oxide layer, such as hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO), bismuth ruthenate. Hafnium silicon oxynitride (HfSiON), aluminum oxide (AlO), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta) ₂ O ₃ ), zirconium oxide (ZrO ₂ ), zirconium silicon oxide (ZrSiO), hafnium zirconium oxide (HfZrO), strontium bismuth tantalate (SrBi) ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) or barium strontium titanate (BaxSr _1-x TiO ₃ , BST). The oxide layer 305 has a dielectric constant lower than that of the high dielectric constant layer 303, and is substantially between 4 and 15, and includes various oxide materials such as cerium oxide (SiO ₂ ). In another embodiment of the present invention, a oxyfluoride or an oxynitride such as cerium oxyfluoride (SiOF) or cerium oxynitride (SiON) may also be included. The dummy gate layer 307 is, for example, a poly-silicon, but may be a composite gate composed of a polycrystalline germanium layer, an amorphous silicon or a germanium layer. The cap layer 309 is, for example, tantalum nitride (SiN).

Next, as shown in FIG. 5, one or more photo-etching-processes are used to pattern the interface layer 301, the high dielectric constant layer 303, the oxide layer 305, and the dummy gate layer. 307 and a cap layer 309 to form an interface gate dielectric layer 302, a high dielectric constant gate dielectric layer 304, an oxygen-containing dielectric layer 306, a dummy gate 308, and a patterned cap layer 310, respectively, to form a gate. Pole structure. Next, as shown in FIG. 6, a sidewall 312 is formed on sidewalls of the interface gate dielectric layer 302, the high dielectric constant gate dielectric layer 304, the oxygen-containing dielectric layer 306, and the dummy gate 308. The sidewall 312 may be a single layer or a composite film layer, for example, it may comprise a high temperature oxide (HTO), tantalum nitride, hafnium oxide or hexachlorodisilane (Si ₂ Cl _{6 ).} ) formed tantalum nitride (HCD-SiN). The method of forming the sidewall spacers 312 is a conventional technique and will not be described herein. Next, an ion implantation process is performed with the sidewall 312 and the gate structure as a mask to form a source/drain 314 in the substrate 300, and an annealing process is performed to activate the source/drain 314. It is worth noting that the annealing process of the source/drain 314 is usually greater than 1000 degrees, which tends to cause oxygen vacancies in the high dielectric constant gate dielectric layer 304 (refer to FIG. 1). In the present embodiment, since the high dielectric constant gate dielectric layer 304 directly contacts the interface gate dielectric layer 302 having cerium oxide and the oxygen-containing dielectric layer 306 having an oxide, the dummy gate 308 There is no metal layer between the high dielectric constant gate dielectric layer 304, so the oxygen atoms in the high dielectric constant gate dielectric layer 304 do not escape during the annealing process, but can be interposed by the interface gate The electric layer 302 and the oxygen-containing dielectric layer 306 supply oxygen atoms, so that the problem of oxygen vacancy in the conventional high dielectric constant gate dielectric layer 304 can be effectively avoided. Similarly, the present invention can provide the same efficacy in other high temperature annealing steps such as an annealing step to form a metal telluride.

Moreover, although not explicitly depicted in FIG. 6, the transistor 400 of the present invention may still comprise other semiconductor structures, such as light doped drain (LDD), metal salicide, to select Selective epitaxial growth (SEG) forms a source/drain 314 or other protective layer having a hexagonal (also known as sigmaΣ) or octangon cross-sectional shape. In one embodiment, after the source/drain 314 or the metal telluride layer (not shown) is completed, the sidewall spacers 312 may also be partially or completely removed, so that the subsequently formed contact hole etch stop layer ( Contact etch stop layer, CESL) 316 has better stress for transistor 400.

Next, as shown in FIG. 7, after the fabrication of the transistor 400 is completed, a contact hole etch stop layer 316 and an inter-layer dielectric (ILD) 318 are sequentially deposited over the transistor 400. . In one embodiment, the contact hole etch stop layer 316 has a stress. Then, a planarization process, such as a chemical mechanical polish (CMP) process or an etch process, is performed to sequentially remove portions of the inner dielectric layer 318 and a portion of the contact hole etch stop layer. 316, a portion of the sidewall 312, and completely remove the patterned cap layer 310 until the top surface of the dummy gate 308 is exposed.

Next, as shown in FIG. 8, the dummy gate 308 is removed. The method of removal involves the use of a wet etching process, such as the use of a hydrogen peroxide (H ₂ O ₂ ) solution. Since the oxygen-containing dielectric layer 306 has a good etching selectivity for the dummy gate 308 of the polysilicon, it can serve as a good etch stop layer, and the etching process for removing the dummy gate 308 is stopped at the oxygen-containing dielectric layer 306. on.

Next, as shown in FIG. 9, the oxygen-containing dielectric layer 306 on the high dielectric constant gate dielectric layer 304 is removed, for example, a dry etching process, including the use of hydrofluoric acid (HF) or the like to remove the oxygen-containing medium. Electrical layer 306. In another embodiment of the present invention, the dummy gate 308 and the oxygen-containing dielectric layer 306 over the high dielectric constant gate dielectric layer 304 may be simultaneously removed by the same etching process. After the dummy gate 308 and the oxygen-containing dielectric layer 306 are removed, a trench 320 is formed in the transistor 400.

Finally, as shown in FIG. 10, a metal gate 326 is formed by filling a suitable metal in the trench 320 depending on the conductivity type of the transistor 400. Metal gate 326 can include a work function metal layer 322 and a metal layer 324. If the transistor 400 is an N-type transistor, the work function metal layer 322 may be titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl) or tantalum aluminide (HfAl). ), but not limited to the above. If the transistor 400 is a P-type transistor, the work function metal layer 322 may be titanium nitride (TiN) or tantalum carbide (TaC), etc., but is not limited thereto. The metal layer 324 may be aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide ( TiC), tantalum nitride (TaN), titanium tungsten (Ti/W) or a composite metal layer such as titanium and titanium nitride (Ti/TiN), but not limited thereto.

It should be noted that since the oxygen-containing dielectric layer 306 of the second embodiment has been removed in the foregoing steps, the metal gate 326 formed in the trench 320 may directly contact the high-k gate dielectric layer 304. . Compared with the first embodiment (please refer to FIG. 3), there is a metal layer 106 between the metal gate 116 and the high dielectric constant gate oxide layer 104. The transistor 400 of the present invention can have better work function adjustment. Tuning capability, so it has better performance.

In summary, the present invention provides a method of fabricating a transistor having a metal gate with an oxide layer as an etch stop layer for removing dummy gates. The oxide layer can avoid the phenomenon of oxygen depletion in the high dielectric constant layer during the annealing process, and can be removed in the subsequent step, so that the metal gate can directly contact the high dielectric constant layer to obtain a better performance. Crystal.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧Base

102‧‧‧Interface gate dielectric layer

104‧‧‧High dielectric constant layer

106‧‧‧metal layer

108‧‧‧Virtual gate

110‧‧‧ cover

112‧‧‧ Sidewall

114‧‧‧Source/Bungee

115‧‧‧ Inner dielectric layer

116‧‧‧Metal gate

117‧‧‧Work function metal layer

119‧‧‧metal layer

200‧‧‧Optoelectronics

300‧‧‧Base

301‧‧‧Interface

302‧‧‧Interface gate dielectric layer

303‧‧‧High dielectric constant layer

304‧‧‧High dielectric constant gate dielectric layer

305‧‧‧Oxide layer

306‧‧‧Oxygenated dielectric layer

307‧‧‧Virtual gate layer

308‧‧‧Virtual gate

309‧‧‧ cover

310‧‧‧ patterned cover

312‧‧‧ 边边子

314‧‧‧Source/Bungee

316‧‧‧Contact hole etch stop layer

318‧‧‧Internal dielectric layer

320‧‧‧ditch

322‧‧‧Work function metal layer

324‧‧‧metal layer

326‧‧‧Metal gate

400‧‧‧Optoelectronics

401‧‧‧Shallow trench isolation

1 to 3 are schematic views showing a method of forming a transistor having a metal gate in the first embodiment of the present invention.

4 to 10 are schematic views showing the steps of fabricating a transistor having a metal gate in the second embodiment of the present invention.

300‧‧‧Base

302‧‧‧Interface gate dielectric layer

304‧‧‧High dielectric constant gate dielectric layer

306‧‧‧Oxygenated dielectric layer

308‧‧‧Virtual gate

310‧‧‧ patterned cover

312‧‧‧ 边边子

314‧‧‧Source/Bungee

400‧‧‧Optoelectronics

401‧‧‧Shallow trench isolation

Claims (16)

A method of fabricating a transistor having a metal gate, comprising: providing a substrate; forming a transistor on the substrate, the transistor comprising a high dielectric constant gate dielectric layer, and an oxygen-containing dielectric layer disposed on The high dielectric constant gate dielectric layer and a dummy gate are disposed on the oxygen-containing dielectric layer; the dummy gate on the high dielectric constant gate dielectric layer is removed and the An oxygen-containing dielectric layer; and forming a metal gate, wherein the metal gate is in direct contact with the high-k gate dielectric layer. A method of fabricating a transistor having a metal gate as described in claim 1, wherein the oxygen-containing dielectric layer comprises a fluoride or a nitride. A method of fabricating a transistor having a metal gate as described in claim 2, wherein the oxygen-containing dielectric layer comprises cerium oxide (SiO ₂ ), cerium oxyfluoride (SiOF) or cerium oxynitride (SiON). . The method of fabricating a transistor having a metal gate according to claim 1, wherein in the step of forming the transistor, the oxygen-containing dielectric layer is in direct contact with the high dielectric constant gate dielectric layer. . The method for fabricating a transistor having a metal gate as described in claim 1 In the step of forming the transistor, there is no metal layer between the dummy gate and the high dielectric constant gate dielectric layer. A method of fabricating a transistor having a metal gate as described in claim 1, wherein the oxygen-containing dielectric layer is removed after the dummy gate is removed. A method of fabricating a transistor having a metal gate as described in claim 6 wherein the step of removing the dummy gate comprises a wet etching process. A method of fabricating a transistor having a metal gate as described in claim 6 wherein the step of removing the oxygen-containing dielectric layer comprises a dry etching process. A method of fabricating a transistor having a metal gate as described in claim 1, wherein the high dielectric constant gate dielectric layer is a metal oxide layer. A method of fabricating a transistor having a metal gate as described in claim 9 wherein the metal is a rare earth metal. A method of fabricating a transistor having a metal gate according to claim 9 wherein the high dielectric constant gate dielectric layer comprises a hafnium oxynitride (HfSiO) or a niobium niobate oxynitride (HfSiON). ), yttrium oxide (HfO ₂ ), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminate (LaAlO), zirconia (ZrO ₂ ), zirconium oxynitride (ZrSiO), yttrium zirconate (HfZrO), yttrium Strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) or barium strontium titanate (BaxSr _{1) -x} TiO ₃ , BST). The method of fabricating a transistor having a metal gate according to the first aspect of the invention, wherein the transistor further comprises an interface gate dielectric layer disposed between the substrate and the high dielectric constant gate dielectric layer, And the interface gate dielectric layer is in direct contact with the high dielectric constant gate dielectric layer. A method of fabricating a transistor having a metal gate as described in claim 12, wherein the interface gate dielectric layer comprises hafnium oxide or nitrogen-containing hafnium oxide. The method for fabricating a transistor having a metal gate according to claim 12, wherein the method for forming the transistor comprises: sequentially forming an interface layer, a high dielectric constant layer, and an oxidation on the substrate. a dummy layer and a dummy gate layer; and performing a patterning process to form the interface gate dielectric layer, the high dielectric constant gate dielectric layer, the oxygen-containing dielectric layer, and the dummy gate . A method for fabricating a transistor having a metal gate as described in claim 14, wherein the method of forming the transistor further comprises: the interface gate dielectric layer, the high dielectric constant gate dielectric layer Forming a sidewall on the sidewall of the oxide layer and the dummy gate; performing an ion implantation process on the sidewall as a mask to form a source in the substrate Pole/drain; and performing a source/drain annealing process. A method of fabricating a transistor having a metal gate as described in claim 15 wherein the source/drain annealing process has a temperature greater than 1000 degrees.