201237947 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種製作金屬閘極方法，特別是一種在以氧化物 層為移除虛置閘極時的餘刻停止層的方法。 【先前技術】 在習知半導體產業中，多晶矽(P〇ly_silic〇n)係廣泛地應用於半導 體元件如金氧半導體(metal-oxide-semiconductor，MOS)電晶體中， 作為標準的閘極材料。然而，隨著金氧半導體電晶體尺寸持續地縮 小’傳統多晶矽閘極因硼穿透(bor〇npenetrati〇n)效應而導致元件效 能降低，以及空乏效應(depletion effect)問題，使得等效的閘極介電 層(equivalentoxidethickness，E〇T)厚度增加、閘極電容值下降進 而導致元件驅動能力的衰退。因此，料體業界更嘗以新的閉極材 料，例如利用功函數(w〇rkfimcti〇I1)金屬來取代傳統的多晶矽閘極， 用以作為匹配高介電常數(high-K)閘極介電層的控制電極。 【發明内容】 、^發明提出-種製作具有金制極之電晶體的方法使金屬間極 可以得到較佳的功函數調節功能。 根據本發明較佳實施例，本發明係提出一種製作具有金屬閘極 之電晶體的方法。首先提供一基底，並於基底上形成—電晶體。電 3 201237947 晶體包含1介電常數_介騎、—含氧介電躲置於高介電常 數閘極介電層上以及—虛置閘極設置於含氧介電層上。接著移除位 於高介電常數_介電層上之虛置閘極以及含氧介電層。最後形成 一金屬閘極，其+金制極直接接觸於高介f常數_介電層。 本發明以含氧介電層作為移除虛置閘極時的細停止層。含氧 介電層在耿抛日村魏高介”數_介·鼓氧空乏的現 象’且後續步驟中可以被移除，使得金翻極能直接細高介電常 數閘極介電層，而得到一較佳效能的電晶體。 【實施方式】 為使熟習本發明所屬技術領域之—般技藝者能更進_步了解本 發明’下文制舉本發明之數個齡實關，並配合所_式，詳 細說明本發明的構成内容及所欲達成之功效。 。月參考第1圖至苐3圖，所繪示為本發明第一實施例中形成具 有金屬閘極之電晶體的步驟示意圖。如第1圖所示，首先在基底 上开>成一電晶體200。電晶體200包含有一介面閘極介電層1〇2、一 尚介電常數層104、一金屬層1〇6、一虛置閘極ι〇8、一蓋層11〇、 一側壁子112以及一源極/;及極114。介面閘極介電層1〇2主要提供 高介電常數層104較佳的附著能力，其材質例如是二氧化矽或是含 亂的二氧化石夕層(nitridation silicon dioxide)。高介電常數層1〇4可以 是一層或多層的結構’其介電常數大致大於20。高介電常數層1〇4 201237947 可以是一金屬氧化物層，例如一稀土金屬氧化物層，例如是氧化铪 (hafnium oxide, Hf02)、矽酸铪氧化合物(hafhium smc〇n 0Xide， HfSiO)、石夕酸給氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧 化鋁(aluminumoxide，A10)、氧化鑭(lanthanumoxide，La203)、鋁酸 鑭（lanthanum aluminum oxide，LaAlO)、氧化鈕(tantalum oxide， Ta2〇3)、氧化#(zirconium oxide，Zr02)、石夕酸#氧化合物(zirconium silicon oxide，ZrSiO)、錄酸給(hafnium zirconium oxide, HfZrO)、錯叙 鈕氧化物(strontium bismuth tantalate，SrBi2Ta209, SBT)、鍅鈦酸鉛 (lead zirconate titanate，PbZrxTikOs，PZT)或鈦酸鋇鋰(barium strontium titanathBaxSr^TiC^BST)等。金屬層 106 包含各種金屬材 質例如氮化鈦(TiN)、氮化姐(TaN)或鈦與氮化鈦(Ti/TiN)，但不以此 為限。虛置閘極108例如是多晶石夕(p〇ly-silicon)，但也可以是由多晶 矽層、非晶矽(amorphous Si)或者鍺層所組合的複合閘極。蓋層11〇 例如是氮化矽(SiN)。側壁子112可為一單層或複合膜層之結構，例 如其可包含高溫氧化石夕層(high temperature oxide, HTO)、It化石夕、氧 化石夕、氣氧化石夕或使用六氯二石夕院(hexachlorodisilane, Si2Cl6)形成的 氮化矽(HCD-SiN)。源極/沒極114則以適當的摻質形成。接著於電 晶體200上形成一内層介電層115。如第2圖所示，移除蓋層11〇 以及虛置閘極108，並以金屬層106為蝕刻停止層。最後如第3圖 所示，填入金屬閘極116後進行一平坦化製程，而形成具有金屬閘 極116之電晶體200。其中金屬閘極116可以包含具有U型剖面之 功函數金屬層117以及金屬層119。若電晶體200為N型電晶體， 功函數金屬層117可以是鋁化鈦(TiAl)、鋁化锆(ZrAl)、鋁化鎢 5 i 201237947 (WAl)、紹化钽(TaAl)或紹化給(HfAi)，但不以上述為限。若電晶體 200為Ρ型電晶體，功函數金屬層117可以是氮化鈦(TiN)或碳化鈕 (TaC)等，但不以上述為限。金屬層丨丨9可以是鋁(A1)、鈦(Ti)、鈕(τ&)、 鎢(W)、錕(Nb)、鉬(Mo)、銅(cu)、氮化鈦(TiN)、碳化鈦(Tic)、氮 化钽(TaN)、鈦鎢(Ti/W)或鈦與氮化鈦(Ti/TiN)等複合金屬層料，但不 以此為限。 然而’則述實施例中向介電常數層1〇4由於在移除虛置閘極⑺8 之前便已形成，因此會經過—般金氧半導體電晶體的製作過程，例 如-些高溫退火的製程’這將對高介電常數層⑽造成損害。如第 1圖所示’⑷I電爷數層1〇4上方為金屬層1〇6,當進行高溫退火(例 如活化源極級極m)製程的時候，金屬層倾取高介電常數層 104中的氧原子，而造成氧空缺(⑽作如^⑶以^)的現象。這會影響 南介電常數層104的品質，也使得寬帶電_atbandv〇kage,vfb)201237947 VI. Description of the Invention: [Technical Field] The present invention relates to a method of fabricating a metal gate, and more particularly to a method of stopping a layer with an oxide layer as a residual gate. [Prior Art] In the conventional semiconductor industry, polycrystalline germanium (P〇ly_silic) is widely used in semiconductor elements such as metal-oxide-semiconductor (MOS) transistors as a standard gate material. However, as the size of MOS transistors continues to shrink, 'the traditional polysilicon gates are reduced by the boron penetration (bor〇npenetrati〇n) effect, and the depletion effect problem, making the equivalent gate The increase in the thickness of the equielectric oxide thickness (E〇T) and the decrease in the gate capacitance result in the degradation of the component driving capability. Therefore, the material industry is eager to use new closed-cell materials, such as the use of work function (w〇rkfimcti〇I1) metal to replace the traditional polysilicon gate, as a matching high-k (high-K) gate Control electrode of the electrical layer. SUMMARY OF THE INVENTION The invention has been proposed to produce a transistor having a gold electrode so that a good work function adjustment function can be obtained for the intermetallic electrode. In accordance with a preferred embodiment of the present invention, the present invention provides a method of fabricating a transistor having a metal gate. A substrate is first provided and a transistor is formed on the substrate. Electricity 3 201237947 The crystal contains a dielectric constant. The dielectric is trapped on the high dielectric constant gate dielectric layer and the dummy gate is placed on the oxygen-containing dielectric layer. The dummy gate and the oxygen-containing dielectric layer on the high dielectric constant dielectric layer are then removed. Finally, a metal gate is formed, the + gold pole directly contacting the high dielectric constant_ dielectric layer. The present invention uses an oxygen-containing dielectric layer as a fine stop layer for removing dummy gates. The oxygen-containing dielectric layer can be removed in the subsequent steps of the 耿 日 村 村 高 高 ” 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且A preferred performance transistor. [Embodiment] To enable those skilled in the art to which the present invention pertains, the present invention can be further described in the following claims. The composition of the present invention and the effects to be achieved are described in detail. Referring to Figures 1 to 3, the steps of forming a transistor having a metal gate in the first embodiment of the present invention are shown. As shown in Fig. 1, first, a transistor 200 is formed on the substrate. The transistor 200 includes a dielectric gate dielectric layer 1, a dielectric constant layer 104, and a metal layer 1 and 6. A dummy gate 〇8, a cap layer 11 〇, a sidewall spacer 112, and a source/pole and a drain 114. The interface gate dielectric layer 〇2 mainly provides a high adhesion property of the high dielectric constant layer 104. , the material is, for example, cerium oxide or a disordered silicon dioxide layer (nitridation silicon d Ioxide). The high dielectric constant layer 1〇4 may be one or more layers of structure whose dielectric constant is substantially greater than 20. The high dielectric constant layer 1〇4 201237947 may be a metal oxide layer, such as a rare earth metal oxide. The layer is, for example, hafnium oxide (Hf02), hafhium smc〇n 0Xide (HfSiO), hafnium silicon oxynitride (HfSiON), alumina (aluminum oxide, A10) Lanthanum oxide (La203), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta2〇3), oxidation #(zirconium oxide, Zr02), zirconium silicon oxide , ZrSiO), hafnium zirconium oxide (HfZrO), strontium bismuth tantalate (SrBi2Ta209, SBT), lead zirconate titanate (PbZrxTikOs, PZT) or barium titanate (barium) Strontium titanathBaxSr^TiC^BST), etc. The metal layer 106 comprises various metal materials such as titanium nitride (TiN), tantalum (TaN) or titanium and titanium nitride (Ti/TiN), but not limited thereto. Gate 108 is for example It is p〇ly-silicon, but it can also be a composite gate composed of a polycrystalline germanium layer, an amorphous silicon or a germanium layer. The cap layer 11 is, for example, tantalum nitride (SiN). The side wall 112 may be a single layer or a composite film layer, for example, it may comprise high temperature oxide (HTO), It's fossil, oxidized stone, gas oxidized stone or using hexachlorite. Niobium nitride (HCD-SiN) formed by hexachlorodisilane (Si2Cl6). Source/dipole 114 is formed with a suitable dopant. An inner dielectric layer 115 is then formed over the transistor 200. As shown in Fig. 2, the cap layer 11 〇 and the dummy gate 108 are removed, and the metal layer 106 is used as an etch stop layer. Finally, as shown in Fig. 3, a planarization process is performed after filling the metal gate 116 to form a transistor 200 having a metal gate 116. The metal gate 116 may include a work function metal layer 117 having a U-shaped cross section and a metal layer 119. If the transistor 200 is an N-type transistor, the work function metal layer 117 may be titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide 5 i 201237947 (WAl), TaAl or Shaohua. Give (HfAi), but not limited to the above. If the transistor 200 is a Ρ-type transistor, the work function metal layer 117 may be titanium nitride (TiN) or a carbonized button (TaC), etc., but is not limited thereto. The metal layer 丨丨9 may be aluminum (A1), titanium (Ti), button (τ &), tungsten (W), niobium (Nb), molybdenum (Mo), copper (cu), titanium nitride (TiN), A composite metal layer such as titanium carbide (Tic), tantalum nitride (TaN), titanium tungsten (Ti/W) or titanium and titanium nitride (Ti/TiN), but is not limited thereto. However, in the embodiment, the dielectric constant layer 1〇4 is formed before the dummy gate (7) 8 is removed, and thus passes through the fabrication process of the MOS transistor, for example, a process of high temperature annealing. 'This will cause damage to the high dielectric constant layer (10). As shown in FIG. 1 '(4) I, the number of layers 1 〇 4 is a metal layer 1 〇 6 , and when a high temperature annealing (for example, activating the source level m) is performed, the metal layer is poured into the high dielectric constant layer 104 . The oxygen atom in the process causes oxygen vacancies ((10) as ^(3) to ^). This affects the quality of the south dielectric constant layer 104, and also makes the broadband power _atbandv〇kage, vfb)
Ik之下降。再者’金屬層106在移除虛置閘極應時並不會一併被 移除此在後續填入金屬閘極116時，金屬層⑴6的存在會影響 金屬閘極116整體的功函數，而降低了元件的效能。 «月參考第4圖至第10圖’所繪示為本發明第二實施例中製作具 有金屬開極之電晶體的步驟示意圖。如第$晒示，首先提供一基 底300例如疋一石夕基底' 含石夕基底或石夕覆絕緣㈣.oh·】·, SOI)基底#。接著祕底·上形成複油淺溝渠隔離fallow trench isolation，sti)4〇i。 201237947 接著於基底300上依序全面性沈積一介面層3〇ι、一高介電常 數層303、-氧化物層305、-虛置閘極層3〇7以及一蓋層3〇9。沈 積的方法可以用習知的各種沈積製程，例如是化學氣相沈積 (chemical vapor deposition，PVD)、物理氣相沈積vap〇r deposition，PVD)等，但不以上述為限。介面層3〇1主要提供高介電 ㊉數層3G3 #父佳的附著能力’其材質例如是二氧化梦或是含氮的二 氧化石夕層(nitridatkm silicon dioxide)。於本發明另一實施例中，介面 層301可以以熱氧化的方式在基底3〇〇上形成。高介電常數層3〇3 可以是一層或多層的結構，其介電常數大致大於2〇。高介電常數層 303可以是一金屬氧化物層，例如一稀土金屬氧化物層，例如是氧 化铪(hafnium oxide，Hf〇2)、矽酸铪氧化合*(hafhium smc〇n 〇xide,The decline of Ik. Furthermore, the metal layer 106 is not removed when the dummy gate is removed. When the metal gate 116 is subsequently filled, the presence of the metal layer (1) 6 affects the overall work function of the metal gate 116. It reduces the performance of the component. The "month reference to Fig. 4 to Fig. 10" is a schematic view showing the steps of fabricating a transistor having a metal opening in the second embodiment of the present invention. For example, the first display is provided by a substrate 300 such as a stone base substrate or a stone-covered insulation (four). oh·, ·, SOI) substrate #. Then, the secret bottom isolation, sti) 4〇i is formed on the secret bottom. 201237947 Next, a via layer 3〇, a high dielectric constant layer 303, an oxide layer 305, a dummy gate layer 3〇7, and a cap layer 3〇9 are sequentially deposited on the substrate 300 in a comprehensive manner. The deposition method can be carried out by various conventional deposition processes such as chemical vapor deposition (PVD), physical vapor deposition vap〇r deposition (PVD), etc., but not limited to the above. The interface layer 〇1 mainly provides a high dielectric tens of layers of 3G3 #父佳 adhesion ability' material such as a dioxide dream or a nitrogen-containing nitridatkm silicon dioxide. In another embodiment of the invention, the interface layer 301 can be formed on the substrate 3 in a thermally oxidized manner. The high dielectric constant layer 3 〇 3 may be one or more layers having a dielectric constant substantially greater than 2 Å. The high dielectric constant layer 303 may be a metal oxide layer such as a rare earth metal oxide layer such as hafnium oxide (Hf〇2) or hafnium smc〇n 〇xide.
HfSiO)、石夕酸給氮氧化合物(hafnium siiic〇n 〇xynitride，HfSi〇N)、氧 化鋁(aluminum oxide，AlO)、氧化鑭(lanthanum oxide, La203)、鋁酸 鑭（lanthanum aluminum oxide，LaAlO)、氧化组(tantalum oxide，HfSiO), hafnium siiic〇n 〇xynitride (HfSi〇N), aluminum oxide (AlO), lanthanum oxide (La203), lanthanum aluminum oxide (LaAlO) ), oxidation group (tantalum oxide,
Ta：2〇3)、氧化鍅(zirconium oxide，Zr〇2)、矽酸锆氧化合物(zire〇nium silicon oxide, ZrSiO)、錯酸給(hafnium zirconium oxide, HfZrO)、銘级 鈕氧化物(strontium bismuth tantalate，SrBi2Ta209, SBT)、鍅鈦酸鉛 (lead zirconate titanate，PbZrxTikO]，PZT)或鈦酸鋇锶(barium strontium titanate，BaxSr^TiO3, BST)等。氧化物層 305 的介電常數低 於高介電常數層303，大致上為4〜15之間，其包含各種氧化物材質， 例如是二氧化矽(Si〇2)。於本發明另一實施例中，也可以包含氟氧化 物或氮氧化物，例如是氟氧化矽(SiOF)或氮氧化矽(SiON)。虛置閘 201237947 極層307例如是多晶石夕(p〇iy_siiic〇n)，但也可以是由多晶石夕層、非曰 矽(amorphous Si)或者鍺層所組合的複合閘極。蓋層309例如是氮化 矽(SiN)。 接著如第5圖所示，利用一次或多次的微影暨儀刻步驟 (photo-etching-process)以圖案化介面層301、高介電常數層3〇3、氧 化物層305、虛置閘極層307以及蓋層309,以分別形成介面間極介 電層302、高介電常數閘極介電層304、含氧介電層3〇6、虛置開極 308以及圖案化蓋層310，構成一閘極結構。接著如第6圖所示，在 前述介面閘極介電層302、高介電常數閘極介電層3〇4、含氧介電層 306以及虛置閘極308之側壁形成一側壁子312。側壁子312可為一 單層或衩合膜層之結構’例如其可包含高溫氧化石夕層(j^gh temperature oxide，HTO)、氮化矽、氧化矽或使用六氣二矽烷 (hexachlorodisilane，Si2Cl6)形成的氮化石夕(HCD-SiN)。形成側壁子 312 的方法為習知技術’在此不加以贅述。接著，以側壁子Μ]與問極 結構為遮罩進行-離子佈植製程，以在基底·中形成—源極/沒極 314 ’並進行一退火製程以活化源極級極314。值得注意的是，源極 /沒極314的退火製程通常會大於1000度，容易使得高介電常數閘 極介電層304產生氧空缺的問題(請參考第i圖）。而在本實施例中， 由於高介電常數_介電層會直接接觸具有二氧切的介面問 極介電層3〇2以及具有氧化物的含氧介電層3〇6，虛置間極與 高介電常數閘極介電層3G4之間不具有金屬層，因此在退火製程 時，高介電常數閘極介電層3〇4中的氧原子並不會逸失，反而可以 201237947 由介面閘極介電層302以及含氧介電層306供給氧原子，故可以有 效避免習知咼介電常數閘極介電層304氧空缺的問題。相同的，在 其他鬲溫退火步驟例如形成金屬矽化物的退火步驟，本發明也可以 提供相同的功效。 此外，雖然第6圖中未明白繪出，但本發明的電晶體4〇〇仍可 包3其他半導體結構’例如輕摻雜汲極(light d〇ped drain，LDD)、金 屬石夕化物層(salicide)、以選擇性磊晶成長(selectiveepitaxialgr〇wth, SEG)而形成具有六面體(hexagon ’又叫sigmaE)或八面體(〇伽叩〇11) 截面形狀的源極/汲極314或是其他保護層。而於一實施例中，在完 成源極/汲極314或金屬石夕化物層（圖未示)後，側壁子μ]亦可部份 或完全被移除，使得後續形成的接觸洞蝕刻停止層(c〇ntactetchst〇p layer，CESL) 316對於電晶體400具有較佳應力。 接著如第7圖所示，於完成了電晶體4〇〇的製作後，依序沈積 一接觸洞蝕刻停止層316與一内層介電層(如沉七^1>(^1沈以(：， ILD)318’覆蓋在電晶體400。於-實施例中，接觸洞勉刻停止層316 具有一應力。接著進行一平坦化製程，例如一化學機械平坦化 (chemical mechanical polish，CMP)製程或者一回蝕刻製程，以依序移 除部份的内層介電層318、部份的接觸洞蝕刻停止層316、部份的側 壁子312 ’並完全移除圖案化蓋層310 ’直到暴露出虛置閘極3〇8 之頂面。 201237947 一、接著如第8圖所示，移除虛謂極3G8。移除的方法包含利用 刻製程’例如使用過氧化氫_溶液。由於含氧介電層306 對於多晶判虛置閘極有良好祕刻選擇比，因此可以作為良 子的似j停止層’使移除虛置閑極祕刻製程停止在含氧介電 層306上。 人接著如第9圖所#，移除高介電常數閘極介電層3〇4上的含氧 ”電層306例如進行一乾餘刻製程，包含使用氫氟酸(册)等來移 除含氧介電層3G6。本發明另一實施例中，亦可以同一敍刻製程來 :時移除高介電常數閘極介電層撕之上的虛置閘極通以及含氧 η電層306。在移除了虛置閘極以及含氧介電層如6後會在 電晶體400中形成一溝渠320。 最後如第10圖所示，依據電晶體4〇〇的導電型態，在溝渠32〇 中填入適當的金屬而形成金屬閘極326。金屬閘極326可以包含功 函數金屬層322以及金屬層324。若電晶體400為Ν型電晶體，功 函數金屬層322可以是鋁化鈦(TiA1)、鋁化锆^认丨）、鋁化嫣(WA1)、 銘化组(TaAl)或鋁化铪(HfAl)，但不以上述為限。若電晶體4〇〇為p 型電晶體，功函數金屬層322可以是氮化欽(TiN)或碳化l^TaC)等， 但不以上述為限。金屬層324可以是鋁(A1)、鈦(Ti)、鈕(Ta)、鎢(W)、 鈮(Nb)、鉬(Mo)、銅(Cu)、氮化鈦(TiN)、碳化鈦(TiC)、氮化钽(TaN) ' 鈦鎢(Ti/W)或鈦與氮化鈦(Ti/TiN)等複合金屬層料，但不以此為限。 201237947 值得注意的是，由於第二實施例的含氧介電層3G6在前述步驟 中已經被移除，因此形成在溝渠η时的金屬間極咖可以直接接 觸高介電常賴極介電層3〇4。相較於第—實施财中齡考第3 圖)金屬閘極116和高介電常數閘極氧化層1〇4之間還具有金屬層 1〇6 ’本發明的電晶體彻可以具有較佳功函數調節能力細㈣曰 capability)，故具有更好的效能。 练上所述，本發明提供了一種製作具有金屬閘極之電晶體的方 法’以氧化物層作為移除虛置閘極的敍刻停止層。氧化物層在 製程時可避免高介電t數層產生氧空乏的現象，錢續步驟中可以 被移除’使得金屬·能直接賴高介電常數層，而得到 能的電晶體。 ^ 以上所述僅為本發明之較佳實施例，凡依本發财請專利範 所做之均㈣化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第3圖所繪示為本發明第一實施例中形成具有 極之電晶體的方法示意圖。 第4圖至第1〇圖所緣示為本發明第二實施例中製作具有金 極之電晶體的步驟示意圖。 ？ 【主要元件符號說明】 201237947 100 基底 304 高介電常數閘極介電層 102 介面閘極介電層 305 氧化物層 104 高介電常數層 306 含氧介電層 106 金屬詹 307 虛置閘極層 108 虛置閘極 308 虛置閘極 110 蓋層 309 蓋層 112 側壁子 310 圖案化蓋層 114 源極/沒極 312 側壁子 115 内層介電層 314 源極/没極 116 金屬閘極 316 接觸洞姓刻停止層 117 功函數金屬層 318 内層介電層 119 金屬層 320 溝渠 200 電晶體 322 功函數金屬層 300 基底 324 金屬層 301 介面層 326 金屬閘極 302 介面閘極介電層 400 電晶體 303 高介電常數層 401 淺溝渠隔離 12Ta: 2〇3), zirconium oxide (Zr〇2), zirconium silicon oxide (ZrSiO), hafnium zirconium oxide (HfZrO), Ming-grade button oxide ( Strontium bismuth tantalate, SrBi2Ta209, SBT), lead zirconate titanate (PbZrxTikO), PZT) or barium strontium titanate (BaxSr^TiO3, BST). The oxide layer 305 has a dielectric constant lower than that of the high dielectric constant layer 303, and is substantially between 4 and 15, and includes various oxide materials such as cerium oxide (Si 〇 2). In another embodiment of the present invention, a oxyfluoride or an oxynitride such as cerium oxyfluoride (SiOF) or cerium oxynitride (SiON) may also be contained. The dummy gate 201237947 is, for example, a polycrystalline stone (p〇iy_siiic〇n), but may also be a composite gate composed of a polycrystalline layer, an amorphous Si or a tantalum layer. The cap layer 309 is, for example, tantalum nitride (SiN). Next, as shown in FIG. 5, the interface layer 301, the high dielectric constant layer 3〇3, the oxide layer 305, and the dummy layer are patterned by one or more photo-etching-process steps. The gate layer 307 and the cap layer 309 respectively form an inter-electrode dielectric layer 302, a high dielectric constant gate dielectric layer 304, an oxygen-containing dielectric layer 3〇6, a dummy open electrode 308, and a patterned cap layer. 310, forming a gate structure. Next, as shown in FIG. 6, a sidewall 312 is formed on the sidewalls of the interface gate dielectric layer 302, the high dielectric constant gate dielectric layer 3〇4, the oxygen-containing dielectric layer 306, and the dummy gate 308. . The sidewall 312 can be a single layer or a structure of a chelating film layer. For example, it can comprise a high temperature oxidized oxide layer (HTO), tantalum nitride, cerium oxide or hexachlorodisilane. Nitride (HCD-SiN) formed by Si2Cl6). The method of forming the sidewall spacers 312 is a prior art and will not be described herein. Next, an ion implantation process is performed with the sidewall spacer and the spacer structure as a mask to form a source/drain 314 in the substrate and an annealing process is performed to activate the source level electrode 314. It is worth noting that the annealing process of the source/dot electrode 314 is usually greater than 1000 degrees, which tends to cause oxygen vacancies in the high dielectric constant gate dielectric layer 304 (refer to Figure i). In this embodiment, since the high dielectric constant_dielectric layer directly contacts the interposer dielectric layer 3〇2 having the dioxotomy and the oxygen-containing dielectric layer 3〇6 having the oxide, the dummy layer There is no metal layer between the pole and high dielectric constant gate dielectric layer 3G4. Therefore, during the annealing process, the oxygen atoms in the high dielectric constant gate dielectric layer 3〇4 will not escape, but can be 201237947 The interface gate dielectric layer 302 and the oxygen-containing dielectric layer 306 supply oxygen atoms, so that the problem of oxygen vacancy in the conventional dielectric constant gate dielectric layer 304 can be effectively avoided. Similarly, the present invention can provide the same efficacy in other annealing steps such as an annealing step of forming a metal telluride. In addition, although not clearly depicted in FIG. 6, the transistor 4 of the present invention may still include other semiconductor structures such as a lightly doped drain (LDD) and a metallized layer. (salicide), forming a source/drain 314 having a cross-sectional shape of a hexahedron (also known as sigmaE) or octahedron (sigma 叩〇11) by selective epitaxial growth (SEG) Or other layers of protection. In an embodiment, after the source/drain 314 or the metal-lithium layer (not shown) is completed, the sidewall μ may be partially or completely removed, so that the subsequently formed contact hole is etched. The layer (c〇ntactetchstp layer, CESL) 316 has better stress for the transistor 400. Then, as shown in FIG. 7, after the fabrication of the transistor 4 is completed, a contact hole etch stop layer 316 and an inner dielectric layer are deposited in sequence (eg, sinking 1^> , ILD) 318' is overlying the transistor 400. In the embodiment, the contact hole etch stop layer 316 has a stress. A planarization process, such as a chemical mechanical polish (CMP) process, or An etching process is performed to sequentially remove portions of the inner dielectric layer 318, portions of the contact hole etch stop layer 316, portions of the sidewall spacers 312', and completely remove the patterned cap layer 310' until exposed to a virtual The top surface of the gate 3〇8. 201237947 1. Next, as shown in Fig. 8, the virtual positive pole 3G8 is removed. The removal method includes the use of an engraving process 'for example, using a hydrogen peroxide solution. Layer 306 has a good secret selection ratio for the polycrystalline dummy gate, so it can be used as a good j-stop layer to stop the dummy dummy process on the oxygen-containing dielectric layer 306. Figure 9, Figure #, removes oxygen from the high dielectric constant gate dielectric layer 3〇4” The layer 306 is, for example, subjected to a dry process, including the use of hydrofluoric acid (salt) or the like to remove the oxygen-containing dielectric layer 3G6. In another embodiment of the present invention, the same process can be used to: remove the high dielectric The dummy gate via the constant gate dielectric layer and the oxygen-containing NMOS layer 306. A trench 320 is formed in the transistor 400 after the dummy gate and the oxygen-containing dielectric layer, such as 6, are removed. Finally, as shown in Fig. 10, according to the conductivity type of the transistor 4, a suitable metal is filled in the trench 32A to form a metal gate 326. The metal gate 326 may include a work function metal layer 322 and a metal. Layer 324. If the transistor 400 is a Ν-type transistor, the work function metal layer 322 may be titanium aluminide (TiA1), zirconia, yttrium (WA1), yam (TaAl) or aluminum. HfAl, but not limited to the above. If the transistor 4 is a p-type transistor, the work function metal layer 322 may be a nitride (TiN) or a carbonized l^TaC), but not the above The metal layer 324 may be aluminum (A1), titanium (Ti), button (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), Titanium carbide (TiC), nitriding (TaN) 'Titanium-tungsten (Ti/W) or composite metal layer such as titanium and titanium nitride (Ti/TiN), but not limited to this. 201237947 It is worth noting that the oxygen-containing medium of the second embodiment The electric layer 3G6 has been removed in the foregoing steps, so that the inter-metal enamel formed in the trench η can directly contact the high dielectric constant dielectric layer 3〇4. Compared with the first implementation of the middle age test 3)) The metal gate 116 and the high dielectric constant gate oxide layer 1 〇 4 also have a metal layer 1 〇 6 'The transistor of the present invention can have a good work function adjustment ability (four) 曰capability), Have better performance. As described above, the present invention provides a method of fabricating a transistor having a metal gate with an oxide layer as a stop stop for removing a dummy gate. The oxide layer can avoid the phenomenon of oxygen depletion in the high dielectric t-number layer during the process, and can be removed in the subsequent steps, so that the metal can directly depend on the high dielectric constant layer to obtain an energy transistor. The above is only the preferred embodiment of the present invention, and all the modifications and modifications made by the patent application are subject to the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 to Fig. 3 are schematic views showing a method of forming a transistor having a pole in the first embodiment of the present invention. 4 to 1 are schematic views showing the steps of fabricating a transistor having a gold electrode in the second embodiment of the present invention. ? [Main component symbol description] 201237947 100 Substrate 304 High dielectric constant gate dielectric layer 102 Interface gate dielectric layer 305 Oxide layer 104 High dielectric constant layer 306 Oxygen-containing dielectric layer 106 Metal Zhan 307 dummy gate Layer 108 dummy gate 308 dummy gate 110 cap layer 309 cap layer 112 sidewall sub-310 patterned cap layer 114 source/dot 312 sidewall sub-115 inner dielectric layer 314 source/nopole 116 metal gate 316 Contact hole name stop layer 117 work function metal layer 318 inner layer dielectric layer 119 metal layer 320 trench 200 transistor 322 work function metal layer 300 substrate 324 metal layer 301 interface layer 326 metal gate 302 interface gate dielectric layer 400 Crystal 303 high dielectric constant layer 401 shallow trench isolation 12