201239992 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種具有金屬閘極(metal gate)之半導體元件之 製作方法。 【先前技術】 在習知半導體產業中，多晶矽係廣泛地應用於半導體元件如金 氧半導體(metal-oxide-semiconductor，MOS)電晶體中，作為標準的 閘極材料麟。_，縣M〇S電猶尺寸持續地難，傳統多 晶矽閘極因硼穿透(boronpenetration)效應導致元件效能降低，及其 難以避免的空乏效應(deletioneffect)等問題，使得等效的閘極介電 層厚度增加、閘極電容值下降’進而導致元件驅動能力的衰退等困 境。因此’半導體業界更嘗以新的閘極材料，例如利用功函數(work ftmction)金屬來取代傳統的多晶矽閘極，用以作為匹配高介電常數 (High-K)閘極介電層的控制電極。 而在互補式金氧半導體(comp!ementary semiconductor，CMOS)元件中，雙功函數金屬閘極一方面需與 NMOS元件搭配’另-方面則需與PM〇s元件搭配，因此使得相關 元件的整合技_及f健制更形娜，且各材·厚度與成分控 制要求亦更形嚴苛。雙功函數金制極之製作方法係可概分為前閉 極(§扣6行加)製程及後閘極(职纪1批〇製程兩大類。其中前閘極製程會 4 201239992 在形成金>1 ’後始進行源極/汲極超淺接面活化回火以及形成金 屬石夕化物等高熱預算製程，因此使得材料的選擇與赃面對較多的 挑戰。為避免上述高熱預算環境並獲得較寬的材料選擇，業界係提 出以後閘極製程取代前閘極製程之方法。 、而S知後閘極製程中’係先形成一犧牲閘極(sacrifice糾e)或取 代閘極(replaCement_，並在完成一般應電晶體的製作後，將 犧牲/取代閘極移除而形成一閑極凹槽(g齡㈣，再依電性需求於 閘極凹槽内填人不同的金屬。但由於後閘極製程相當複雜，需要多 道製程才能完成，因此目前廠商皆致力精簡化形成金仙極之製程。 【發明内容】 是提供-種製作具有金制極之轉航件的方法， 了侍到較佳的製程可靠度。 導體彻’她祕了—_輪她之半 S i法導=首先提供一基底。基底包含-第-導： _極，:ΓΓ電 導電型電晶體體包含一第4牲閘極。接著移除第一 形成-第-金以形成一第一溝渠’並於第-溝渠内 -第-、、餘料。移除第二導電型電晶體之第二犧牲閘極以形由 於第—溝渠内以及第二溝渠内形201239992 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method of fabricating a semiconductor element having a metal gate. [Prior Art] In the conventional semiconductor industry, polycrystalline germanium is widely used in semiconductor elements such as metal-oxide-semiconductor (MOS) transistors as a standard gate material. _, the county M〇S electricity is still difficult to size, the traditional polysilicon gate due to boron penetration (boronpenetration) effect caused by the reduction of component performance, and its inevitable depletion effect (deletioneffect) and other issues, making the equivalent of the gate The thickness of the electric layer increases, and the value of the gate capacitance decreases, which leads to the dilemma of the decline of the component driving capability. Therefore, the semiconductor industry has adopted a new gate material, such as the use of work ftmction metal instead of the traditional polysilicon gate to control the high dielectric constant (High-K) gate dielectric layer. electrode. In a complementary CMOS device, the dual-function metal gate needs to be paired with the NMOS component on the one hand, and the other component needs to be matched with the PM 〇s component, thus integrating the related components. Technology and f health are more versatile, and the material, thickness and composition control requirements are more stringent. The production method of the double work function gold pole can be divided into two parts: the front closed pole (§6 line plus) and the rear gate (the first batch of the first batch). The front gate process will be 4 201239992. >1 ' After the source / bungee ultra-shallow junction activation tempering and the formation of metal-lithium and other high-heat budget process, so the choice of materials and 赃 face more challenges. To avoid the above high thermal budget environment And to obtain a wider choice of materials, the industry has proposed a method of replacing the front gate process by the gate process. In the process of the S-gate process, a sacrificial gate is formed or replaced. replaCement_, and after the completion of the general transistor production, the sacrificial/replacement gate is removed to form a recessed recess (g-age (4), and different metals are filled in the gate recess according to electrical requirements. However, since the post-gate process is quite complicated and requires multiple processes to complete, the current manufacturers are all striving to simplify the process of forming the Jinxian Pole. [Invention] It is a method for producing a transfer member having a gold pole. Responsible for better process reliability The conductor is 'her secret' - _ her half S i method = first provides a substrate. The substrate contains - the first guide: _ pole, the ΓΓ electrically conductive type crystal body contains a fourth gate. Removing the first formation-first-gold to form a first trench' and in the first-drain---, the remaining material. Removing the second sacrificial gate of the second conductivity type transistor to form the first-ditch Inner and second trench inner shape
、一金屬層上形成1三金屬層，使得第三金屬層填入L 201239992 溝渠以及第二溝渠中。 本發贿提供之方法’係先在第-溝縣者第二溝渠中分別形 成p型功函數金屬層以及N型韻數金屬層，最後再魏電阻之金 屬層同時填箱及第二溝渠，故可以避免習知技術金屬層 (通常是is)填洞能力不佳的問題，且本發明亦只需要—次的金屬平 坦化步驟，故可有效提高製程的良率。 【實施方式】 為使熟習本發賴屬技術倾之—般技藝者能更進-步了解本 發明’下文特列舉本發明之數個較佳實施例，並配合所附圖式，詳 細說明本發明的構成内容及所欲達成之功效。 清參考第1圖至第12圖，所綠示為本發明第一實施例中製作具 有金屬閘極之半導體元件的方法之示意圖。首先，提供—基底3〇〇， 例如疋-祕底、含魏底切覆穩請，哪基 ^4 0 300 ^^^'；^^|||^^(shallow trench isolation » STI)302 ’淺溝渠隔離3G2可具有適當的應力。藉由淺溝渠隔離3〇2 所包圍的區域，可定義出彼此電性絕緣的—第_主動區域4〇〇以及 -第二主動區域5GG。接著分別於第_主動區域·與第二主動區 域500之基底300上形成一第一導電型電晶體4〇2與一第二導電型 電晶體502。在本實施例中，第一導電型電晶體4〇2係為一 p型電 晶體’而第二導電型電晶體5〇2則為一 n型電晶體。 6 201239992 如第1圖所示，第一導電型電晶體402包含一第一閘極介電層 404、一第一犧牲閘極406、一第一蓋層408、一第一側壁子410、 一第一輕摻雜汲極(light doped drain，LDD) 412以及一第一源極/汲 極414。於本發明較佳實施例中，第一閘極介電層404可為一二氧 化石夕層’亦可為一高介電常數(high-K)閘極介電層。高介電常數閘極 介電層的材料例如為氮化矽(SiN)、氮氧化矽(Si〇N)或者金屬氧化物 所組成之一群組，其中金屬氧化物可以是稀土金屬氧化物層，例如 是包含氧化铪(hafnium oxide，Hf02)、矽酸姶氧化合物(hafnium silicon oxide，HfSi〇4)、石夕酸給氮氧化合物(hafhium silicon oxynitride, H⑸〇N)、氧化!呂(aluminum oxide，Al2〇3)、氧化鑭(lanthanum oxide, La203)、紹酸鑭（ianthanum aiumjnum 〇xjde，LaAi〇 )、氧化组(tantalum oxide，Ta2〇5)、氧化錯(zirconium oxide，Zr02)、石夕酸錯氧化合物 (zirconium silicon oxide, ZrSi04) ' (hafnium zirconium oxide,A metal layer is formed on a metal layer such that the third metal layer is filled into the L 201239992 trench and the second trench. The method of providing bribes is to form a p-type work function metal layer and an N-type rhyme metal layer respectively in the second ditch of the Digou County, and finally fill the metal layer of the Wei resistance and the second ditch at the same time. Therefore, the problem of poor filling ability of the conventional metal layer (usually is) can be avoided, and the present invention only requires a metal planarization step, so that the yield of the process can be effectively improved. [Embodiment] In order to make the skilled artisan, the skilled artisan can further understand the present invention. The following is a detailed description of several preferred embodiments of the present invention, and the present invention will be described in detail in conjunction with the drawings. The composition of the invention and the desired effect. Referring to Figs. 1 to 12, green is a schematic view showing a method of fabricating a semiconductor element having a metal gate in the first embodiment of the present invention. First, provide - the base 3 〇〇, for example, 疋-secret, containing the Wei undercut, which base ^ 4 0 300 ^ ^ ^ '; ^ ^ | | | ^ ^ (shallow trench isolation » STI) 302 ' Shallow trench isolation 3G2 can have appropriate stress. By the area surrounded by the shallow trench isolation 3〇2, the first active region 4〇〇 and the second active region 5GG can be defined electrically insulated from each other. A first conductive type transistor 4〇2 and a second conductive type transistor 502 are formed on the substrate 300 of the first active region and the second active region 500, respectively. In the present embodiment, the first conductivity type transistor 4〇2 is a p-type transistor 'and the second conductivity type transistor 5〇2 is an n-type transistor. 6 201239992 As shown in FIG. 1 , the first conductive type transistor 402 includes a first gate dielectric layer 404 , a first sacrificial gate 406 , a first cap layer 408 , and a first sidewall sub-410 . A first light doped drain (LDD) 412 and a first source/drain 414. In a preferred embodiment of the invention, the first gate dielectric layer 404 can be a dioxide layer or a high-k gate dielectric layer. The material of the high dielectric constant gate dielectric layer is, for example, a group consisting of tantalum nitride (SiN), yttrium oxynitride (Si〇N) or a metal oxide, wherein the metal oxide may be a rare earth metal oxide layer. For example, it includes hafnium oxide (Hf02), hafnium silicon oxide (HfSi〇4), hafhium silicon oxynitride (H(5)〇N), and oxidation! Oxide, Al2〇3), lanthanum oxide (La203), ianthanium aiumjnum 〇xjde (LaAi〇), oxidation group (tantalum oxide, Ta2〇5), zirconium oxide (Zr02), stone Zirconium silicon oxide (ZrSi04) ' (hafnium zirconium oxide,
HfZr〇)、锶鉍鈕氧化物(strontium bismuth tantalate，SrBi2Ta209， SBT)、錯鈦酸紹(lead zirc〇nate titanate，pbZrxTii x〇3, pzT)或鈦酸鋇 鰓(barium strontium titanate，BaxSrNxTi03，BST)等。第一閘極介電層 404亦可為一複合層，包含上述之任意組合，較佳地由下而上包含 二氧化矽層及高介電常數閘極介電層。第一犧牲閘極4〇6則例如是 夕曰曰石夕閘極，但也可以是由多晶石夕層、非晶石夕(am〇rph〇us別)或者錯 層所組合的複合閘極，或者，於其他實施例中，第一犧牲閘極4〇6 會具有傾斜側壁，而具有「上大下小」的形狀。在第一犧牲閘極4〇6 與第閘極介電層404之間可選擇性地增加一匹配層或後續製程用 201239992 的姓刻停土層，例如包含氮化矽層或金屬氮化物層如氮化鈦或氮化 鈕。第一蓋層408則是一選擇性膜層，例如是一氮化矽層或氧化層 或此兩者的複合層。第一側壁子410可為一複合膜層之結構，其可 包含咼溫氧化矽層(high temperature oxide，HTO)、氮化矽、氧化矽 或使用六氣二石夕烧(hexachlorodisilane，Si2Cl6)形成的氮化石夕 (HCD-SiN)。於一實施例中’第一側壁子41〇亦可部份或完全被移 除’使得接觸洞#刻停止層(contact etch stop layer ’ CESL) 306對於 第一導電型電晶體402以及第二導電型電晶體502能具有較佳應 力。第一輕摻雜汲極412以及第一源極/汲極414則以適當濃度的摻 質加以形成。 第一導電型電晶體502包含一第二閘極介電層504、一第二犧 牲閘極506、一第二蓋層508、一第二側壁子510、一第二輕摻雜汲 極512以及一第二源極/汲極514。第二導電型電晶體5〇2中各元件 的實施方式大致與第一導電型電晶體4〇2相同，在此不加以贅述。 此外，雖然第1圖中未明白緣出，但第一導電型電晶體402與第二 導電型電晶體502仍可包含其他半導體結構，例如金屬石夕化物層 (salicide)、以選擇性磊晶成長(seiective epitaxiaigr〇wth，SEG)而形成 具有六面體(hexagon，又叫sigmaS)或八面體(0Ctang0n)截面形狀的 源極/汲極或是其他保護層。在形成了第一導電型電晶體與第二 導電型電晶體502後，於基底300上依序形成一接觸洞蝕刻停止層 (contact etch stop layer，CESL) 306 與一内層介電層(inter_iayer dielectric，ILD)308，覆蓋在第一導電型電晶體4〇2與第二導電型電 8 201239992 晶體502上。於一實施例中，接觸洞蝕刻停止層3〇6具有一應力 (stress)，以作為一選擇性應力系統(seiective stfainscheme，sss);接 觸洞蝕刻停止層306可為單一層或複合層，在第一導電型電晶體4〇2 上施加壓縮應力而在第二導電型電晶體5〇2上施加伸張應力。 如第2圖所示，接著進行一平坦化製程，例如一化學機械平坦 化(chemical mechanical p〇lish，CMP)製程或者一回蝕刻製程或兩者 的組合，以依序移除部份的内層介電層3〇8、部份的接觸洞蝕刻停 止層306、部份的第一側壁子41〇、部份的第二側壁子51〇，並完全 移除第-蓋層408、第二蓋層5〇8,直到暴露出第一犧牲閘極4〇6 與第二犧牲閘極506之頂面。 如第3圖所示，接著於基底3〇〇上全面形成一遮罩層312以及 選擇性的一輔助層314。於本發明較佳實施例中，遮罩層312較佳 為-氣化鈦(TiN)層’而輔助層314較佳為一氧化石夕(別〇2)層。輔助 層314可提供後續圖案化之光阻層316較佳的附著力。於-實施例 遮罩層312之厚度大體上為5〇至15〇埃(&11吕也〇111)，較佳地為 埃，而誠3M術讀上㈣料，雛地為2〇埃為 仁不以上述為限。接著，於基底·上形成―第一圖案化光阻層 316，其覆蓋至少第二主動區域·。 接著’利用第—圖案化光阻層316為遮罩，以移除未被第一圖 案光阻層316覆蓋之遮罩層、輔助層別以及第一犧牲開極 201239992 ==:第一__層-之圖形轉印至遮罩層 L後再乂遮罩層312為遮罩來移除第一犧牲閘極概。然而，第 游广=極Γ6的材質例如為多晶石夕，而使用遮罩層312為遮罩來 移除下方之夕曰曰矽材質時，濕蝕刻雖有較佳蝕刻選擇比，能完美地 Γ彡絲他轉_構，咖㈣關存取記憶 體魏晶軸N龍晶狀_介面的半導 α在第=會發生如地，酬較編侧，但無法 =第—閘極介電層4G4上，而有馳制題，因此，-實施例 :的二乾除大部分第一犧牲閘極406後，再以濕#刻移除最 後的第一犧牲間極406，而停止在第一間極介電層404上。本發明 之另實施例在移除多晶教第一犧牲間極概時，提供了如下文 Z驟。請參考第4a圖至第7b圖，其中第4b圖與第7b圖所代表 、疋具有p型電晶體以及N型電晶體閘極接面的半導體結構，可分 :對應於第4a圖與第7a圖之橫剖面圖，而剖面係對應於第二犧牲 甲二506之位置。第4b圖與苐几圖之虛線！即代表了由多晶石夕所 ^成之接面位置，虛線1之右側代表P型半導體，左側代表N型半 導體。 如第4a ©與帛4b騎*，首先蹄—乾侧製似移除未被 第-圖案化光阻層316覆蓋的遮罩層312以及辅助層314，以及部 :的第一犧牲閘極4,接著如第5圖所示，對第—圖案化光阻316 仃一修整步驟__，例如使用氧氣(〇2)、臭氧(〇3)、喊化碳 201239992 (CF細化氫(HB_賴氣體以對第—_化光 =行修整，而鑛減少第一_光阻層31 ^側 圖案化光阻㈣大體上均勾地向内縮 使： 光阻層317。如第4b圖所示，第一圖案 ，一圖案化 :，閘極概之一侧，而進行光阻修整步驟後，第二光 會罪近第二犧牲閘極506之一側而形成了第二圖案化光阻層爪。 =Γ ’若以上視圖的角度來看，第二圖案化光阻層爪的 覆蓋面積會小於第—圖案化光阻層316的覆蓋面積1著如第6圖 所不’料二圖案化光阻層317為遮罩，移除未被第二圖案化光阻 :3圖:覆蓋之遮罩層312以及輔助層314。錢，如第乃圖以及第 几圖所示，移除第二圖案化光阻層317以及輔助層314後，進行一 祕刻步驟以徹底移除第一犧牲閘極娜。如第^圖所示，移除第 一犧牲閘極406後’會在第-導電型電晶體4〇2中形成一第一溝渠 (如_6，第二導電型電晶體5〇2之第二犧牲閘極由於被遮 罩層312覆蓋，因此並不會被移除；而如第几圖所示，經姓刻後的 多晶石夕侧壁可以鮮確地位於虛線〗處，且不會有側向侧的問題。 於本發明之-實施例中，移除了第—犧牲閘極4%後還可以 進行一退火(anneal)步驟。由於在形成進行如第2圖之平坦化製程 時’會移除部份的接觸洞触刻停止層306，進而破壞了接觸洞侧 停止層306原、先應有之應力。因此，在移除了第一犧牲問極4〇6後， 本發明還進行了-退火步驟以回復接觸洞姓刻停止層⑽6的應力狀 態。於本發贿佳實補巾，退火步_域峨料溫退火設備 201239992 或雷射退火設備進行5〇〇至度的加熱，或者在綱度至度 的環境下照射紫外光(UV)。此外，在移除了第一犧牲閘極後， 還可搭配保護第一溝渠416之下部的光阻(圖未示)進行-乾敍刻步 驟或祕刻步驟以移除位於第一溝渠416上部處的第一間隙壁 410 ’例如移除位於區域a中的第一間隙壁，以加大第一溝渠 416的上開口大小。 接著如第8圖所示，於基底3⑽上全面形成—p型功函數金屬 層318。P型功函數金屬層318會沿著第一溝渠416之表面共形形 成’但並不完全填滿第-溝渠416。於本實關巾，p型功函數金屬 層318為-滿足P型電晶體所需功函數要求的金屬，例如是錄⑽、 鈀㈣、雖〇、鍵_、鈒(Ir)、碲(Te)、銖(Re)、釘(Ru)、錢_、 鎢(W)、鉬(Mo);鎢、釕、鉬、钽⑽、鈦⑼的氮化物；鎢、鈕、 鈦的碳化物；或者TiAIN、TaAIN，但不以上述為限；p型功函數金 屬與遮罩層312可使用相同材料或不同材料，但較佳地p型功函數 金屬與遮罩層312對於同-種侧劑可具有接近的侧率，最佳的 P型功函數金屬與遮罩層312為同一種材料。 接著如第9圖所示’於基底3〇〇上形成一第三圖案化光阻層 320，其至少覆蓋於第一主動區域4〇〇。接著，如第1〇圖所示以 第三圖案化光阻層320為遮罩，移除未被第三圖案化光阻層32〇覆 蓋之P型功函數金屬層318以及遮罩層312，並暴露出第二犧牲閘 極506。最後，去除第三圖案化光阻層32〇。當然，此處利用第三圖 201239992 ”光P層320進行侧步驟時，亦可包含前文所述之修整步驟。 接著如第11圖所示，進行一乾侧製程及成麵刻製程以移 除第二犧牲閘極506,而在第二導電型電晶體5〇2中形成了第二溝 渠516。同樣的’在移除了第二犧牲問極後，可進行一退火製 程以回復接觸、·刻停止層3〇6之應力。同_，在移除了第二犧 牲閘極506後，亦可選擇性地搭配保護第二溝雜_)516之下部 的光阻(®未示)進行—乾侧轉或祕辭⑽雜位於第二溝 渠_也)516上部處的第二間隙壁51〇，擴大第二溝渠516上部的 開口大小。接著，於基底3〇〇上全面共形地形成一 N型功函數金屬 層322 〇N型功函數金屬$ 322 f共形地沿第二溝渠516之表面以 及第-溝渠416中P型功函數金屬層318之表面形成，但並不完全 填滿第二溝渠516以及第-溝渠416。於本發明較佳實施例中，n 型功函數金屬層322為一滿足N型電晶體所需功函數要求的金屬， 例如是鋁化鈦(titaniumaluminides，TiAl)、鋁化鍅(aluminum zirconium，ZrAl)、化鶴(aluminum tungsten, WA1)、銘化组(aiuminum tantalum’ TaAl)或I呂化給(aluminum hafnium，HfAl) ’ 但不以上述為 限。接著’為了避免N型功函數金屬層322被後續填入的金屬層326 侵入(spike)而影響其功能，本實施例還可以選擇性的在n型功函數 金屬層322以及金屬層326之間形成一阻障層324。於本發明較佳 實施例中，阻障層324為一金屬層，例如是一氮化鈦(TiN)層。最後， 於基底300上全面形成一低電阻的金屬層326。金屬層326會形成 於N型功函數金屬層322上(如有阻障層324’則是形成在阻障層324 13 201239992 上），並填滿第二溝渠516以及第一溝渠416。於本發明較佳實施例 中’金屬層326包含鋁(A1)、鈦(Ti)、鈕(Ta)、鎢(W)、鈮(Nb)、鉬(Mo)、 銅(Cu)、氮化鈦(TiN)、碳化鈦(TiC)、氮化钽(TaN)、鈦鎢(Ti/W)或鈦 與氮化鈦(Ti/TiN)等複合金屬層料，但不以此為限。 最後，如第12圖所示，進行一平坦化製程以同時移除第一溝渠 416以及第一溝渠516以外之P型功函數金屬層318、N型功函數金 屬層322以及金屬層326。如此一來，位於第一溝渠416内的p型 功函數金屬318、N型功函數金屬322、（阻障層324)以及金屬層326 會形成第一導電型電晶體402(P型電晶體)中的第一金屬閘極418， 且其功函數大致上介於4.8eV與5.2eV之間；而位於第二溝渠518 内的N型功函數金屬層322、（阻障層324)以及金屬層326會形成第 一導電型電晶體502(N型電晶體)中的第二金屬閘極Mg，且其功函 數大致上介於3.9eV與4.3eV之間。於本發明另一實施例中，可調 整P型功函數金屬層318以及N型功函數金屬層322之厚度，使其 發揮較佳的功函數功能。 在完成了第-金屬閘極418以及第二金屬閘極M8之後，後績 還可進行接觸插拾(咖叫_之製作，例如形成具有應力的接觸 插栓。或者’於接觸插栓形成前，還可以先完全移除内層介電層3〇6 以及接觸洞蝕刻停止層308，接著於基底3〇〇上再次形成至少另一 接觸洞I虫刻停止層（圖未示），並且藉由施加紫外線或者熱能之步 驟，以使新的接觸_刻停止層產生一應力，以分別提升第—導電 201239992 型電晶體402與第二導電型電晶體5〇2之效能。接著再次形成另一 内層介電層（圖未示），並於其中形成接觸插拴，此接觸插拴亦可具 有適當的應力。 值得注意的是，前述實施方式係先形成高介電常數之閘極介電 層為例(即high-K first製程），而本領域技藝人士應當了解，本發明 亦可在形成金屬閘極之前才形成高介電常數之閘極介電層（即 hlgh-Klast製程)’例如在第一溝渠内416形成p型功函數金屬層318 之刖’可先在第-溝渠4丨6之表面上形成高介電常數之閘極介電 層，然後再依序形成P型功函數金屬層318以及金屬層326等結構。 此位於第-溝渠416内之高介電常數之閘極介電層會和p型功函數 金屬層318 -樣具有u型剖面；同樣的，在第二溝渠516内形成n 型功函數金屬層322之前，也可先在第二溝渠516之表面上形成高 介電常數之閘極介電層，再依序形成N型功函數金屬層322以及金 屬層326等、纟β構’位於第二溝渠516之高介電常數之閘極介電層會 和Ν型功函數金屬層322 一樣具有〇型剖面。此外，若是採 撕謝崎電常數材質， 豪細种製作 步驟與第-實施例的第圖， ^祕.第2圖相同，可參考前文說明，在此 …而：了能夠清楚描述本發_實施方式，相同的元件 201239992 =相_元件符縣示。如第13 _心於進行平坦化製程後， =者於基底獅上全面形成—遮罩層阳、-輔助層別以及-第 -圖案化光阻層319，其中第一圖案化光阻層319會覆蓋至少第一 主動區域400。 接著如第Η圖所示，以第—圖案化光阻層319為遮罩，移除未 ==案化光阻層319覆蓋之遮罩層312、輔助層Μ以及部份 =:牲_ 。然後，移除第一圖案化光阻層319以及輔助 二—U疋全移除第二犧牲閉極506以形麟二溝渠516。接 虚、步驟以加強接__停止層308之應力。當然，此 匕光阻層319進行崎驟時，亦可包含第-實施 以擴I第驟。或者’亦可以進行—乾_步驟紐触刻步驟 擴大第一溝渠516上部的開口大小。 接著如第15圖所示，於其戍_ L入 、基底300上全面形成一 N型功函數金 人埴數金屬層322會沿著第二溝渠训之表面形成， 二溝渠516。接著如第16圖所示，於基底上 =一圖所 層321，其覆蓋至少於第二主動區轉。如 321 層21覆蓋之Μ功函數金屬層322以及遮罩層312，並暴 露出第一犧牲閘極4〇6,最後再移— θ ' 用第三圖案化雜層321Hm光阻層321。此處利 述之修整步驟。步驟時’亦可包含第一實施例所 201239992 如第18圖所TF ’進行一乾餘刻製程及/或腿刻製程以移除第 -犧牲閘極406’而在第—導電型電晶體4〇2中形成了第一溝渠 416於另-實施例中，可進行—乾姓刻步驟或醜刻步驟以擴大第 溝渠416上部的開口大小。或者進行一退火步驟以加強接觸洞姓 刻停止層308之應力。接著，於基底·上全面形成一 p型功函數 金屬層3射型功函數金屬層會沿第一溝渠仙之表面以及第 二溝渠516中N型功函數金屬層322之表面形成，但並不完全填滿 第-溝渠416以及第二溝渠。接著，可直接在p型功函數金屬 層318上形成低電阻的金屬層326。金屬層326形成於㈣功函數 金屬層322上，並填滿第二溝渠516以及第一溝渠4ΐό。 最後，如第19圖所示，進行一平坦化製程以同時移除位於第一 溝渠416以及第二溝渠516以外之的p型功函數金屬層318、N型 功函數金屬層322以及金屬層326。如此一來’位於第一溝準416 内的P型功函數金屬層318以及金屬層326會形成第一導電型電晶 體402(P型電晶體)中的第一金屬閘極418，且其功函數大致上介於 4.8eV與5.2eV之間；而位於第二溝渠518内的N型功函數金屬層 322、P型功函數金屬層318以及金屬層326會形成第二導電型電晶 體502(N型電晶體)中的第二金屬閘極518 ’且其功函數大致上介於 3.9eV 與 4.3eV 之間。 本實施例的特徵在於，因P型功函數金屬層318的材料亦可作 17 201239992 為良好的_|〇™) ’故;}：目較於第_實施例，本實施例毋需額外設 置阻障層324於N型功函數金屬層322以及金屬層326之間。p型 功函數金屬層318可同時扮演p型功函數金屬以及阻障層的角色。 如此-來’可減少第-電晶體4()2以及第二電晶體⑽中金屬層的 堆疊層數，以避免過多金屬層填洞，造成填洞能力科的問題。 同樣的，本實施例在完成了第一金屬閘極及第二金屬間 極518之後’後續可依據選擇性應力系_設計而形成具有應力接 觸插拴或者具有應力的接觸洞_停止層。林實關除了前述的 high-Kfirst製程’也可應用high Klast製程。 而於本發明另_實施财，在N型功函數金騎322形成後， 可立刻進行一鈍化製程，使得N型功函數金屬層322之表面形成一 鈍化結構。鈍化製程例如利用氨水對N型功函數金屬層322表面純 化’或者是物-氮化餘絲—氧化製程1在進行规化製程 後’即可以前述實關的方式，在N型功函數金屬層M2上形成p 型功函數金屬層318、金屬層326或是阻障層324。 综上而言’本發明提供了一種製作具有閘極之半導體元件的方 方法係先在第—溝渠或者第二溝針，分卿成1^功函數 第一功函數金屬層，最後再以低電阻之金屬層同時填滿 伊by/、X及第一溝渠，故可以避免習知技術金屬層(通常是紹)填 a不佳的問題。本發明亦只需要―次的金屬平坦化步驟，可有 201239992 ㈣良率。本發明亦考量到_功函數 贿入的_，因此提供了各種實施方式(形成轉層、=== ^直接^㈣函數金屬層為阻障層)來避免 =:第-溝渠以及第二溝渠時，使用了光阻修整;程另:及 、、寿玉白可增加產品的可靠度而提高產品良率。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均錢化娜飾本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第12圖所繪示為本發明第一實施例中製作具有金屬閘 極之半導體元件的方法之示意圖。 第13圖至第19圖所繪示為本發明第二實施例中製作具有金屬 閘極之半導體元件的方法之示意圖。 【主要元件符號說明】 3〇〇 基底 302 淺溝渠隔離 306 接觸洞餘刻停止層 308 層内介電層 312 遮罩層 314 輔助層 316 第一圖案化光阻層 406 第一犧牲閘極 408 第一蓋層 410 第一側壁子 412 第一輕摻雜汲極 414 第一源極/汲極 416 第一溝渠 418 第一金屬閘極 19 201239992 317 第二圖案化光阻層 500 第二主動區域 318 P型功函數金屬層 502 第二導電型電晶邀 319 第一圖案化光阻層 504 第二閘極介電層 320 第三圖案化光阻層 506 第二犧牲閘極 321 第三圖案化光阻層 508 第二蓋層 322 N型功函數金屬層 510 第二側壁子 324 阻障層 512 第二輕摻雜汲極 326 金屬層 514 第二源極/汲極 400 第一主動區域 516 第二溝渠 402 第一導電型電晶體 518 第二金屬閘極 404 第一閘極介電層HfZr〇), strontium bismuth tantalate (SrBi2Ta209, SBT), lead zirc〇nate titanate (pbZrxTii x〇3, pzT) or barium strontium titanate (BaxSrNxTi03, BST) )Wait. The first gate dielectric layer 404 can also be a composite layer comprising any combination of the above, preferably comprising a ruthenium dioxide layer and a high dielectric constant gate dielectric layer from bottom to top. The first sacrificial gate 4〇6 is, for example, a Xiqiaoshixi gate, but may also be a composite gate composed of a polycrystalline stone layer, an amorphous stone (am〇rph〇us) or a split layer. Alternatively, or in other embodiments, the first sacrificial gate 4〇6 will have a sloping sidewall with a "upper and lower" shape. Between the first sacrificial gate 4〇6 and the gate dielectric layer 404, a matching layer or a subsequent stop layer of 201239992 may be selectively added, for example, including a tantalum nitride layer or a metal nitride layer. Such as titanium nitride or nitride button. The first cap layer 408 is a selective film layer such as a tantalum nitride layer or an oxide layer or a composite layer of the two. The first sidewall 410 may be a composite film layer structure, which may include a high temperature oxide (HTO), a tantalum nitride, a hafnium oxide or a hexachlorodisilane (Si2Cl6). Nitride Xi (HCD-SiN). In one embodiment, 'the first sidewall 41 〇 can also be partially or completely removed' such that the contact etch stop layer CESL 306 is for the first conductivity type transistor 402 and the second conductivity The type of transistor 502 can have better stress. The first lightly doped drain 412 and the first source/drain 414 are formed with a suitable concentration of dopant. The first conductive type transistor 502 includes a second gate dielectric layer 504, a second sacrificial gate 506, a second cap layer 508, a second sidewall 510, and a second lightly doped drain 512. A second source/drain 514. The embodiment of each element in the second conductivity type transistor 5〇2 is substantially the same as that of the first conductivity type transistor 4〇2, and will not be described herein. In addition, although not shown in FIG. 1, the first conductive type transistor 402 and the second conductive type transistor 502 may still include other semiconductor structures, such as a metal salide, for selective epitaxy. Growth (seiective epitaxiaigr〇wth, SEG) to form a source/dippole or other protective layer having a hexagonal (also known as sigmaS) or octahedral (0Ctang0n) cross-sectional shape. After the first conductive type transistor and the second conductive type transistor 502 are formed, a contact etch stop layer (CESL) 306 and an inner dielectric layer (inter_iayer dielectric) are sequentially formed on the substrate 300. , ILD) 308, covering the first conductivity type transistor 4〇2 and the second conductivity type electricity 8 201239992 crystal 502. In one embodiment, the contact hole etch stop layer 3〇6 has a stress as a selective stress system (sss); the contact hole etch stop layer 306 may be a single layer or a composite layer. A compressive stress is applied to the first conductive type transistor 4〇2 to apply a tensile stress to the second conductive type transistor 5〇2. As shown in FIG. 2, a planarization process, such as a chemical mechanical planarization (CMP) process or an etchback process or a combination of the two is performed to sequentially remove portions of the inner layer. The dielectric layer 3〇8, a portion of the contact hole etch stop layer 306, a portion of the first sidewall spacer 41〇, a portion of the second sidewall spacer 51〇, and completely remove the first cap layer 408 and the second cap Layer 5 〇 8 until the top surface of the first sacrificial gate 4 〇 6 and the second sacrificial gate 506 are exposed. As shown in Fig. 3, a mask layer 312 and a selective auxiliary layer 314 are then formed over the substrate 3. In a preferred embodiment of the invention, the mask layer 312 is preferably a titanium oxide (TiN) layer and the auxiliary layer 314 is preferably a layer of a oxidized stone. The auxiliary layer 314 can provide better adhesion of the subsequently patterned photoresist layer 316. The thickness of the mask layer 312 is substantially 5 〇 to 15 〇 (<11 〇 〇 111), preferably angstroms, and Cheng 3M is read (4), and the ground is 2 angstroms. For Ren is not limited to the above. Next, a first patterned photoresist layer 316 is formed over the substrate, covering at least the second active region. Then using the first patterned photoresist layer 316 as a mask to remove the mask layer not covered by the first pattern photoresist layer 316, the auxiliary layer and the first sacrificial opening 201239992 ==: first __ The layer-pattern is transferred to the mask layer L and then the mask layer 312 is masked to remove the first sacrificial gate. However, the material of the first = = Γ Γ 例如 例如 例如 例如 例如 例如 例如 例如 , , , , , , , , , , = = = = = = = = = = = = = = = = = = = = = The mantle silk he turns _ structure, coffee (four) off access memory Wei Jing axis N dragon crystal _ interface semi-conducting α in the = will occur as the ground, the reward side, but can not = the first gate On the electrical layer 4G4, there is a problem, so, after the second embodiment removes most of the first sacrificial gate 406, the last first sacrificial pole 406 is removed by wet etching, and stops at The first dielectric layer 404 is on the first. Another embodiment of the present invention provides the following procedure when removing the polycrystalline teaching first sacrificial pole. Please refer to the 4th to 7th, wherein the semiconductor structure represented by the 4b and 7b, having a p-type transistor and an N-type transistor gate junction, can be divided into: corresponding to the 4a and the The cross-sectional view of Figure 7a, and the profile corresponds to the position of the second sacrificial armor 506. Figure 4b and the dotted line of the figure! That is, it represents the junction position of the polycrystalline stone, the right side of the dotted line 1 represents the P-type semiconductor, and the left side represents the N-type semiconductor. As in 4a © and 帛 4b riding*, first the hoof-dry side is like removing the mask layer 312 and the auxiliary layer 314 not covered by the first-patterned photoresist layer 316, and the first sacrificial gate 4 of the portion: Then, as shown in FIG. 5, the trimming step __ for the first patterned photoresist 316, for example, using oxygen (〇2), ozone (〇3), shouting carbon 201239992 (CF refining hydrogen (HB_) The gas is trimmed in the same manner as the first light, and the patterned photoresist (4) on the side of the first photoresist layer 31 is substantially inwardly contracted to: the photoresist layer 317. As shown in Fig. 4b The first pattern is patterned, one side of the gate is substantially one side, and after the photoresist trimming step, the second light sin approaches one side of the second sacrificial gate 506 to form a second patterned photoresist Layer claws. = Γ 'From the perspective of the above view, the coverage area of the second patterned photoresist layer will be smaller than the coverage area of the first patterned photoresist layer 316 as shown in Fig. 6. The photoresist layer 317 is a mask, and is removed from the second patterned photoresist: 3: covered mask layer 312 and auxiliary layer 314. Money, as shown in the first picture and the first few figures, remove the first Two pictures After the photoresist layer 317 and the auxiliary layer 314 are patterned, a secret step is performed to completely remove the first sacrificial gate. As shown in FIG. 4, after the first sacrificial gate 406 is removed, it will be in the first-conducting state. Forming a first trench in the transistor 4〇2 (eg, _6, the second sacrificial gate of the second conductivity type transistor 5〇2 is covered by the mask layer 312, and thus is not removed; As shown in the first few figures, the side wall of the polycrystalline stone after the surname can be clearly located at the dotted line, and there is no problem of the lateral side. In the embodiment of the present invention, the first An annealing step can be performed after 4% of the gate is sacrificed. Since the portion of the contact hole is removed to form the stop layer 306 during the planarization process as shown in FIG. 2, the contact hole side is destroyed. The stress of the stop layer 306 is the same as that of the first layer. Therefore, after the first sacrificial pole 4〇6 is removed, the present invention also performs an annealing step to restore the stress state of the contact hole stop layer (10)6. Bribe good coverage, annealing step _ domain 峨 material temperature annealing equipment 201239992 or laser annealing equipment for 5 〇〇 degree heating, Or ultraviolet light (UV) is irradiated in a moderate degree environment. In addition, after the first sacrificial gate is removed, the photoresist (not shown) protecting the lower portion of the first trench 416 may be used together with the dry The step of engraving or the step of secreting to remove the first spacer 410' located at the upper portion of the first trench 416, for example, removes the first spacer located in the region a to increase the size of the upper opening of the first trench 416. As shown in Fig. 8, a p-type work function metal layer 318 is formed entirely on the substrate 3 (10). The P-type work function metal layer 318 is conformed along the surface of the first trench 416 to form 'but not completely fill the first- Ditch 416. In the actual sealing towel, the p-type work function metal layer 318 is a metal that satisfies the required work function of the P-type transistor, for example, recording (10), palladium (four), although 〇, bond _, 鈒 (Ir), Te (Te), 铢 (Re), nail (Ru), money _, tungsten (W), molybdenum (Mo); tungsten, tantalum, molybdenum, niobium (10), titanium (9) nitride; tungsten, button, titanium carbonization Or TiAIN, TaAIN, but not limited to the above; p-type work function metal and mask layer 312 can use the same material or different materials, but preferably p-type work function metal A mask layer 312 for the same - kind of agent can have side closer to the side of, the optimum P type work function metal layer 312 is a mask with the same material. Next, as shown in Fig. 9, a third patterned photoresist layer 320 is formed on the substrate 3, which covers at least the first active region 4''. Next, as shown in FIG. 1 , the third patterned photoresist layer 320 is used as a mask, and the P-type work function metal layer 318 and the mask layer 312 not covered by the third patterned photoresist layer 32 are removed. A second sacrificial gate 506 is exposed. Finally, the third patterned photoresist layer 32 is removed. Of course, when the third step 201239992 "light P layer 320 is used to perform the side step, the trimming step described above may also be included. Then, as shown in FIG. 11, a dry side process and a face engraving process are performed to remove the first step. Two sacrificial gates 506, and a second trench 516 is formed in the second conductivity type transistor 5〇2. The same 'after removing the second sacrificial pole, an annealing process can be performed to restore contact, engrave Stopping the stress of layer 3〇6. Same as _, after removing the second sacrificial gate 506, it can also be selectively used to protect the photoresist under the second trench _) 516 (® not shown). The side turn or the secret (10) is located at the second gap 51〇 at the upper portion of the second trench _ 516, expanding the opening size of the upper portion of the second trench 516. Then, a N is formed conformally on the base 3〇〇 The work function metal layer 322 〇N type work function metal $ 322 f conformally formed along the surface of the second trench 516 and the surface of the P-type work function metal layer 318 in the first trench 416, but not completely filled second a trench 516 and a first trench 416. In a preferred embodiment of the invention, the n-type work function metal layer 322 is A metal that satisfies the required work function of an N-type transistor, such as titanium aluminide (TiAl), aluminum zirconium (ZrAl), aluminum tungsten (WA1), and aiuminum tantalum TaAl) or Ialumination (aluminum hafnium, HfAl)' is not limited to the above. Then, in order to prevent the N-type work function metal layer 322 from being infiltrated by the subsequently filled metal layer 326, its function is affected. The embodiment may also selectively form a barrier layer 324 between the n-type work function metal layer 322 and the metal layer 326. In a preferred embodiment of the invention, the barrier layer 324 is a metal layer, such as a nitrogen. Titanium (TiN) layer. Finally, a low-resistance metal layer 326 is formed on the substrate 300. The metal layer 326 is formed on the N-type work function metal layer 322 (if the barrier layer 324' is formed in the resist The barrier layer 324 13 201239992 is filled with the second trench 516 and the first trench 416. In the preferred embodiment of the invention, the metal layer 326 comprises aluminum (A1), titanium (Ti), button (Ta), tungsten. (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide (TiC), nitriding (TaN), titanium tungsten (Ti/W) or composite metal layer such as titanium and titanium nitride (Ti/TiN), but not limited thereto. Finally, as shown in Fig. 12, a planarization process is performed. At the same time, the first trench 416 and the P-type work function metal layer 318, the N-type work function metal layer 322, and the metal layer 326 other than the first trench 516 are removed. As a result, the p-type work function metal 318, the N-type work function metal 322, the (barrier layer 324), and the metal layer 326 located in the first trench 416 form the first conductive type transistor 402 (P-type transistor). The first metal gate 418, and its work function is substantially between 4.8 eV and 5.2 eV; and the N-type work function metal layer 322, (barrier layer 324) and metal layer in the second trench 518 326 forms a second metal gate Mg in the first conductivity type transistor 502 (N-type transistor), and its work function is substantially between 3.9 eV and 4.3 eV. In another embodiment of the invention, the thickness of the P-type work function metal layer 318 and the N-type work function metal layer 322 are adjusted to provide a better work function. After the completion of the first-metal gate 418 and the second metal gate M8, the post-production can also be contact-inserted (made of a coffee-like contact, for example, forming a contact plug with stress) or 'before the contact plug is formed The inner dielectric layer 3〇6 and the contact hole etch stop layer 308 may be completely removed first, and then at least another contact hole I insect stop layer (not shown) is formed on the substrate 3〇〇, and by The step of applying ultraviolet or thermal energy to cause a new contact-etching layer to generate a stress to respectively enhance the performance of the first conductive type 201239992 type transistor 402 and the second conductive type transistor 5〇2. Then another inner layer is formed again. A dielectric layer (not shown) is formed in the contact plug, and the contact plug can also have an appropriate stress. It is noted that the foregoing embodiment is to form a gate dielectric layer having a high dielectric constant. For example, the high-K first process, and those skilled in the art will appreciate that the present invention can also form a high dielectric constant gate dielectric layer (ie, hlgh-Klast process) before forming a metal gate. Inside the first ditch 416 forms a p-type work function metal layer 318' to form a high dielectric constant gate dielectric layer on the surface of the first trench 4丨6, and then sequentially forms a P-type work function metal layer 318 and metal The structure of layer 326 and the like. The high dielectric constant gate dielectric layer in the first trench 416 has a u-shaped cross section and the p-type work function metal layer 318. Similarly, a second n is formed in the second trench 516. Before the work function metal layer 322, a high dielectric constant gate dielectric layer may be formed on the surface of the second trench 516, and an N-type work function metal layer 322 and a metal layer 326, etc., 纟β may be sequentially formed. The gate dielectric layer of the high dielectric constant of the second trench 516 has the same 〇-shaped cross section as the Ν-type work function metal layer 322. In addition, if the material of the Xieqi electric constant is used, the manufacturing steps of the fine-grained species are The first embodiment of the first embodiment, the same as the second figure, can be referred to the foregoing description, here: and can clearly describe the present invention, the same element 201239992 = phase_component symbol. 13 _ After the flattening process, the = is formed on the base lion - cover a layer-positive layer, an auxiliary layer, and a first-patterned photoresist layer 319, wherein the first patterned photoresist layer 319 covers at least the first active region 400. Next, as shown in the first figure, the first patterned light The resist layer 319 is a mask, and the mask layer 312, the auxiliary layer layer, and the portion of the mask layer 319 which are not covered by the patterned photoresist layer 319 are removed. Then, the first patterned photoresist layer 319 is removed and the auxiliary layer is removed. The second sacrificial closed pole 506 is removed to form the second sacrificial closed pole 516. The virtual step is taken to strengthen the stress of the stop layer 308. Of course, when the tantalum photoresist layer 319 is subjected to a sacrificial step, The first implementation is included to expand the first step. Alternatively, the 'dry-step' step can be used to enlarge the opening size of the upper portion of the first trench 516. Then, as shown in Fig. 15, an N-type work function is formed on the substrate 300 to form an N-type work function. The metal layer 322 is formed along the surface of the second trench, and the second trench 516 is formed. Next, as shown in Fig. 16, on the substrate = a layer 321 of the image, which covers at least the second active region. For example, the 321 layer 21 covers the work function metal layer 322 and the mask layer 312, and exposes the first sacrificial gate 4〇6, and finally moves θ' with the third patterned impurity layer 321Hm photoresist layer 321. The finishing steps are described here. The step 'can also include the first embodiment 201239992, as shown in FIG. 18, TF' performs a dry process and/or a leg process to remove the first-sacrificial gate 406' in the first conductivity type transistor 4〇 In the second embodiment, the first trench 416 is formed. In another embodiment, a dry or etch step may be performed to enlarge the opening size of the upper portion of the trench 416. Alternatively, an annealing step is performed to reinforce the stress in the contact hole 308. Then, a p-type work function metal layer is formed on the substrate, and the metal function layer 3 is formed along the surface of the first trench and the surface of the N-type work function metal layer 322 in the second trench 516, but Completely fill the first-ditch 416 and the second ditch. Next, a low resistance metal layer 326 can be formed directly on the p-type work function metal layer 318. A metal layer 326 is formed on the (IV) work function metal layer 322 and fills the second trench 516 and the first trench 4ΐό. Finally, as shown in FIG. 19, a planarization process is performed to simultaneously remove the p-type work function metal layer 318, the N-type work function metal layer 322, and the metal layer 326 located outside the first trench 416 and the second trench 516. . Thus, the P-type work function metal layer 318 and the metal layer 326 located in the first trench 416 form the first metal gate 418 in the first conductive type transistor 402 (P-type transistor), and its work The function is substantially between 4.8 eV and 5.2 eV; and the N-type work function metal layer 322, the P-type work function metal layer 318, and the metal layer 326 located in the second trench 518 form a second conductivity type transistor 502 ( The second metal gate 518' in the N-type transistor) and its work function is substantially between 3.9 eV and 4.3 eV. The feature of this embodiment is that the material of the P-type work function metal layer 318 can also be 17 201239992 is a good _|〇TM); therefore: compared to the first embodiment, this embodiment requires no additional setting. The barrier layer 324 is between the N-type work function metal layer 322 and the metal layer 326. The p-type work function metal layer 318 can simultaneously function as a p-type work function metal and a barrier layer. Such a - can reduce the number of stacked layers of the metal layer in the first transistor 4 () 2 and the second transistor (10) to avoid excessive metal layer filling holes, causing problems in the hole filling ability section. Similarly, in this embodiment, after the first metal gate and the second metal interpole 518 are completed, a contact hole-stop layer having a stress contact plug or a stress may be formed according to the selective stress system design. In addition to the aforementioned high-Kfirst process, Lin Shiguan can also apply the high Klast process. In the present invention, after the formation of the N-type work function Jinqi 322, a passivation process can be performed immediately, so that the surface of the N-type work function metal layer 322 forms a passivation structure. The passivation process, for example, the surface purification of the N-type work function metal layer 322 by using ammonia water or the material-nitriding remaining wire-oxidation process 1 after the normalization process can be performed in the above-mentioned manner, in the N-type work function metal layer A p-type work function metal layer 318, a metal layer 326 or a barrier layer 324 is formed on M2. In summary, the present invention provides a method for fabricating a semiconductor device having a gate first in a first trench or a second trench, and is divided into a first work function metal layer of a work function, and finally low. The metal layer of the resistor fills the I/, X and the first trench at the same time, so that the problem of poor filling of the conventional metal layer (usually) can be avoided. The present invention also requires only a "secondary metal planarization step", which may have a 201239992 (four) yield. The present invention also considers the _work function bribe _, thus providing various embodiments (forming a layer, === ^ direct ^ (four) function metal layer as a barrier layer) to avoid =: the first ditch and the second ditch At the time, the use of photoresist trimming; Cheng another: and, Shou Yubai can increase the reliability of the product and improve product yield. The above is only the preferred embodiment of the present invention, and the scope of the present invention is covered by the average of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 through Fig. 12 are schematic views showing a method of fabricating a semiconductor device having a metal gate in the first embodiment of the present invention. 13 to 19 are schematic views showing a method of fabricating a semiconductor device having a metal gate in a second embodiment of the present invention. [Main component symbol description] 3〇〇 substrate 302 shallow trench isolation 306 contact hole residual stop layer 308 interlayer dielectric layer 312 mask layer 314 auxiliary layer 316 first patterned photoresist layer 406 first sacrificial gate 408 A cap layer 410 first sidewall sub-412 412 a first lightly doped drain 414 a first source/drain 416 a first trench 418 a first metal gate 19 201239992 317 a second patterned photoresist layer 500 a second active region 318 P-type work function metal layer 502 second conductivity type crystallization 319 first patterned photoresist layer 504 second gate dielectric layer 320 third patterned photoresist layer 506 second sacrificial gate 321 third patterned light Resistor layer 508 second cap layer 322 N-type work function metal layer 510 second sidewall sub-324 barrier layer 512 second lightly doped drain 326 metal layer 514 second source/drain 400 first active region 516 second Ditch 402 first conductivity type transistor 518 second metal gate 404 first gate dielectric layer