TWI520492B - Level shifter - Google Patents

Description

Converter

The invention relates to a pressure converter, in particular to a pressure converter capable of effectively reducing the layout area.

The converter can receive an input signal with a small signal range and convert it correspondingly into an output signal with a large signal range, which is an important building block in the interface circuit. For example, in a source driver chip that drives a display panel, the signal range of the original control signal in the chip can be 0 to 1.5 volts. However, when the output drives the source of the display panel, the required signal range may be To convert to expand to -5 to 0 volts. In order to convert between the two signal ranges, a transducer is required to convert the input signal from 0 to 1.5 volts to an output signal of -5 to 0 volts. Since this conversion is to convert the lower limit of the signal range of the input signal to the upper limit of the signal range of the output signal, it can be regarded as an operation of turning negative pressure.

Please refer to Fig. 1, which is a conventional converter 10 for achieving the purpose of turning negative pressure. In the prior art, if the input signal IN of the signal range of VSS to VPP is to be converted to the output signal OUT of the signal range between the voltages VSSL and VSS, the conventional converter 10 must undergo three stages. This type of negative pressure operation.

In the converter 10, the converter LS1, the inverter INV0 and the other converter LS2 respectively perform the above three-stage conversion, wherein the converter LS1 operating at the voltages VPP to VSSH performs the first re-rotation Pressing, the input signal IN is converted into the signal OUTa, the signal range of the signal OUTa is between the voltage VSSH to VPP; the inverter INV0 operating at the voltage VSS to VSSH performs the second re-rotation, The signal OUTa is converted into the signal OUTb, and the signal range of the signal OUTb falls between the voltages VSSH to VSS; finally, the voltage converter LS2 operating at the voltage VSS to VSSL performs the third re-transfer, converting the signal OUTb into The output signal OUT is such that the signal range of the output signal OUT can be between the voltages VSSL to VSS. In the above various conversions, for example, the voltages VSSL, VSSH, VSS, and VPP may be -5, -1.5, 0, and 1.5 volts, respectively, for converting the input signal IN of 0 to 1.5 volts to a negative voltage - Output signal OUT of 5 to 0 volts.

Although the lower limit of the signal range of the input signal IN is equivalent to the output signal The upper limit of the signal range of OUT (both voltage VSS), but in each of the above-mentioned re-conversions, when the converters LS1, LS2 and inverter INV0 are each converted between the input and output signal ranges, they can only be based on the same signal range. The upper or lower limit is converted. That is to say, the converter LS1 is converted based on the upper limit of the signal range of the input/output signal, and the upper limit of the signal range of the input signal IN is equal to the upper limit of the signal range of the signal OUTa (that is, the voltage VPP). The inverter INV0 is converted based on the lower limit of the common input-in signal range, and the lower limit of the signal range of the signal OUTa is equal to the lower limit of the signal range of the signal OUTb. The converter LS2 converts the same signal range upper limit between the input and output signals, and the signal range upper limit of the signal OUTb must be equal to the upper limit of the signal range of the output signal OUT. In combination with the above three-fold conversion, the conventional pressure converter 10 can achieve the purpose of turning negative pressure.

To further illustrate, the conventional converter 10 must be in three circuits (rotating One of the reasons for the triple conversion of LS1, LS2 and inverter INV0) is to ensure that the transistors in each circuit are not damaged by excessive voltage differences, in which the signal is converted to a larger signal range. At the same time, the voltage difference between the electrodes of each transistor also becomes large, which in turn affects the reliability of the transistor. However, since the total layout area of the converters LS1, LS2 and the inverter INV0 is also large under the triple conversion architecture, the overall layout area of the conventional converter 10 cannot be effectively reduced.

The invention relates to a pressure converter for converting an input signal into An output signal includes: a first N-type transistor having a first drain connected to a first supply voltage, a first gate receiving the input signal, and a first source connected to a first node a second N-type transistor having a second drain connected to the first supply voltage, a second gate receiving the inverted input signal, and a second source coupled to a second node; a first P-type transistor having a third source connected to the first node, a third drain connected to a third node, and a third gate connected to a fourth node; a second P-type a transistor having a fourth source connected to the second node, a fourth drain connected to the fourth node, and a fourth gate connected to the third node, wherein the third node generates the output signal And the fourth node generates the inverted output signal; a third N-type transistor having a fifth drain connected to the third node, a fifth source connected to a second supply voltage, and a a fifth gate is connected to the fourth node; a fourth N-type transistor has a sixth a pole connected to the fourth node, a sixth source connected to the second power voltage, and a sixth gate connected to the third node; and a switching unit connected to the third node and the fourth node During the switching of the input signal, the switching unit is controlled to be turned off according to the consistent energy signal for a period of time, thereby causing the output signal to be converted to a level; wherein the output signal has a first level The first power voltage is when the output signal has a second level, the second power voltage is greater than the second power voltage, and the second power voltage is a negative value.

The invention further provides a converter for converting an input signal An output signal includes: a first N-type transistor having a first drain connected to a first supply voltage, a first gate receiving the input signal, and a first source connected to a first a second N-type transistor having a second drain connected to the first supply voltage, a second gate receiving the inverted input signal, and a second source coupled to a second node; a third node generating the output signal; a fourth node generating the inverted output signal; a first P-type transistor having a third source connected to the first node and a third drain And a third gate is connected to the fourth node; a second P-type transistor has a fourth source connected to the first a second node, a fourth drain, and a fourth gate connected to the third node; a first switch connected between the third drain of the first P-type transistor and the third node, and Acting according to a first enable signal; a second switch connected between the fourth drain of the second P-type transistor and the fourth node, and acting according to the first enable signal; An N-type transistor having a fifth drain connected to the third node, a fifth source connected to a second supply voltage, and a fifth gate connected to the fourth node; a fourth N-type a crystal having a sixth drain connected to the fourth node, a sixth source connected to the second supply voltage, and a sixth gate connected to the third node; and a switching unit coupled to the first Between the three nodes and the fourth node, when the second signal is used to switch the level according to the second enable signal, the switch unit is controlled to be turned off after a period of time, and then the output signal is converted into a level; When the output signal has a first level, the first power voltage is When the output signal has a second level, the second power voltage is greater than the second power voltage, the second power voltage is a negative value, and the first switch and the second switch relationship are The first consistent energy signal is turned off during the time period.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

10‧‧‧Transducer

20‧‧‧Transducer

30‧‧‧Transducer

40‧‧‧Transducer

LS1, LS2‧‧‧Transducer

INV0‧‧‧Inverter

MN1, MN2, MN3, MN4‧‧‧N type transistor

MP1, MP2‧‧‧P type transistor

SW, SW1, SW2, SW3, SW4‧‧‧ switch

VSS‧‧‧First supply voltage

IN‧‧‧ input signal

INB‧‧‧Inverting input signal

a, b, c, d‧‧‧ first to fourth nodes

EN‧‧‧Enable signal

OUT‧‧‧ output signal

OUTB‧‧‧Inverted output signal

VSSL‧‧‧second supply voltage

Figure 1 shows a conventional pressure converter.

2A and 2B are diagrams showing a first embodiment of the converter of the present invention and related signal diagrams.

Figure 3 is a view showing a second embodiment of the pressure converter of the present invention.

Figure 4 is a view showing a third embodiment of the pressure converter of the present invention.

The invention utilizes a few transistors to form a converter and achieve the purpose of turning negative pressure. Furthermore, the following embodiments use an input signal (IN) and an inverting input. The signal (INB) has a signal range of 1.5 volts to 0 volts, and the output signal (OUT) and inverted output signal (OUTB) have a signal range of 0 volts to -5 volts. However, the invention is not limited thereto.

Please refer to FIG. 2A and FIG. 2B, which are illustrated as the turn of the present invention. A first embodiment of the press and its associated signal schematic. The converter 20 includes: a switch (SW), a first N-type transistor (MN1), a second N-type transistor (MN2), a third N-type transistor (MN3), and a fourth N-type transistor. (MN4), a first P-type transistor (MP1), and a second P-type transistor (MP2). Furthermore, the first supply voltage (VSS) is 0 volts and the second supply voltage (VSSL) is -5 volts.

The first N-type transistor (MN1) is connected to the first supply voltage (VSS); the gate receives the input signal (IN); the source is connected to the first node (a). The second N-type transistor (MN2) is connected to the first supply voltage (VSS), the gate receives the inverted input signal (INB), and the source is connected to the second node (b).

The first P-type transistor (MP1) source is connected to the first node (a); The pole is connected to the third node (c); the gate is connected to the fourth node (d). The second P-type transistor (MP2) source is connected to the second node (b); the drain is connected to the fourth node (d); and the gate is connected to the third node (c).

The third N-type transistor (MN3) is connected to the third node (c); the source The pole is connected to the second supply voltage (VSSL); the gate is connected to the fourth node (d). The fourth N-type transistor (MN4) is connected to the fourth node (d); the source is connected to the second supply voltage (VSSL); and the gate is connected to the third node (c).

a switch (SW) is connected between the third node (c) and the fourth node (d), and The switch is controlled by an enable signal (EN). Furthermore, the third node (c) can generate an output signal (OUT), and the fourth node (d) can generate an inverted output signal (OUTB).

When the converter 20 is in the first steady state, the enable signal (EN) is disabled, the input signal (IN) is 1.5 volts; the inverting input signal (INB) is 0 volts; The signal (OUT) is a first supply voltage (VSS) of 0 volts; the inverted output signal (OUTB) is a second supply voltage (VSSL) of -5 volts. Obviously, in the first steady state, the switch (SW) is open; the first N The type transistor (MN1) turns on; the second N-type transistor (MN2) does not turn off; the first P-type transistor (MP1) turns on; the second P-type transistor ( MP2) does not turn off; the third N-type transistor (MN3) does not turn off; the fourth N-type transistor (MN4) turns on.

When the input signal (IN) is converted from 1.5 volts to 0 volts, and the inverting input When the input signal (INB) is converted from 0 volts to 1.5 volts, the enable signal (EN) is disabled, the output signal (OUT) is maintained at 0 volts of the first supply voltage (VSS), and the inverted output signal ( OUTB) maintains a second supply voltage (VSSL) at -5 volts.

At this time, the switch (SW) is open; the first N-type transistor (MN1) and the first P-type transistor (MP1) are not turned off, so that the first node (a) is floating (floating); the second N-type transistor (MN2) is turned off (turn off) And the second P-type transistor (MP2) is not turned off, so that the second node (b) is a first power supply voltage (VSS) of 0 volts; the third N-type transistor (MN3) is not turned on (turn off) ); the fourth N-type transistor (MN4) turns on.

Next, enable the switch briefly with the enable signal (EN) After (SW), disable again, causing the switch (SW) to briefly close and open. During a short period of time during which the switch (SW) is turned off, due to a short circuit between the third node (c) and the fourth node (d), charge sharing is performed such that the third node (c) and the fourth node (d) The voltage changes to the same voltage (for example -2.5 volts). That is, the voltage of the third node (c) drops from the first supply voltage (VSS) of 0 volts to -2.5 volts, and the voltage of the fourth node (d) rises from the second supply voltage (VSSL) of -5 volts to -2.5 volts.

Since the voltage at the third node (c) drops to -2.5 volts, it will make The second P-type transistor (MP2) turns on and the fourth N-type transistor (MN4) does not turn off, so that the voltage of the fourth node (d) continues to rise from -2.5 volts to 0 volts. A power supply voltage (VSS). Furthermore, the third N-type transistor (NM3) turns on due to the voltage increase of the fourth node (d), so that the voltage of the third node (c) continues to drop from -2.5 volts to -5 volts. Second supply voltage (VSSL).

As can be seen from the above description, when the input signal (IN) is converted by 1.5 volts When it is 0 volts, and the inverting input signal (INB) is converted from 0 volts to 1.5 volts, as long as the enable signal (EN) is used to control the switch (SW) to briefly close and open, it can be smooth. Ground the voltage of the third node (c) from a first supply voltage (VSS) of 0 volts to a second supply voltage (VSSL) of -5 volts, and let the voltage of the fourth node (d) be -5 volts The second supply voltage (VSSL) changes to a first supply voltage (VSS) of 0 volts. After that, it is maintained in the second stable state.

When the converter 20 is in the second stable state, the enable signal (EN) For disable, the input signal (IN) is 0 volts; the inverting input signal (INB) is 1.5 volts; the output signal (OUT) is -5 volts of the second supply voltage (VSSL); the inverted output signal ( OUTB) is the first supply voltage (VSS) of 0 volts. Obviously, in the second steady state, the switch (SW) is open; the first N-type transistor (MN1) is not turned off; the second N-type transistor (MN2) is turned on (turn) On); the first P-type transistor (MP1) is not turned off; the second P-type transistor (MP2) is turned on; the third N-type transistor (MN3) is turned on; The four N-type transistors (MN4) are not turned off.

When the input signal (IN) is converted from 0 volts to 1.5 volts, and the inverted input When the input signal (INB) is converted from 1.5 volts to 0 volts, the enable signal (EN) is disabled, the output signal (OUT) is maintained at -5 volts of the second supply voltage (VSSL), and the inverted output signal (OUTB) maintains the first supply voltage (VSS) at 0 volts.

At this time, the switch (SW) is open; the first N-type transistor (MN1) turns off, and the first P-type transistor (MP1) does not turn off, so that the first node (a) is a first power supply voltage (VSS) of 0 volts; the second N-type power The crystal (MN2) and the second P-type transistor (MP2) are not turned off, so that the second node (b) is floating; the third N-type transistor (MN3) is turned on (turn on ); the fourth N-type transistor (MN4) does not turn off.

Next, enable the switch briefly with the enable signal (EN) After (SW), disable again, causing the switch (SW) to briefly close and open. In a short period of time during which the switch (SW) is turned off, due to a short circuit between the third node (c) and the fourth node (d), charging sharing is caused to make the third The voltage at node (c) and fourth node (d) changes to the same voltage (eg, -2.5 volts). That is, the voltage of the third node (c) rises from -5 volts of the second power supply voltage (VSSL) to -2.5 volts; and the voltage of the fourth node (d) drops by the first supply voltage (VSS) of 0 volts. To -2.5 volts.

Since the voltage of the fourth node (d) drops to -2.5 volts, the first P-type transistor (MP1) will be turned on and the third N-type transistor (MN3) will not be turned off, so that The voltage at the three node (c) continues to rise from -2.5 volts to a first supply voltage (VSS) of zero volts. Furthermore, the fourth N-type transistor (NM4) turns on due to the voltage increase of the third node (c), so that the voltage of the fourth node (d) continues to drop from -2.5 volts to -5 volts. Second supply voltage (VSSL).

As can be seen from the above description, when the input signal (IN) is converted from 0 volts to 1.5 volts, and the inverted input signal (INB) is converted from 1.5 volts to 0 volts, the switch (SW) is controlled by the enable signal (EN). A short close (open) and open (open), you can smoothly increase the voltage of the third node (c) from the second supply voltage (VSSL) of -5 volts to the first supply voltage of 0 volts (VSS) And let the voltage of the fourth node (d) be changed from a first supply voltage (VSS) of 0 volts to a second supply voltage (VSSL) of -5 volts. After that, it is maintained in the first stable state.

With the change of the input signal (IN) and the inverted input signal (INB), it is only necessary to use the enable signal (EN) to control the switch (SW) to briefly close and open. The converter 20 can be varied between a first steady state and a second steady state.

As shown in FIG. 2B, it is the first stable state before time point t1. At time t1, the input signal (IN) and the inverted input signal (INB) start to shift the level. Since the enable signal (EN) is temporarily enabled between the time point t1 and the time point t2, the output signal (OUT) and the inverted output signal (OUTB) are smoothly switched to the level. And between the time point t2 and the time point t3 is a second stable state. Among them, the enable signal (EN) is briefly enabled for a time period of about 10 ns to 40 ns.

Similarly, at time t3, the input signal (IN) and the inverted input signal (INB) start to shift the level. Since the time point t3 and the time point t4, the enable letter The number (EN) is temporarily enabled (enable), so that the output signal (OUT) and the inverted output signal (OUTB) are smoothly converted to the level. And after the time point t4, it returns to the first stable state. Among them, the enable signal (EN) is briefly enabled for a time period of about 10 ns to 40 ns.

According to an embodiment of the invention, the switch (SW) can be implemented using a transistor, such as an N-type transistor. When the enable signal (EN) is 0 volts, the switch (SW) is enabled and turned off; when the enable signal (EN) is -5 volts, the switch (SW) is disabled and disconnected (open).

As apparent from the above description, the first embodiment of the present invention includes only a total of seven transistors for the switch, so that the overall layout area of the converter 20 can be greatly reduced. Furthermore, the converter 20 of the present invention further utilizes an enable signal (EN) to control the switch (SW) to achieve the purpose of the negative pressure of the converter 20.

Please refer to FIG. 3, which illustrates a second embodiment of the pressure converter of the present invention. The voltage converter 30 includes: a first switch (SW1), a second switch (SW2), a first N-type transistor (MN1), a second N-type transistor (MN2), and a third N-type transistor (MN3). a fourth N-type transistor (MN4), a first P-type transistor (MP1), and a second P-type transistor (MP2). Furthermore, the first supply voltage (VSS) is 0 volts and the second supply voltage (VSSL) is -5 volts.

The first N-type transistor (MN1) to the fourth N-type transistor (MN4), the connection relationship between the first P-type transistor (MP1) and the second P-type transistor (MP2) is the same as that of the first embodiment, I won't go into details here.

The difference from the first embodiment is that the first switch (SW1) and the second switch (SW2) are simultaneously controlled by the enable signal (EN). And, the first end of the first switch (SW1) is connected to the third node (c), the second end is connected to the second power voltage (VSSL); the second end of the second switch (SW2) is connected to the first Four nodes (d), the second end is connected to the second supply voltage (VSSL).

In the second embodiment, the connection relationship of the converter 30 is such that when the input signal (IN) and the inverted input signal (INB) are converted to their levels, the first switch (SW1) and the second switch are made by the enable signal (EN). The switch (SW2) is briefly turned off and then turned on, so that the voltages of the third node (c) and the fourth node (d) are changed to the same power. Pressure (eg -5 volts). In this way, the output signal (OUT) and the inverted output signal (OUTB) can be smoothly converted to the level.

For example, when the pressure converter 30 is in the first steady state (steady State), the enable signal (EN) is disabled, the input signal (IN) is 1.5 volts; the inverting input signal (INB) is 0 volts; the output signal (OUT) is 0 volts of the first supply voltage (VSS); the inverted output signal (OUTB) is a second supply voltage (VSSL) of -5 volts. That is, in the first stable state, the first switch (SW1) and the second switch (SW2) are both open; the first N-type transistor (MN1) is turned on; the second N The type transistor (MN2) does not turn off; the first P-type transistor (MP1) turns on; the second P-type transistor (MP2) does not turn off; the third N-type transistor (MN3) does not turn off; the fourth N-type transistor (MN4) turns on.

When the input signal (IN) is converted from 1.5 volts to 0 volts, and the inverting input When the input signal (INB) is converted from 0 volts to 1.5 volts, the enable signal (EN) is disabled, the output signal (OUT) is maintained at 0 volts of the first supply voltage (VSS), and the inverted output signal ( OUTB) maintains a second supply voltage (VSSL) at -5 volts.

At this time, both the first switch (SW1) and the second switch (SW2) are disconnected. (open); neither the first N-type transistor (MN1) nor the first P-type transistor (MP1) is turned off, so that the first node (a) is floating (floating); the second N-type The transistor (MN2) turns off and the second P-type transistor (MP2) does not turn off, such that the second node (b) is a first supply voltage (VSS) of 0 volts; the third N-type The transistor (MN3) is not turned off; the fourth N-type transistor (MN4) is turned on.

Then, enable the first enable with the enable signal (EN) The switch (SW1) and the second switch (SW2) are again disabled (disable), so that the first switch (SW1) and the second switch (SW2) are simultaneously closed and opened simultaneously. In a short period of time during which the first switch (SW1) and the second switch (SW2) are turned off, the voltages of the third node (c) and the fourth node (d) will be changed to the same voltage (for example, -5 volts) Two power supply voltage (VSSL)).

Since the voltage at the third node (c) drops to -5 volts, it will make the second The P-type transistor (MP2) turns on and the fourth N-type transistor (MN4) does not turn off, so that the voltage of the fourth node (d) continues to rise from -5 volts to the first of 0 volts. Power supply voltage (VSS). Furthermore, the third N-type transistor (NM3) turns on because the voltage of the fourth node (d) rises, so that the voltage of the third node (c) is maintained at the second supply voltage of -5 volts ( VSSL). After that, it is maintained in the second stable state.

And in the same way, can change from the second stable state to the first stable state. I will not repeat them here.

Of course, in the second embodiment, the first switch (SW1) and the second switch The second end of (SW2) is not limited to being connected to a second supply voltage (VSSL). The second ends of the first switch (SW1) and the second switch (SW2) may also be connected to a reference voltage, for example between -2.5 volts and -5 volts, which may also allow the converter 30 to operate normally. .

To prevent the switch from causing a short-circuit current when it is turned off, causing excessive Energy consumption. The present invention proposes a third embodiment of a voltage converter for preventing the generation of a short circuit current.

Please refer to FIG. 4, which is a third embodiment of the present invention. Example. The difference from the second embodiment is that a third switch (SW3) is connected between the first P-type transistor (MP1) and the third node (c), and the second P-type transistor (MP2) is connected to the drain. A fourth switch (SW4) is connected between the fourth node (c). Furthermore, the first switch (SW1) and the second switch (SW2) are controlled by the first enable signal (EN1); the third switch (SW3) and the fourth switch (SW4) are controlled by the second enablement Signal (EN2). The first switch (SW1) and the second switch (SW2) are controlled by the first enable signal (EN1), and the first enable signal (EN1) operates in the same manner as the second embodiment. The detailed action principle will not be described again.

According to a third embodiment of the present invention, at the first switch (SW1) and During the time period in which the second switch (SW2) is closed, the third switch (SW3) and the fourth switch (SW4) are opened (open), and the third switch (SW3) and the fourth switch (SW4) are in the It will be closed at other times. In other words, when the first switch (SW1) and the second switch (SW2) are turned off, and the third node (c) is short-circuited with the fourth node (d) During the cycle, the third switch (SW3) and the fourth switch (SW4) are opened. Therefore, it is possible to prevent a short-circuit current from being generated between the first power supply voltage (VSSL) and the third node (c) or between the first power supply voltage (VSSL) and the fourth node (d).

Furthermore, using the same action mode, the third switch (SW3) and the third The four switches (SW4) are applied to the first embodiment, as well as preventing the occurrence of short-circuit current. That is, in the converter of the first embodiment, a third switch (SW3) is added between the first P-type transistor (MP1) and the third node (c), and the second P-type transistor is added. A fourth switch (SW4) is added between the (MP2) drain and the fourth node (c). The detailed action principle will not be described again.

It can be seen from the above description that the pressure converter of the present invention is composed only of a small number of transistors, so that the overall layout area of the pressure converter can be greatly reduced, and the purpose of turning the negative pressure of the pressure converter is achieved.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

20‧‧‧Transducer

MN1, MN2, MN3, MN4‧‧‧N type transistor

MP1, MP2‧‧‧P type transistor

SW‧‧ switch

VSS‧‧‧First supply voltage

IN‧‧‧ input signal

INB‧‧‧Inverting input signal

a, b, c, d‧‧‧ first to fourth nodes

EN‧‧‧Enable signal

OUT‧‧‧ output signal

OUTB‧‧‧Inverted output signal

VSSL‧‧‧second supply voltage

Claims (12)

A voltage converter for converting an input signal into an output signal, comprising: a first N-type transistor having a first drain connected to a first supply voltage, a first gate receiving the input signal, and a first source is coupled to a first node; a second N-type transistor having a second drain connected to the first supply voltage, a second gate receiving the inverted input signal, and a first The two sources are connected to a second node; a first P-type transistor having a third source connected to the first node, a third drain connected to a third node, and a third gate connection a fourth P-type transistor having a fourth source connected to the second node, a fourth drain connected to the fourth node, and a fourth gate connected to the third a node, wherein the third node generates the output signal, and the fourth node generates the inverted output signal; a third N-type transistor having a fifth drain connected to the third node, a fifth source The pole is connected to a second power voltage, and a fifth gate is connected to the fourth section a fourth N-type transistor having a sixth drain connected to the fourth node, a sixth source connected to the second supply voltage, and a sixth gate connected to the third node; a switching unit is connected between the third node and the fourth node. When the input signal is converted to a level, the switching unit is controlled to be turned off according to the consistent energy signal for a period of time, thereby causing the output signal to be converted. a first power supply voltage when the output signal has a first level, the second power supply voltage when the output signal has a second level, the first power supply voltage being greater than the second power supply voltage And the second supply voltage is a negative value. The pressure converter of claim 1, wherein the first power source The voltage is 0 volts. The converter of claim 1, wherein the time period is between 10 ns and 40 ns. The switch device of claim 1, wherein the switch unit further includes a first switch connected between the third node and the fourth node for turning off the time period according to the enable signal. And causing the third node to have the same voltage as the fourth node. The converter of claim 1, wherein the switch unit comprises: a first switch connected between the third node and a reference voltage; and a second switch connected to the fourth node Between the reference voltages, wherein the first switch and the second switch turn off the time period according to the enable signal, so that the voltages of the third node and the fourth node are the reference voltages. The converter of claim 5, wherein the reference voltage is the second power voltage. A voltage converter for converting an input signal into an output signal, comprising: a first N-type transistor having a first drain connected to a first supply voltage and a first gate receiving the input signal And a first source connected to a first node; a second N-type transistor having a second drain connected to the first supply voltage, a second gate receiving the inverted input signal, and a second source is coupled to a second node; a third node is configured to generate the output signal; a fourth node, generating the inverted output signal; a first P-type transistor having a third source connected to the first node, a third drain, and a third gate connected to the first a fourth P-type transistor having a fourth source connected to the second node, a fourth drain, and a fourth gate connected to the third node; a first switch connected to Between the third drain of the first P-type transistor and the third node, and according to a first enable signal; a second switch connected to the fourth drain of the second P-type transistor And the fourth node, and according to the first enable signal; a third N-type transistor having a fifth drain connected to the third node, and a fifth source connected to a second power source a voltage, and a fifth gate connected to the fourth node; a fourth N-type transistor having a sixth drain connected to the fourth node, a sixth source connected to the second supply voltage, and a sixth gate is connected to the third node; and a switch unit is connected to the third node and the fourth node When the switching signal is turned on according to a second enabling signal, the switching unit is controlled to be turned off after a period of time, and then the output signal is switched to a level; wherein the output signal has a first When the level is the first power voltage, the output signal has a second level, the second power voltage, the first power voltage is greater than the second power voltage, the second power voltage is a negative value, and the The first switch and the second open relationship are disconnected during the time period according to the first enable signal. The converter of claim 7, wherein the first power supply voltage is 0 volts. The converter of claim 7, wherein the time period is between 10 ns and 40 ns. The switch device of claim 7, wherein the switch unit further includes a third switch connected between the third node and the fourth node for controlling the second enable signal according to the second enabler signal The switching unit turns off the time period, and then has the same voltage according to the third node and the fourth node. The converter of claim 7, wherein the switch unit comprises: a third switch connected between the third node and a reference voltage; and a fourth switch connected to the fourth node and Between the reference voltages, wherein the third switch and the fourth switch turn off the time period according to the second enable signal, so that the voltages of the third node and the fourth node are the reference voltage. The converter of claim 11, wherein the reference voltage is the second power voltage.