TWI513050B - 發光二極體封裝結構的製造方法 - Google Patents

發光二極體封裝結構的製造方法 Download PDF

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TWI513050B
TWI513050B TW102112080A TW102112080A TWI513050B TW I513050 B TWI513050 B TW I513050B TW 102112080 A TW102112080 A TW 102112080A TW 102112080 A TW102112080 A TW 102112080A TW I513050 B TWI513050 B TW I513050B
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emitting diode
light emitting
package structure
diode package
manufacturing
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TW201442288A (zh
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Hsing Fen Lo
Lung Hsin Chen
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Advanced Optoelectronic Tech
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483Containers
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009Pre-treatment of the bonding area
    • H01L2224/8003Reshaping the bonding area in the bonding apparatus, e.g. flattening the bonding area
    • H01L2224/80047Reshaping the bonding area in the bonding apparatus, e.g. flattening the bonding area by mechanical means, e.g. severing, pressing, stamping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/181Encapsulation
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
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    • H01L2933/0033Processes relating to semiconductor body packages
    • H01L2933/005Processes relating to semiconductor body packages relating to encapsulations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008Processes
    • H01L2933/0033Processes relating to semiconductor body packages
    • H01L2933/0066Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52Encapsulations
    • H01L33/54Encapsulations having a particular shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

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Description

發光二極體封裝結構的製造方法
本發明涉及一種半導體的製造方法,尤其涉及一種發光二極體封裝結構的製造方法。
相比傳統的發光源,發光二極體(Light Emitting Diode,LED)具有重量輕、體積小、污染低、壽命長等優點,其作為一種新型的發光源,已經被越來越多地應用到各領域當中,如路燈、交通燈、信號燈、射燈及裝飾燈等。
為了適應習知發光設備(例如顯示器等)日益微型化的趨勢,作為新一代光源的發光二極體封裝結構也被要求能夠向日益微型化的趨勢發展。然而一般的發光二極體封裝結構通常包括基板、在該基板上形成的金屬層及承載於基板上並與金屬層電連接的發光二極體晶片。並且,為了增強發光二極體封裝結構的發出光線的會聚效率,通常在基板上還形成反射杯,該種發光二極體封裝結構在體積尺寸上可縮減的空間較小,因此通常無法滿足當今產業微型化的趨勢。
有鑒於此,有必要提供一種微型化的發光二極體封裝結構的製造方法。
一種發光二極體封裝結構的製造方法,包括以下步驟: 提供一金屬板,在所述金屬板上形成複數相互絕緣的電極板,在每相鄰兩電極板上電連接一發光二極體晶片;在金屬板上形成複數凸起部,每一凸起部環繞一發光二極體晶片並形成容置發光二極體晶片的凹陷部;在凸起部下方形成覆蓋電極板的基板;形成封裝層於凹陷部內;以及切割基板形成複數個發光二極體封裝結構。
本發明採用先在電極板上連接發光二極體晶片,再將電極板衝壓形成多個環繞發光二極體晶片的凸起部,然後再形成包覆電極板的基板,能夠盡可能的減小發光二極體封裝結構的體積,能夠通過控制凸起部的形成位置從而控制發光二極體封裝結構的寬度,通過控制基板的厚度以及凸起部的高度來從而控制發光二極體封裝結構的厚度,從而利於體積較小的發光二極體封裝結構的製造。並且,由於發光二極體晶片是收容於金屬板的凹陷部內的,因此金屬板本身就可充當反射結構使用,無需再在基板或金屬板上再形成反射杯,從而使發光二極體封裝結構的厚度較小。
100‧‧‧發光二極體封裝結構
10‧‧‧基板
11‧‧‧上表面
12‧‧‧下表面
20‧‧‧電極板
21‧‧‧第一電極板
22‧‧‧第二電極板
23‧‧‧絕緣帶
24‧‧‧凹陷部
25‧‧‧凸起部
30‧‧‧發光二極體晶片
40‧‧‧封裝層
50‧‧‧金屬板
60‧‧‧模具
61‧‧‧下模
611‧‧‧凸塊
62‧‧‧上模
621‧‧‧凹槽
622‧‧‧容置口
圖1為本發明實施方式的發光二極體封裝結構的製造方法製成的發光二極體封裝結構的剖視示意圖。
圖2至圖8為本發明實施方式的發光二極體封裝結構的製造過程中各步驟示意圖。
如圖1所示,本發明實施方式提供的發光二極體封裝結構100包括 基板10、形成於基板10內的兩電極板20、承載於兩電極板20上並與兩電極板20電性連接的發光二極體晶片30,以及封裝該發光二極體晶片30的封裝層40。
所述基板10包括上表面11和相對設置的下表面12。所述電極板20分為第一電極板21和第二電極板22。該第一、第二電極板21、22之間夾設一絕緣帶23,以使第一、第二電極板21、22相互絕緣。該電極板20在基板10的中央與基板10的下表面12齊平並形成一凹陷部24,電極板20自凹陷部24的外邊緣向上延伸至基板10的上表面11從而形成一凸起部25,該凸起部25環繞凹陷部24。所述發光二極體晶片30容置於該凹陷部24中,並與第一、第二電極板21、22電連接。在本實施方式中,該發光二極體晶片30是採用覆晶方式連接於電極板20上。電極板20還可自凸起部25的週邊進一步向基板10的下表面12延伸,並自基板10的下表面12向基板10的側面水準延伸,從而從基板10的側面外露。所述電極板20上直接形成凸起部25,不但作為發光二極體封裝結構100的電極使用,還可以作為反射杯使用,能夠使發光二極體封裝結構100在尺寸上有所縮減。
所述封裝層40填充於電極板20的凹陷部24中,並將發光二極體晶片30覆蓋。該封裝層40的上表面與基板10的上表面11平齊,從而使該發光二極體封裝結構100整體呈平板狀,並具有較小的厚度。
本發明還提供上述發光二極體封裝結構100的製造方法,以下,將結合其他附圖對該製造方法進行詳細說明。
請參考圖2,提供一平板狀金屬板50,並在金屬板50上形成複數 相互間隔的絕緣帶23,從而使該金屬板50分隔成複數相互絕緣的電極板20,在每相鄰兩電極板20上電連接一發光二極體晶片30。
請參閱圖3至圖5,提供一模具60將金屬板50夾設其中,在金屬板50上衝壓出複數凸起部25,每一凸起部25環繞一發光二極體晶片30並形成容置發光二極體晶片30的凹陷部24。該模具60包括一下模61和一上模62。下模61的上表面間隔設有複數凸塊611,上模62的下表面對應下模61的凸塊611處形成有複數凹槽621,該凸塊611凸起的高度與凹槽621凹陷的深度大致相等。上模62的下表面對應每一發光二極體晶片30形成有複數容置口622,該容置口622為自上模62的下表面向內凹陷形成的另一組凹槽,該容置口622的深度大於電極板20上的發光二極體晶片30裝設的高度,以使上模62和下模61相互衝壓時,避免上模62與發光二極體晶片30接觸,以防止將發光二極體晶片30壓壞。操作時,將金屬板50放置於下模61和上模62之間,並將每一凸塊611和凹槽621面對金屬板50且一一對應放置;向相對方向移動下模61和上模62,從而使下模61的凸塊611將金屬板50向上衝壓至上模62的凹槽621中進而形成凸起部25;最後再移除模具60。
請參閱圖6,形成覆蓋電極板20的基板10。在該步驟中,可採用壓模的方式將高分子材料從電極板20的上方和下方壓合,從而使高分子材料填充於電極板20的凸起部25的下方,同時填充於相鄰兩發光二極體晶片30的相鄰兩凸起部25之間。該基板10包括上表面11和下表面12,該上表面11與電極板20的凸起部25的頂面相平齊,從而使凸起部25裸露於頂面,以便電極板20可以從頂部與其他元件電性連接。該下表面12與電極板20的凹陷部24的底面相平 齊,從而使凹陷部24裸露於底面,以便電極板20可以從底部與其他元件電性連接。此種結構不但能盡可能的減小封裝結構的厚度尺寸,還能夠使該封裝結構連入電路的方式多樣化,提高該結構在運用時的靈活性和可調性。當然,在其他實施方式中,所述基板10可將電極板20的凸起部25的上表面和凹陷部24的下表面完全包覆於內,僅使電極板20從基板10的側面伸出,從而使電極板20的側面可以與其他元件電性連接。
請參閱圖7,形成封裝層40於凹陷部24內。該封裝層40內可包含螢光粉。該封裝層40的上表面可以與基板10的上表面相平齊,從而使整個封裝結構呈薄型平板狀。
請參閱圖8,切割基板10以形成多個發光二極體封裝結構100,如圖1所示。在該步驟中,可沿相鄰兩發光二極體晶片30的相鄰兩凸起部25之間的區域進行切割,從而使每一發光二極體封裝結構100均包括環繞一發光二極體晶片30的凸起部25。此外,由於凸起部25的材料為金屬,因此環繞每一發光二極體晶片30的凸起部25的內壁具有較高的光反射特性,可提高發光二極體封裝結構100的出光效率。
本發明採用先在電極板20上連接發光二極體晶片30,再將電極板20衝壓形成多個環繞發光二極體晶片30的凸起部25,然後再形成包覆電極板20的基板10,能夠盡可能的減小發光二極體封裝結構100的體積,能夠通過控制凸起部25的形成位置從而控制發光二極體封裝結構100的寬度,通過控制基板10的厚度以及凸起部25的高度來從而控制發光二極體封裝結構100的厚度。且由於凸起部25為金屬材質,其環繞發光二極體晶片30設置,能夠有效的反 射發光二極體晶片30發出的光線,提高發光二極體封裝結構100的出光效率。另外,由於發光二極體晶片30是直接裝設在衝壓前的電極板20上,因此在平板狀的電極板20上進行發光二極體晶片30的固晶打線或覆晶操作具有較大的操作空間,避免了因為操作空間狹小(例如在反射杯內固晶操作)而對操作更為苛刻以及容易產生不良品的缺失。
本發明之技術內容及技術特點已揭示如上,然而熟悉本項技術之人士仍可能基於本發明之教示及揭示而作種種不背離本發明精神之替換及修飾。因此,本發明之保護範圍應不限於實施例所揭示者,而應包括各種不背離本發明之替換及修飾,並為以下之申請專利範圍所涵蓋。
100‧‧‧發光二極體封裝結構
10‧‧‧基板
11‧‧‧上表面
12‧‧‧下表面
20‧‧‧電極板
21‧‧‧第一電極板
22‧‧‧第二電極板
23‧‧‧絕緣帶
24‧‧‧凹陷部
25‧‧‧凸起部
30‧‧‧發光二極體晶片
40‧‧‧封裝層

Claims (10)

  1. 一種發光二極體封裝結構的製造方法,包括以下步驟:提供一金屬板,在所述金屬板上形成複數相互絕緣的電極板,在每相鄰兩電極板上電連接一發光二極體晶片;在金屬板上形成複數凸起部,每一凸起部環繞一發光二極體晶片並形成容置發光二極體晶片的凹陷部;在凸起部下方形成覆蓋電極板的基板;形成封裝層於凹陷部內;以及切割基板形成複數個發光二極體封裝結構。
  2. 如申請專利範圍第1項所述的發光二極體封裝結構的製造方法,其中,所述在金屬板上形成複數凸起部的步驟包括以下步驟:提供一模具,所述模具包括下模和上模,所述下模的上表面形成複數凸塊,所述上模的下表面形成複數凹槽,所述凸塊和凹槽一一對應;將金屬板夾設於上模和下模中;上模和下模相互衝壓金屬板形成複數凸起部;以及移除模具。
  3. 如申請專利範圍第2項所述的發光二極體封裝結構的製造方法,其中,所述上模的下表面還形成有複數容置口,每一容置口與每一發光二極體晶片一一對應,每一容置口的深度大於發光二極體晶片裝設的高度。
  4. 如申請專利範圍第1項所述的發光二極體封裝結構的製造方法,其中,所述形成覆蓋電極板的基板的步驟是採用壓模的方式將高分子材料填充於電極板的凸起部內以及相鄰兩發光二極體晶片的相鄰兩凸起部之間。
  5. 如申請專利範圍第4項所述的發光二極體封裝結構的製造方法,其中,所 述基板包括上表面,所述上表面與電極板的凸起部的頂面平齊。
  6. 如申請專利範圍第4項所述的發光二極體封裝結構的製造方法,其中,所述基板包括下表面,所述下表面與電極板的凹陷部的底面平齊。
  7. 如申請專利範圍第1項所述的發光二極體封裝結構的製造方法,其中,所述基板包括上表面和下表面,所述上表面和下表面將電極板的凸起部的頂面和凹陷部的底面包覆於內。
  8. 如申請專利範圍第1項所述的發光二極體封裝結構的製造方法,其中,所述形成封裝層於凹陷部內的步驟中封裝層與基板的上表面平齊。
  9. 如申請專利範圍第8項所述的發光二極體封裝結構的製造方法,其中,所述封裝層內包括螢光粉。
  10. 如申請專利範圍第1項所述的發光二極體封裝結構的製造方法,其中,所述切割基板形成複數個發光二極體封裝結構的步驟是沿相鄰兩發光二極體晶片的相鄰兩凸起部之間的區域進行切割。
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